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1/*
2 * This file is part of the sigrok-firmware-fx2lafw project.
3 *
4 * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
5 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <eputils.h>
23#include <fx2regs.h>
24#include <fx2macros.h>
25#include <delay.h>
26#include <gpif.h>
27#include <fx2lafw.h>
28#include <gpif-acquisition.h>
29
30__bit gpif_acquiring;
31
32static void gpif_reset_waveforms(void)
33{
34 int i;
35
36 /* Reset WAVEDATA. */
37 AUTOPTRSETUP = 0x03;
38 AUTOPTRH1 = 0xe4;
39 AUTOPTRL1 = 0x00;
40 for (i = 0; i < 128; i++)
41 EXTAUTODAT1 = 0;
42}
43
44static void gpif_setup_registers(void)
45{
46 /* TODO. Value probably irrelevant, as we don't use RDY* signals? */
47 GPIFREADYCFG = 0;
48
49 /* Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs. */
50 GPIFCTLCFG = 0;
51
52 /* When GPIF is idle, tri-state the data bus. */
53 /* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
54 GPIFIDLECS = (0 << 0);
55
56 /* When GPIF is idle, set CTL0-CTL5 to 0. */
57 GPIFIDLECTL = 0;
58
59 /*
60 * Map index 0 in WAVEDATA to FIFORD. The rest is assigned too,
61 * but not used by us.
62 *
63 * GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index,
64 * [3:2] = FIFOWR index, [1:0] = FIFORD index
65 */
66 GPIFWFSELECT = (0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0);
67
68 /* Contains RDY* pin values. Read-only according to TRM. */
69 GPIFREADYSTAT = 0;
70
71 /* Make GPIF stop on transaction count not flag. */
72 EP2GPIFPFSTOP = (0 << 0);
73}
74
75static void gpif_init_addr_pins(void)
76{
77 /*
78 * Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of
79 * PORTC[7:0] and PORTE[7]), and output an initial address (zero).
80 * TODO: Probably irrelevant, the 56pin FX2 has no ports C and E.
81 */
82 PORTCCFG = 0xff; /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */
83 OEC = 0xff; /* Configure PORTC[7:0] as outputs. */
84 PORTECFG |= 0x80; /* Set PORTE[7] as alt. func. (GPIFADR[8]). */
85 OEE |= 0x80; /* Configure PORTE[7] as output. */
86 SYNCDELAY();
87 GPIFADRL = 0x00; /* Clear GPIFADR[7:0]. */
88 SYNCDELAY();
89 GPIFADRH = 0x00; /* Clear GPIFADR[8]. */
90}
91
92static void gpif_init_flowstates(void)
93{
94 /* Clear all flowstate registers, we don't use this functionality. */
95 FLOWSTATE = 0;
96 FLOWLOGIC = 0;
97 FLOWEQ0CTL = 0;
98 FLOWEQ1CTL = 0;
99 FLOWHOLDOFF = 0;
100 FLOWSTB = 0;
101 FLOWSTBEDGE = 0;
102 FLOWSTBHPERIOD = 0;
103}
104
105void gpif_init_la(void)
106{
107 /*
108 * Setup the FX2 in GPIF master mode, using the internal clock
109 * (non-inverted) at 48MHz, and using async sampling.
110 */
111 IFCONFIG = 0xee;
112
113 /* Abort currently executing GPIF waveform (if any). */
114 GPIFABORT = 0xff;
115
116 /* Setup the GPIF registers. */
117 gpif_setup_registers();
118
119 /* Reset WAVEDATA. */
120 gpif_reset_waveforms();
121
122 /* Initialize GPIF address pins, output initial values. */
123 gpif_init_addr_pins();
124
125 /* Initialize flowstate registers (not used by us). */
126 gpif_init_flowstates();
127
128 /* Reset the status. */
129 gpif_acquiring = FALSE;
130}
131
132static void gpif_make_delay_state(volatile BYTE *pSTATE, uint8_t delay, uint8_t output)
133{
134 /*
135 * DELAY
136 * Delay cmd->sample_delay clocks.
137 */
138 pSTATE[0] = delay;
139
140 /*
141 * OPCODE
142 * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=0, DP=0
143 */
144 pSTATE[8] = 0;
145
146 /*
147 * OUTPUT
148 * CTL[0:5]=output
149 */
150 pSTATE[16] = output;
151
152 /*
153 * LOGIC FUNCTION
154 * Not used.
155 */
156 pSTATE[24] = 0x00;
157}
158
159static void gpif_make_data_dp_state(volatile BYTE *pSTATE)
160{
161 /*
162 * BRANCH
163 * Branch to IDLE if condition is true, back to S0 otherwise.
164 */
165 pSTATE[0] = (7 << 3) | (0 << 0);
166
167 /*
168 * OPCODE
169 * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=1, DP=1
170 */
171 pSTATE[8] = (1 << 1) | (1 << 0);
172
173 /*
174 * OUTPUT
175 * CTL[0:5]=0
176 */
177 pSTATE[16] = 0x00;
178
179 /*
180 * LOGIC FUNCTION
181 * Evaluate if the FIFO full flag is set.
182 * LFUNC=0 (AND), TERMA=6 (FIFO Flag), TERMB=6 (FIFO Flag)
183 */
184 pSTATE[24] = (6 << 3) | (6 << 0);
185}
186
187bool gpif_acquisition_start(const struct cmd_start_acquisition *cmd)
188{
189 int i;
190 volatile BYTE *pSTATE = &GPIF_WAVE_DATA;
191
192 /* Ensure GPIF is idle before reconfiguration. */
193 while (!(GPIFTRIG & 0x80));
194
195 /* Configure the EP2 FIFO. */
196 if (cmd->flags & CMD_START_FLAGS_SAMPLE_16BIT)
197 EP2FIFOCFG = bmAUTOIN | bmWORDWIDE;
198 else
199 EP2FIFOCFG = bmAUTOIN;
200 SYNCDELAY();
201
202 /* Set IFCONFIG to the correct clock source. */
203 if (cmd->flags & CMD_START_FLAGS_CLK_48MHZ) {
204 IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmASYNC |
205 bmGSTATE | bmIFGPIF;
206 } else {
207 IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmASYNC |
208 bmGSTATE | bmIFGPIF;
209 }
210
211 /* Populate delay states. */
212 if ((cmd->sample_delay_h == 0 && cmd->sample_delay_l == 0) ||
213 cmd->sample_delay_h >= 6)
214 return false;
215
216 if (cmd->flags & CMD_START_FLAGS_CLK_CTL2) {
217 uint8_t delay_1, delay_2 = cmd->sample_delay_l;
218
219 /* We need a pulse where the CTL1/2 pins alternate states. */
220 if (cmd->sample_delay_h) {
221 for (i = 0; i < cmd->sample_delay_h; i++)
222 gpif_make_delay_state(pSTATE++, 0, 0x06);
223 } else {
224 delay_1 = delay_2 / 2;
225 delay_2 -= delay_1;
226 gpif_make_delay_state(pSTATE++, delay_1, 0x06);
227 }
228
229 /* sample_delay_l is always != 0 for the supported rates. */
230 gpif_make_delay_state(pSTATE++, delay_2, 0x00);
231 } else {
232 for (i = 0; i < cmd->sample_delay_h; i++)
233 gpif_make_delay_state(pSTATE++, 0, 0x00);
234
235 if (cmd->sample_delay_l != 0)
236 gpif_make_delay_state(pSTATE++, cmd->sample_delay_l, 0x00);
237 }
238
239 /* Populate S1 - the decision point. */
240 gpif_make_data_dp_state(pSTATE++);
241
242 /* Execute the whole GPIF waveform once. */
243 gpif_set_tc16(1);
244
245 /* Perform the initial GPIF read. */
246 gpif_fifo_read(GPIF_EP2);
247
248 /* Update the status. */
249 gpif_acquiring = TRUE;
250
251 return true;
252}
253
254void gpif_poll(void)
255{
256 /* Detect if acquisition has completed. */
257 if (gpif_acquiring && (GPIFTRIG & 0x80)) {
258 /* Activate NAK-ALL to avoid race conditions. */
259 FIFORESET = 0x80;
260 SYNCDELAY();
261
262 /* Switch to manual mode. */
263 EP2FIFOCFG = 0;
264 SYNCDELAY();
265
266 /* Reset EP2. */
267 FIFORESET = 0x02;
268 SYNCDELAY();
269
270 /* Return to auto mode. */
271 EP2FIFOCFG = bmAUTOIN;
272 SYNCDELAY();
273
274 /* Release NAK-ALL. */
275 FIFORESET = 0x00;
276 SYNCDELAY();
277
278 gpif_acquiring = FALSE;
279 }
280}