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1 | // Copyright (C) 2009 Ubixum, Inc. | |
2 | // | |
3 | // This library is free software; you can redistribute it and/or | |
4 | // modify it under the terms of the GNU Lesser General Public | |
5 | // License as published by the Free Software Foundation; either | |
6 | // version 2.1 of the License, or (at your option) any later version. | |
7 | // | |
8 | // This library is distributed in the hope that it will be useful, | |
9 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | // Lesser General Public License for more details. | |
12 | // | |
13 | // You should have received a copy of the GNU Lesser General Public | |
14 | // License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
15 | ||
16 | /*! \file | |
17 | * | |
18 | * This is the basic header/register file for working with the cypress fx2 | |
19 | * (cyc768013) and variants 8051 chipset. It contains the special function | |
20 | * register definitions as well as the special configuration registers | |
21 | * addresses. | |
22 | * | |
23 | * The TRM for the fx2 chip contains the full documentation for what each of | |
24 | * these registers do. | |
25 | * | |
26 | * */ | |
27 | ||
28 | ||
29 | /** \mainpage FX2LIB Documentation | |
30 | * \verbinclude README | |
31 | **/ | |
32 | ||
33 | /** \example fw.c | |
34 | * The firmware framework allows for easily beginning a new firware project. | |
35 | **/ | |
36 | ||
37 | #ifndef FX2REGS_H | |
38 | #define FX2REGS_H | |
39 | ||
40 | #include "fx2types.h" | |
41 | ||
42 | __xdata __at 0xE400 volatile BYTE GPIF_WAVE_DATA; | |
43 | __xdata __at 0xE480 volatile BYTE RES_WAVEDATA_END; | |
44 | ||
45 | // General Configuration | |
46 | ||
47 | __xdata __at 0xE600 volatile BYTE CPUCS; ///< Control & Status | |
48 | __xdata __at 0xE601 volatile BYTE IFCONFIG; ///< Interface Configuration | |
49 | __xdata __at 0xE602 volatile BYTE PINFLAGSAB; ///< FIFO FLAGA and FLAGB Assignments | |
50 | __xdata __at 0xE603 volatile BYTE PINFLAGSCD; ///< FIFO FLAGC and FLAGD Assignments | |
51 | __xdata __at 0xE604 volatile BYTE FIFORESET; ///< Restore FIFOS to default state | |
52 | __xdata __at 0xE605 volatile BYTE BREAKPT; ///< Breakpoint | |
53 | __xdata __at 0xE606 volatile BYTE BPADDRH; ///< Breakpoint Address H | |
54 | __xdata __at 0xE607 volatile BYTE BPADDRL; ///< Breakpoint Address L | |
55 | __xdata __at 0xE608 volatile BYTE UART230; ///< 230 Kbaud clock for T0,T1,T2 | |
56 | __xdata __at 0xE609 volatile BYTE FIFOPINPOLAR; ///< FIFO polarities | |
57 | __xdata __at 0xE60A volatile BYTE REVID; ///< Chip Revision | |
58 | __xdata __at 0xE60B volatile BYTE REVCTL; ///< Chip Revision Control | |
59 | ||
60 | // Endpoint Configuration | |
61 | ||
62 | __xdata __at 0xE610 volatile BYTE EP1OUTCFG; ///< Endpoint 1-OUT Configuration | |
63 | __xdata __at 0xE611 volatile BYTE EP1INCFG; ///< Endpoint 1-IN Configuration | |
64 | __xdata __at 0xE612 volatile BYTE EP2CFG; ///< Endpoint 2 Configuration | |
65 | __xdata __at 0xE613 volatile BYTE EP4CFG; ///< Endpoint 4 Configuration | |
66 | __xdata __at 0xE614 volatile BYTE EP6CFG; ///< Endpoint 6 Configuration | |
67 | __xdata __at 0xE615 volatile BYTE EP8CFG; ///< Endpoint 8 Configuration | |
68 | __xdata __at 0xE618 volatile BYTE EP2FIFOCFG; ///< Endpoint 2 FIFO configuration | |
69 | __xdata __at 0xE619 volatile BYTE EP4FIFOCFG; ///< Endpoint 4 FIFO configuration | |
70 | __xdata __at 0xE61A volatile BYTE EP6FIFOCFG; ///< Endpoint 6 FIFO configuration | |
71 | __xdata __at 0xE61B volatile BYTE EP8FIFOCFG; ///< Endpoint 8 FIFO configuration | |
72 | __xdata __at 0xE620 volatile BYTE EP2AUTOINLENH; ///< Endpoint 2 Packet Length H (IN only) | |
73 | __xdata __at 0xE621 volatile BYTE EP2AUTOINLENL; ///< Endpoint 2 Packet Length L (IN only) | |
74 | __xdata __at 0xE622 volatile BYTE EP4AUTOINLENH; ///< Endpoint 4 Packet Length H (IN only) | |
75 | __xdata __at 0xE623 volatile BYTE EP4AUTOINLENL; ///< Endpoint 4 Packet Length L (IN only) | |
76 | __xdata __at 0xE624 volatile BYTE EP6AUTOINLENH; ///< Endpoint 6 Packet Length H (IN only) | |
77 | __xdata __at 0xE625 volatile BYTE EP6AUTOINLENL; ///< Endpoint 6 Packet Length L (IN only) | |
78 | __xdata __at 0xE626 volatile BYTE EP8AUTOINLENH; ///< Endpoint 8 Packet Length H (IN only) | |
79 | __xdata __at 0xE627 volatile BYTE EP8AUTOINLENL; ///< Endpoint 8 Packet Length L (IN only) | |
80 | __xdata __at 0xE630 volatile BYTE EP2FIFOPFH; ///< EP2 Programmable Flag trigger H | |
81 | __xdata __at 0xE631 volatile BYTE EP2FIFOPFL; ///< EP2 Programmable Flag trigger L | |
82 | __xdata __at 0xE632 volatile BYTE EP4FIFOPFH; ///< EP4 Programmable Flag trigger H | |
83 | __xdata __at 0xE633 volatile BYTE EP4FIFOPFL; ///< EP4 Programmable Flag trigger L | |
84 | __xdata __at 0xE634 volatile BYTE EP6FIFOPFH; ///< EP6 Programmable Flag trigger H | |
85 | __xdata __at 0xE635 volatile BYTE EP6FIFOPFL; ///< EP6 Programmable Flag trigger L | |
86 | __xdata __at 0xE636 volatile BYTE EP8FIFOPFH; ///< EP8 Programmable Flag trigger H | |
87 | __xdata __at 0xE637 volatile BYTE EP8FIFOPFL; ///< EP8 Programmable Flag trigger L | |
88 | __xdata __at 0xE640 volatile BYTE EP2ISOINPKTS; ///< EP2 (if ISO) IN Packets per frame (1-3) | |
89 | __xdata __at 0xE641 volatile BYTE EP4ISOINPKTS; ///< EP4 (if ISO) IN Packets per frame (1-3) | |
90 | __xdata __at 0xE642 volatile BYTE EP6ISOINPKTS; ///< EP6 (if ISO) IN Packets per frame (1-3) | |
91 | __xdata __at 0xE643 volatile BYTE EP8ISOINPKTS; ///< EP8 (if ISO) IN Packets per frame (1-3) | |
92 | __xdata __at 0xE648 volatile BYTE INPKTEND; ///< Force IN Packet End | |
93 | __xdata __at 0xE649 volatile BYTE OUTPKTEND; ///< Force OUT Packet End | |
94 | ||
95 | // Interrupts | |
96 | ||
97 | __xdata __at 0xE650 volatile BYTE EP2FIFOIE; ///< Endpoint 2 Flag Interrupt Enable | |
98 | __xdata __at 0xE651 volatile BYTE EP2FIFOIRQ; ///< Endpoint 2 Flag Interrupt Request | |
99 | __xdata __at 0xE652 volatile BYTE EP4FIFOIE; ///< Endpoint 4 Flag Interrupt Enable | |
100 | __xdata __at 0xE653 volatile BYTE EP4FIFOIRQ; ///< Endpoint 4 Flag Interrupt Request | |
101 | __xdata __at 0xE654 volatile BYTE EP6FIFOIE; ///< Endpoint 6 Flag Interrupt Enable | |
102 | __xdata __at 0xE655 volatile BYTE EP6FIFOIRQ; ///< Endpoint 6 Flag Interrupt Request | |
103 | __xdata __at 0xE656 volatile BYTE EP8FIFOIE; ///< Endpoint 8 Flag Interrupt Enable | |
104 | __xdata __at 0xE657 volatile BYTE EP8FIFOIRQ; ///< Endpoint 8 Flag Interrupt Request | |
105 | __xdata __at 0xE658 volatile BYTE IBNIE; ///< IN-BULK-NAK Interrupt Enable | |
106 | __xdata __at 0xE659 volatile BYTE IBNIRQ; ///< IN-BULK-NAK interrupt Request | |
107 | __xdata __at 0xE65A volatile BYTE NAKIE; ///< Endpoint Ping NAK interrupt Enable | |
108 | __xdata __at 0xE65B volatile BYTE NAKIRQ; ///< Endpoint Ping NAK interrupt Request | |
109 | __xdata __at 0xE65C volatile BYTE USBIE; ///< USB Int Enables | |
110 | __xdata __at 0xE65D volatile BYTE USBIRQ; ///< USB Interrupt Requests | |
111 | __xdata __at 0xE65E volatile BYTE EPIE; ///< Endpoint Interrupt Enables | |
112 | __xdata __at 0xE65F volatile BYTE EPIRQ; ///< Endpoint Interrupt Requests | |
113 | __xdata __at 0xE660 volatile BYTE GPIFIE; ///< GPIF Interrupt Enable | |
114 | __xdata __at 0xE661 volatile BYTE GPIFIRQ; ///< GPIF Interrupt Request | |
115 | __xdata __at 0xE662 volatile BYTE USBERRIE; ///< USB Error Interrupt Enables | |
116 | __xdata __at 0xE663 volatile BYTE USBERRIRQ; ///< USB Error Interrupt Requests | |
117 | __xdata __at 0xE664 volatile BYTE ERRCNTLIM; ///< USB Error counter and limit | |
118 | __xdata __at 0xE665 volatile BYTE CLRERRCNT; ///< Clear Error Counter EC[3..0] | |
119 | __xdata __at 0xE666 volatile BYTE INT2IVEC; ///< Interupt 2 (USB) Autovector | |
120 | __xdata __at 0xE667 volatile BYTE INT4IVEC; ///< Interupt 4 (FIFOS & GPIF) Autovector | |
121 | __xdata __at 0xE668 volatile BYTE INTSETUP; ///< Interrupt 2&4 Setup | |
122 | ||
123 | // Input/Output | |
124 | ||
125 | __xdata __at 0xE670 volatile BYTE PORTACFG; ///< I/O PORTA Alternate Configuration | |
126 | __xdata __at 0xE671 volatile BYTE PORTCCFG; ///< I/O PORTC Alternate Configuration | |
127 | __xdata __at 0xE672 volatile BYTE PORTECFG; ///< I/O PORTE Alternate Configuration | |
128 | __xdata __at 0xE678 volatile BYTE I2CS; ///< Control & Status | |
129 | __xdata __at 0xE679 volatile BYTE I2DAT; ///< Data | |
130 | __xdata __at 0xE67A volatile BYTE I2CTL; ///< I2C Control | |
131 | __xdata __at 0xE67B volatile BYTE XAUTODAT1; ///< Autoptr1 MOVX access | |
132 | __xdata __at 0xE67C volatile BYTE XAUTODAT2; ///< Autoptr2 MOVX access | |
133 | ||
134 | #define EXTAUTODAT1 XAUTODAT1 | |
135 | #define EXTAUTODAT2 XAUTODAT2 | |
136 | ||
137 | // USB Control | |
138 | ||
139 | __xdata __at 0xE680 volatile BYTE USBCS; ///< USB Control & Status | |
140 | __xdata __at 0xE681 volatile BYTE SUSPEND; ///< Put chip into suspend | |
141 | __xdata __at 0xE682 volatile BYTE WAKEUPCS; ///< Wakeup source and polarity | |
142 | __xdata __at 0xE683 volatile BYTE TOGCTL; ///< Toggle Control | |
143 | __xdata __at 0xE684 volatile BYTE USBFRAMEH; ///< USB Frame count H | |
144 | __xdata __at 0xE685 volatile BYTE USBFRAMEL; ///< USB Frame count L | |
145 | __xdata __at 0xE686 volatile BYTE MICROFRAME; ///< Microframe count, 0-7 | |
146 | __xdata __at 0xE687 volatile BYTE FNADDR; ///< USB Function address | |
147 | ||
148 | // Endpoints | |
149 | ||
150 | __xdata __at 0xE68A volatile BYTE EP0BCH; ///< Endpoint 0 Byte Count H | |
151 | __xdata __at 0xE68B volatile BYTE EP0BCL; ///< Endpoint 0 Byte Count L | |
152 | __xdata __at 0xE68D volatile BYTE EP1OUTBC; ///< Endpoint 1 OUT Byte Count | |
153 | __xdata __at 0xE68F volatile BYTE EP1INBC; ///< Endpoint 1 IN Byte Count | |
154 | __xdata __at 0xE690 volatile BYTE EP2BCH; ///< Endpoint 2 Byte Count H | |
155 | __xdata __at 0xE691 volatile BYTE EP2BCL; ///< Endpoint 2 Byte Count L | |
156 | __xdata __at 0xE694 volatile BYTE EP4BCH; ///< Endpoint 4 Byte Count H | |
157 | __xdata __at 0xE695 volatile BYTE EP4BCL; ///< Endpoint 4 Byte Count L | |
158 | __xdata __at 0xE698 volatile BYTE EP6BCH; ///< Endpoint 6 Byte Count H | |
159 | __xdata __at 0xE699 volatile BYTE EP6BCL; ///< Endpoint 6 Byte Count L | |
160 | __xdata __at 0xE69C volatile BYTE EP8BCH; ///< Endpoint 8 Byte Count H | |
161 | __xdata __at 0xE69D volatile BYTE EP8BCL; ///< Endpoint 8 Byte Count L | |
162 | __xdata __at 0xE6A0 volatile BYTE EP0CS; ///< Endpoint Control and Status | |
163 | __xdata __at 0xE6A1 volatile BYTE EP1OUTCS; ///< Endpoint 1 OUT Control and Status | |
164 | __xdata __at 0xE6A2 volatile BYTE EP1INCS; ///< Endpoint 1 IN Control and Status | |
165 | __xdata __at 0xE6A3 volatile BYTE EP2CS; ///< Endpoint 2 Control and Status | |
166 | __xdata __at 0xE6A4 volatile BYTE EP4CS; ///< Endpoint 4 Control and Status | |
167 | __xdata __at 0xE6A5 volatile BYTE EP6CS; ///< Endpoint 6 Control and Status | |
168 | __xdata __at 0xE6A6 volatile BYTE EP8CS; ///< Endpoint 8 Control and Status | |
169 | __xdata __at 0xE6A7 volatile BYTE EP2FIFOFLGS; ///< Endpoint 2 Flags | |
170 | __xdata __at 0xE6A8 volatile BYTE EP4FIFOFLGS; ///< Endpoint 4 Flags | |
171 | __xdata __at 0xE6A9 volatile BYTE EP6FIFOFLGS; ///< Endpoint 6 Flags | |
172 | __xdata __at 0xE6AA volatile BYTE EP8FIFOFLGS; ///< Endpoint 8 Flags | |
173 | __xdata __at 0xE6AB volatile BYTE EP2FIFOBCH; ///< EP2 FIFO total byte count H | |
174 | __xdata __at 0xE6AC volatile BYTE EP2FIFOBCL; ///< EP2 FIFO total byte count L | |
175 | __xdata __at 0xE6AD volatile BYTE EP4FIFOBCH; ///< EP4 FIFO total byte count H | |
176 | __xdata __at 0xE6AE volatile BYTE EP4FIFOBCL; ///< EP4 FIFO total byte count L | |
177 | __xdata __at 0xE6AF volatile BYTE EP6FIFOBCH; ///< EP6 FIFO total byte count H | |
178 | __xdata __at 0xE6B0 volatile BYTE EP6FIFOBCL; ///< EP6 FIFO total byte count L | |
179 | __xdata __at 0xE6B1 volatile BYTE EP8FIFOBCH; ///< EP8 FIFO total byte count H | |
180 | __xdata __at 0xE6B2 volatile BYTE EP8FIFOBCL; ///< EP8 FIFO total byte count L | |
181 | __xdata __at 0xE6B3 volatile BYTE SUDPTRH; ///< Setup Data Pointer high address byte | |
182 | __xdata __at 0xE6B4 volatile BYTE SUDPTRL; ///< Setup Data Pointer low address byte | |
183 | __xdata __at 0xE6B5 volatile BYTE SUDPTRCTL; ///< Setup Data Pointer Auto Mode | |
184 | __xdata __at 0xE6B8 volatile BYTE SETUPDAT[8]; ///< 8 bytes of SETUP data | |
185 | ||
186 | // GPIF | |
187 | ||
188 | __xdata __at 0xE6C0 volatile BYTE GPIFWFSELECT; ///< Waveform Selector | |
189 | __xdata __at 0xE6C1 volatile BYTE GPIFIDLECS; ///< GPIF Done, GPIF IDLE drive mode | |
190 | __xdata __at 0xE6C2 volatile BYTE GPIFIDLECTL; ///< Inactive Bus, CTL states | |
191 | __xdata __at 0xE6C3 volatile BYTE GPIFCTLCFG; ///< CTL OUT pin drive | |
192 | __xdata __at 0xE6C4 volatile BYTE GPIFADRH; ///< GPIF Address H | |
193 | __xdata __at 0xE6C5 volatile BYTE GPIFADRL; ///< GPIF Address L | |
194 | ||
195 | __xdata __at 0xE6CE volatile BYTE GPIFTCB3; ///< GPIF Transaction Count Byte 3 | |
196 | __xdata __at 0xE6CF volatile BYTE GPIFTCB2; ///< GPIF Transaction Count Byte 2 | |
197 | __xdata __at 0xE6D0 volatile BYTE GPIFTCB1; ///< GPIF Transaction Count Byte 1 | |
198 | __xdata __at 0xE6D1 volatile BYTE GPIFTCB0; ///< GPIF Transaction Count Byte 0 | |
199 | ||
200 | __xdata __at 0xE6D2 volatile BYTE EP2GPIFFLGSEL; ///< EP2 GPIF Flag select | |
201 | __xdata __at 0xE6D3 volatile BYTE EP2GPIFPFSTOP; ///< Stop GPIF EP2 transaction on prog. flag | |
202 | __xdata __at 0xE6D4 volatile BYTE EP2GPIFTRIG; ///< EP2 FIFO Trigger | |
203 | __xdata __at 0xE6DA volatile BYTE EP4GPIFFLGSEL; ///< EP4 GPIF Flag select | |
204 | __xdata __at 0xE6DB volatile BYTE EP4GPIFPFSTOP; ///< Stop GPIF EP4 transaction on prog. flag | |
205 | __xdata __at 0xE6DC volatile BYTE EP4GPIFTRIG; ///< EP4 FIFO Trigger | |
206 | __xdata __at 0xE6E2 volatile BYTE EP6GPIFFLGSEL; ///< EP6 GPIF Flag select | |
207 | __xdata __at 0xE6E3 volatile BYTE EP6GPIFPFSTOP; ///< Stop GPIF EP6 transaction on prog. flag | |
208 | __xdata __at 0xE6E4 volatile BYTE EP6GPIFTRIG; ///< EP6 FIFO Trigger | |
209 | __xdata __at 0xE6EA volatile BYTE EP8GPIFFLGSEL; ///< EP8 GPIF Flag select | |
210 | __xdata __at 0xE6EB volatile BYTE EP8GPIFPFSTOP; ///< Stop GPIF EP8 transaction on prog. flag | |
211 | __xdata __at 0xE6EC volatile BYTE EP8GPIFTRIG; ///< EP8 FIFO Trigger | |
212 | __xdata __at 0xE6F0 volatile BYTE XGPIFSGLDATH; ///< GPIF Data H (16-bit mode only) | |
213 | __xdata __at 0xE6F1 volatile BYTE XGPIFSGLDATLX; ///< Read/Write GPIF Data L & trigger transac | |
214 | __xdata __at 0xE6F2 volatile BYTE XGPIFSGLDATLNOX; ///< Read GPIF Data L, no transac trigger | |
215 | __xdata __at 0xE6F3 volatile BYTE GPIFREADYCFG; ///< Internal RDY,Sync/Async, RDY5CFG | |
216 | __xdata __at 0xE6F4 volatile BYTE GPIFREADYSTAT; ///< RDY pin states | |
217 | __xdata __at 0xE6F5 volatile BYTE GPIFABORT; ///< Abort GPIF cycles | |
218 | ||
219 | // UDMA | |
220 | ||
221 | __xdata __at 0xE6C6 volatile BYTE FLOWSTATE; ///<Defines GPIF flow state | |
222 | __xdata __at 0xE6C7 volatile BYTE FLOWLOGIC; ///<Defines flow/hold decision criteria | |
223 | __xdata __at 0xE6C8 volatile BYTE FLOWEQ0CTL; ///<CTL states during active flow state | |
224 | __xdata __at 0xE6C9 volatile BYTE FLOWEQ1CTL; ///<CTL states during hold flow state | |
225 | __xdata __at 0xE6CA volatile BYTE FLOWHOLDOFF; | |
226 | __xdata __at 0xE6CB volatile BYTE FLOWSTB; ///<CTL/RDY Signal to use as master data strobe | |
227 | __xdata __at 0xE6CC volatile BYTE FLOWSTBEDGE; ///<Defines active master strobe edge | |
228 | __xdata __at 0xE6CD volatile BYTE FLOWSTBHPERIOD; ///<Half Period of output master strobe | |
229 | __xdata __at 0xE60C volatile BYTE GPIFHOLDAMOUNT; ///<Data delay shift | |
230 | __xdata __at 0xE67D volatile BYTE UDMACRCH; ///<CRC Upper byte | |
231 | __xdata __at 0xE67E volatile BYTE UDMACRCL; ///<CRC Lower byte | |
232 | __xdata __at 0xE67F volatile BYTE UDMACRCQUAL; ///<UDMA In only, host terminated use only | |
233 | ||
234 | // Endpoint Buffers | |
235 | ||
236 | __xdata __at 0xE740 volatile BYTE EP0BUF[64]; ///< EP0 IN-OUT buffer | |
237 | __xdata __at 0xE780 volatile BYTE EP1OUTBUF[64]; ///< EP1-OUT buffer | |
238 | __xdata __at 0xE7C0 volatile BYTE EP1INBUF[64]; ///< EP1-IN buffer | |
239 | __xdata __at 0xF000 volatile BYTE EP2FIFOBUF[1024]; ///< 512/1024-byte EP2 buffer (IN or OUT) | |
240 | __xdata __at 0xF400 volatile BYTE EP4FIFOBUF[1024]; ///< 512 byte EP4 buffer (IN or OUT) | |
241 | __xdata __at 0xF800 volatile BYTE EP6FIFOBUF[1024]; ///< 512/1024-byte EP6 buffer (IN or OUT) | |
242 | __xdata __at 0xFC00 volatile BYTE EP8FIFOBUF[1024]; ///< 512 byte EP8 buffer (IN or OUT) | |
243 | ||
244 | // Error Correction Code (ECC) Registers (FX2LP/FX1 only) | |
245 | ||
246 | __xdata __at 0xE628 volatile BYTE ECCCFG; ///< ECC Configuration | |
247 | __xdata __at 0xE629 volatile BYTE ECCRESET; ///< ECC Reset | |
248 | __xdata __at 0xE62A volatile BYTE ECC1B0; ///< ECC1 Byte 0 | |
249 | __xdata __at 0xE62B volatile BYTE ECC1B1; ///< ECC1 Byte 1 | |
250 | __xdata __at 0xE62C volatile BYTE ECC1B2; ///< ECC1 Byte 2 | |
251 | __xdata __at 0xE62D volatile BYTE ECC2B0; ///< ECC2 Byte 0 | |
252 | __xdata __at 0xE62E volatile BYTE ECC2B1; ///< ECC2 Byte 1 | |
253 | __xdata __at 0xE62F volatile BYTE ECC2B2; ///< ECC2 Byte 2 | |
254 | ||
255 | // Feature Registers (FX2LP/FX1 only) | |
256 | __xdata __at 0xE50D volatile BYTE GPCR2; ///< Chip Features | |
257 | ||
258 | /** | |
259 | * SFRs below | |
260 | * According to TRM 15.2, only rows 0 and 8 of the SFRs are bit addressible | |
261 | * row 0: IOA, IOB, IOC, IOD, SCON1, PSW, ACC, B | |
262 | * row 8: TCON, SCON0, IE, IP, T2CON, IECON, EIE, EIP | |
263 | * | |
264 | * All others have to move a byte to the SRF address | |
265 | **/ | |
266 | ||
267 | __sfr __at 0x80 IOA; | |
268 | /* IOA */ | |
269 | __sbit __at 0x80 + 0 PA0; | |
270 | __sbit __at 0x80 + 1 PA1; | |
271 | __sbit __at 0x80 + 2 PA2; | |
272 | __sbit __at 0x80 + 3 PA3; | |
273 | __sbit __at 0x80 + 4 PA4; | |
274 | __sbit __at 0x80 + 5 PA5; | |
275 | __sbit __at 0x80 + 6 PA6; | |
276 | __sbit __at 0x80 + 7 PA7; | |
277 | __sfr __at 0x81 SP; | |
278 | __sfr __at 0x82 DPL; | |
279 | __sfr __at 0x83 DPH; | |
280 | __sfr __at 0x84 DPL1; | |
281 | __sfr __at 0x85 DPH1; | |
282 | __sfr __at 0x86 DPS; | |
283 | __sfr __at 0x87 PCON; | |
284 | __sfr __at 0x88 TCON; | |
285 | /* TCON */ | |
286 | __sbit __at 0x88+0 IT0; | |
287 | __sbit __at 0x88+1 IE0; | |
288 | __sbit __at 0x88+2 IT1; | |
289 | __sbit __at 0x88+3 IE1; | |
290 | __sbit __at 0x88+4 TR0; | |
291 | __sbit __at 0x88+5 TF0; | |
292 | __sbit __at 0x88+6 TR1; | |
293 | __sbit __at 0x88+7 TF1; | |
294 | __sfr __at 0x89 TMOD; | |
295 | __sfr __at 0x8A TL0; | |
296 | __sfr __at 0x8B TL1; | |
297 | __sfr __at 0x8C TH0; | |
298 | __sfr __at 0x8D TH1; | |
299 | __sfr __at 0x8E CKCON; | |
300 | __sfr __at 0x90 IOB; | |
301 | /* IOB */ | |
302 | __sbit __at 0x90 + 0 PB0; | |
303 | __sbit __at 0x90 + 1 PB1; | |
304 | __sbit __at 0x90 + 2 PB2; | |
305 | __sbit __at 0x90 + 3 PB3; | |
306 | __sbit __at 0x90 + 4 PB4; | |
307 | __sbit __at 0x90 + 5 PB5; | |
308 | __sbit __at 0x90 + 6 PB6; | |
309 | __sbit __at 0x90 + 7 PB7; | |
310 | __sfr __at 0x91 EXIF; | |
311 | ||
312 | //__sfr __at 0x92 MPAGE; | |
313 | __sfr __at 0x92 _XPAGE; // same as MPAGE for pdata __sfr access w/ sdcc | |
314 | __sfr __at 0x98 SCON0; | |
315 | /* SCON0 */ | |
316 | __sbit __at 0x98+0 RI; | |
317 | __sbit __at 0x98+1 TI; | |
318 | __sbit __at 0x98+2 RB8; | |
319 | __sbit __at 0x98+3 TB8; | |
320 | __sbit __at 0x98+4 REN; | |
321 | __sbit __at 0x98+5 SM2; | |
322 | __sbit __at 0x98+6 SM1; | |
323 | __sbit __at 0x98+7 SM0; | |
324 | __sfr __at 0x99 SBUF0; | |
325 | ||
326 | __sfr __at 0x9A AUTOPTRH1; | |
327 | __sfr __at 0x9B AUTOPTRL1; | |
328 | __sfr __at 0x9D AUTOPTRH2; | |
329 | __sfr __at 0x9E AUTOPTRL2; | |
330 | ||
331 | __sfr __at 0xA0 IOC; | |
332 | /* IOC */ | |
333 | __sbit __at 0xA0 + 0 PC0; | |
334 | __sbit __at 0xA0 + 1 PC1; | |
335 | __sbit __at 0xA0 + 2 PC2; | |
336 | __sbit __at 0xA0 + 3 PC3; | |
337 | __sbit __at 0xA0 + 4 PC4; | |
338 | __sbit __at 0xA0 + 5 PC5; | |
339 | __sbit __at 0xA0 + 6 PC6; | |
340 | __sbit __at 0xA0 + 7 PC7; | |
341 | __sfr __at 0xA1 INT2CLR; | |
342 | __sfr __at 0xA2 INT4CLR; | |
343 | ||
344 | __sfr __at 0xA8 IE; | |
345 | /* IE */ | |
346 | __sbit __at 0xA8+0 EX0; | |
347 | __sbit __at 0xA8+1 ET0; | |
348 | __sbit __at 0xA8+2 EX1; | |
349 | __sbit __at 0xA8+3 ET1; | |
350 | __sbit __at 0xA8+4 ES0; | |
351 | __sbit __at 0xA8+5 ET2; | |
352 | __sbit __at 0xA8+6 ES1; | |
353 | __sbit __at 0xA8+7 EA; | |
354 | ||
355 | __sfr __at 0xAA EP2468STAT; | |
356 | __sfr __at 0xAB EP24FIFOFLGS; | |
357 | __sfr __at 0xAC EP68FIFOFLGS; | |
358 | __sfr __at 0xAF AUTOPTRSETUP; | |
359 | __sfr __at 0xB0 IOD; | |
360 | /* IOD */ | |
361 | __sbit __at 0xB0 + 0 PD0; | |
362 | __sbit __at 0xB0 + 1 PD1; | |
363 | __sbit __at 0xB0 + 2 PD2; | |
364 | __sbit __at 0xB0 + 3 PD3; | |
365 | __sbit __at 0xB0 + 4 PD4; | |
366 | __sbit __at 0xB0 + 5 PD5; | |
367 | __sbit __at 0xB0 + 6 PD6; | |
368 | __sbit __at 0xB0 + 7 PD7; | |
369 | __sfr __at 0xB1 IOE; | |
370 | __sfr __at 0xB2 OEA; | |
371 | __sfr __at 0xB3 OEB; | |
372 | __sfr __at 0xB4 OEC; | |
373 | __sfr __at 0xB5 OED; | |
374 | __sfr __at 0xB6 OEE; | |
375 | ||
376 | __sfr __at 0xB8 IP; | |
377 | /* IP */ | |
378 | __sbit __at 0xB8+0 PX0; | |
379 | __sbit __at 0xB8+1 PT0; | |
380 | __sbit __at 0xB8+2 PX1; | |
381 | __sbit __at 0xB8+3 PT1; | |
382 | __sbit __at 0xB8+4 PS0; | |
383 | __sbit __at 0xB8+5 PT2; | |
384 | __sbit __at 0xB8+6 PS1; | |
385 | ||
386 | __sfr __at 0xBA EP01STAT; | |
387 | __sfr __at 0xBB GPIFTRIG; | |
388 | ||
389 | __sfr __at 0xBD GPIFSGLDATH; | |
390 | __sfr __at 0xBE GPIFSGLDATLX; | |
391 | __sfr __at 0xBF GPIFSGLDATLNOX; | |
392 | ||
393 | __sfr __at 0xC0 SCON1; | |
394 | /* SCON1 */ | |
395 | __sbit __at 0xC0+0 RI1; | |
396 | __sbit __at 0xC0+1 TI1; | |
397 | __sbit __at 0xC0+2 RB81; | |
398 | __sbit __at 0xC0+3 TB81; | |
399 | __sbit __at 0xC0+4 REN1; | |
400 | __sbit __at 0xC0+5 SM21; | |
401 | __sbit __at 0xC0+6 SM11; | |
402 | __sbit __at 0xC0+7 SM01; | |
403 | __sfr __at 0xC1 SBUF1; | |
404 | __sfr __at 0xC8 T2CON; | |
405 | /* T2CON */ | |
406 | __sbit __at 0xC8+0 CP_RL2; | |
407 | __sbit __at 0xC8+1 C_T2; | |
408 | __sbit __at 0xC8+2 TR2; | |
409 | __sbit __at 0xC8+3 EXEN2; | |
410 | __sbit __at 0xC8+4 TCLK; | |
411 | __sbit __at 0xC8+5 RCLK; | |
412 | __sbit __at 0xC8+6 EXF2; | |
413 | __sbit __at 0xC8+7 TF2; | |
414 | __sfr __at 0xCA RCAP2L; | |
415 | __sfr __at 0xCB RCAP2H; | |
416 | __sfr __at 0xCC TL2; | |
417 | __sfr __at 0xCD TH2; | |
418 | __sfr __at 0xD0 PSW; | |
419 | /* PSW */ | |
420 | __sbit __at 0xD0+0 P; | |
421 | __sbit __at 0xD0+1 FL; | |
422 | __sbit __at 0xD0+2 OV; | |
423 | __sbit __at 0xD0+3 RS0; | |
424 | __sbit __at 0xD0+4 RS1; | |
425 | __sbit __at 0xD0+5 F0; | |
426 | __sbit __at 0xD0+6 AC; | |
427 | __sbit __at 0xD0+7 CY; | |
428 | __sfr __at 0xD8 EICON; // Was WDCON in DS80C320; Bit Values differ from Reg320 | |
429 | /* EICON */ | |
430 | __sbit __at 0xD8+3 INT6; | |
431 | __sbit __at 0xD8+4 RESI; | |
432 | __sbit __at 0xD8+5 ERESI; | |
433 | __sbit __at 0xD8+7 SMOD1; | |
434 | __sfr __at 0xE0 ACC; | |
435 | __sfr __at 0xE8 EIE; // EIE Bit Values differ from Reg320 | |
436 | /* EIE */ | |
437 | __sbit __at 0xE8+0 EUSB; | |
438 | __sbit __at 0xE8+1 EI2C; | |
439 | __sbit __at 0xE8+2 EIEX4; | |
440 | __sbit __at 0xE8+3 EIEX5; | |
441 | __sbit __at 0xE8+4 EIEX6; | |
442 | __sfr __at 0xF0 B; | |
443 | __sfr __at 0xF8 EIP; // EIP Bit Values differ from Reg320 | |
444 | /* EIP */ | |
445 | __sbit __at 0xF8+0 PUSB; | |
446 | __sbit __at 0xF8+1 PI2C; | |
447 | __sbit __at 0xF8+2 EIPX4; | |
448 | __sbit __at 0xF8+3 EIPX5; | |
449 | __sbit __at 0xF8+4 EIPX6; | |
450 | ||
451 | ||
452 | /* CPU Control & Status Register (CPUCS) */ | |
453 | #define bmPRTCSTB bmBIT5 | |
454 | #define bmCLKSPD (bmBIT4 | bmBIT3) | |
455 | #define bmCLKSPD1 bmBIT4 | |
456 | #define bmCLKSPD0 bmBIT3 | |
457 | #define bmCLKINV bmBIT2 | |
458 | #define bmCLKOE bmBIT1 | |
459 | #define bm8051RES bmBIT0 | |
460 | /* Port Alternate Configuration Registers */ | |
461 | /* Port A (PORTACFG) */ | |
462 | #define bmFLAGD bmBIT7 | |
463 | #define bmINT1 bmBIT1 | |
464 | #define bmINT0 bmBIT0 | |
465 | /* Port C (PORTCCFG) */ | |
466 | #define bmGPIFA7 bmBIT7 | |
467 | #define bmGPIFA6 bmBIT6 | |
468 | #define bmGPIFA5 bmBIT5 | |
469 | #define bmGPIFA4 bmBIT4 | |
470 | #define bmGPIFA3 bmBIT3 | |
471 | #define bmGPIFA2 bmBIT2 | |
472 | #define bmGPIFA1 bmBIT1 | |
473 | #define bmGPIFA0 bmBIT0 | |
474 | /* Port E (PORTECFG) */ | |
475 | #define bmGPIFA8 bmBIT7 | |
476 | #define bmT2EX bmBIT6 | |
477 | #define bmINT6 bmBIT5 | |
478 | #define bmRXD1OUT bmBIT4 | |
479 | #define bmRXD0OUT bmBIT3 | |
480 | #define bmT2OUT bmBIT2 | |
481 | #define bmT1OUT bmBIT1 | |
482 | #define bmT0OUT bmBIT0 | |
483 | ||
484 | /* I2C Control & Status Register (I2CS) */ | |
485 | #define bmSTART bmBIT7 | |
486 | #define bmSTOP bmBIT6 | |
487 | #define bmLASTRD bmBIT5 | |
488 | #define bmID (bmBIT4 | bmBIT3) | |
489 | #define bmBERR bmBIT2 | |
490 | #define bmACK bmBIT1 | |
491 | #define bmDONE bmBIT0 | |
492 | /* I2C Control Register (I2CTL) */ | |
493 | #define bmSTOPIE bmBIT1 | |
494 | #define bm400KHZ bmBIT0 | |
495 | /* Interrupt 2 (USB) Autovector Register (INT2IVEC) */ | |
496 | #define bmIV4 bmBIT6 | |
497 | #define bmIV3 bmBIT5 | |
498 | #define bmIV2 bmBIT4 | |
499 | #define bmIV1 bmBIT3 | |
500 | #define bmIV0 bmBIT2 | |
501 | /* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */ | |
502 | #define bmEP0ACK bmBIT6 | |
503 | #define bmHSGRANT bmBIT5 | |
504 | #define bmURES bmBIT4 | |
505 | #define bmSUSP bmBIT3 | |
506 | #define bmSUTOK bmBIT2 | |
507 | #define bmSOF bmBIT1 | |
508 | #define bmSUDAV bmBIT0 | |
509 | /* USBERRIE/IRQ */ | |
510 | #define bmERRLIMIT bmBIT0 | |
511 | #define bmISOEP2 bmBIT4 | |
512 | #define bmISOEP4 bmBIT5 | |
513 | #define bmISOEP6 bmBIT6 | |
514 | #define bmISOEP8 bmBIT7 | |
515 | ||
516 | /* Endpoint Interrupt & Enable Registers (EPIE/EPIRQ) */ | |
517 | #define bmEP0IN bmBIT0 | |
518 | #define bmEP0OUT bmBIT1 | |
519 | #define bmEP1IN bmBIT2 | |
520 | #define bmEP1OUT bmBIT3 | |
521 | #define bmEP2 bmBIT4 | |
522 | #define bmEP4 bmBIT5 | |
523 | #define bmEP6 bmBIT6 | |
524 | #define bmEP8 bmBIT7 | |
525 | /* Breakpoint register (BREAKPT) */ | |
526 | #define bmBREAK bmBIT3 | |
527 | #define bmBPPULSE bmBIT2 | |
528 | #define bmBPEN bmBIT1 | |
529 | /* Interrupt 2 & 4 Setup (INTSETUP) */ | |
530 | #define bmAV2EN bmBIT3 | |
531 | #define INT4IN bmBIT1 | |
532 | #define bmAV4EN bmBIT0 | |
533 | /* USB Control & Status Register (USBCS) */ | |
534 | #define bmHSM bmBIT7 | |
535 | #define bmDISCON bmBIT3 | |
536 | #define bmNOSYNSOF bmBIT2 | |
537 | #define bmRENUM bmBIT1 | |
538 | #define bmSIGRESUME bmBIT0 | |
539 | /* Wakeup Control and Status Register (WAKEUPCS) */ | |
540 | #define bmWU2 bmBIT7 | |
541 | #define bmWU bmBIT6 | |
542 | #define bmWU2POL bmBIT5 | |
543 | #define bmWUPOL bmBIT4 | |
544 | #define bmDPEN bmBIT2 | |
545 | #define bmWU2EN bmBIT1 | |
546 | #define bmWUEN bmBIT0 | |
547 | /* End Point 0 Control & Status Register (EP0CS) */ | |
548 | #define bmHSNAK bmBIT7 | |
549 | /* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */ | |
550 | #define bmEPBUSY bmBIT1 | |
551 | #define bmEPSTALL bmBIT0 | |
552 | /* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */ | |
553 | #define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4) | |
554 | #define bmEPFULL bmBIT3 | |
555 | #define bmEPEMPTY bmBIT2 | |
556 | /* Endpoint Status (EP2468STAT) __SFR bits */ | |
557 | #define bmEP8FULL bmBIT7 | |
558 | #define bmEP8EMPTY bmBIT6 | |
559 | #define bmEP6FULL bmBIT5 | |
560 | #define bmEP6EMPTY bmBIT4 | |
561 | #define bmEP4FULL bmBIT3 | |
562 | #define bmEP4EMPTY bmBIT2 | |
563 | #define bmEP2FULL bmBIT1 | |
564 | #define bmEP2EMPTY bmBIT0 | |
565 | /* Endpoint Config (EP[24]CFG) */ | |
566 | #define bmBUF (bmBIT0|bmBIT1) | |
567 | /* Endpoint Config (EP[2468]CFG) */ | |
568 | #define bmSIZE bmBIT3 | |
569 | #define bmTYPE (bmBIT4|bmBIT5) | |
570 | #define bmDIR bmBIT6 | |
571 | #define bmVALID bmBIT7 | |
572 | /* SETUP Data Pointer Auto Mode (SUDPTRCTL) */ | |
573 | #define bmSDPAUTO bmBIT0 | |
574 | /* Endpoint Data Toggle Control (TOGCTL) */ | |
575 | #define bmQUERYTOGGLE bmBIT7 | |
576 | #define bmSETTOGGLE bmBIT6 | |
577 | #define bmRESETTOGGLE bmBIT5 | |
578 | #define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0 | |
579 | /* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */ | |
580 | #define bmEP8IBN bmBIT5 | |
581 | #define bmEP6IBN bmBIT4 | |
582 | #define bmEP4IBN bmBIT3 | |
583 | #define bmEP2IBN bmBIT2 | |
584 | #define bmEP1IBN bmBIT1 | |
585 | #define bmEP0IBN bmBIT0 | |
586 | ||
587 | /* PING-NAK enable and request bits (NAKIE/NAKIRQ) */ | |
588 | #define bmEP8PING bmBIT7 | |
589 | #define bmEP6PING bmBIT6 | |
590 | #define bmEP4PING bmBIT5 | |
591 | #define bmEP2PING bmBIT4 | |
592 | #define bmEP1PING bmBIT3 | |
593 | #define bmEP0PING bmBIT2 | |
594 | #define bmIBN bmBIT0 | |
595 | ||
596 | /* Interface Configuration bits (IFCONFIG) */ | |
597 | #define bmIFCLKSRC bmBIT7 | |
598 | #define bm3048MHZ bmBIT6 | |
599 | #define bmIFCLKOE bmBIT5 | |
600 | #define bmIFCLKPOL bmBIT4 | |
601 | #define bmASYNC bmBIT3 | |
602 | #define bmGSTATE bmBIT2 | |
603 | #define bmIFCFG1 bmBIT1 | |
604 | #define bmIFCFG0 bmBIT0 | |
605 | #define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1) | |
606 | #define bmIFGPIF bmIFCFG1 | |
607 | ||
608 | /* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */ | |
609 | #define bmINFM bmBIT6 | |
610 | #define bmOEP bmBIT5 | |
611 | #define bmAUTOOUT bmBIT4 | |
612 | #define bmAUTOIN bmBIT3 | |
613 | #define bmZEROLENIN bmBIT2 | |
614 | #define bmWORDWIDE bmBIT0 | |
615 | ||
616 | /* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specidic | |
617 | features */ | |
618 | #define bmNOAUTOARM bmBIT1 | |
619 | #define bmSKIPCOMMIT bmBIT0 | |
620 | ||
621 | /* Fifo Reset bits (FIFORESET) */ | |
622 | #define bmNAKALL bmBIT7 | |
623 | ||
624 | /* Chip Feature Register (GPCR2) */ | |
625 | #define bmFULLSPEEDONLY bmBIT4 | |
626 | ||
627 | #endif /* FX2REGS_H */ |