]>
Commit | Line | Data |
---|---|---|
a1bb33af | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
fed16f06 UH |
3 | * |
4 | * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com> | |
5 | * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com> | |
6 | * All rights reserved. | |
7 | * | |
8 | * Redistribution and use in source and binary forms, with or | |
9 | * without modification, are permitted provided that the following | |
10 | * conditions are met: | |
11 | * | |
12 | * * Redistributions of source code must retain the above copyright notice, | |
13 | * this list of conditions and the following disclaimer. | |
14 | * | |
15 | * * Redistributions in binary form must reproduce the above copyright notice, | |
16 | * this list of conditions and the following disclaimer in the documentation | |
17 | * and/or other materials provided with the distribution. | |
18 | * | |
19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE | |
23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
29 | * THE POSSIBILITY OF SUCH DAMAGE. | |
30 | */ | |
a1bb33af | 31 | |
fed16f06 | 32 | #include <assert.h> |
6d116114 UH |
33 | #include "libsigrok.h" |
34 | #include "libsigrok-internal.h" | |
a1bb33af UH |
35 | #include "analyzer.h" |
36 | #include "gl_usb.h" | |
6d116114 | 37 | #include "protocol.h" |
a1bb33af UH |
38 | |
39 | enum { | |
fed16f06 | 40 | HARD_DATA_CHECK_SUM = 0x00, |
a1bb33af UH |
41 | PASS_WORD, |
42 | ||
bb7ef793 UH |
43 | DEV_ID0 = 0x10, |
44 | DEV_ID1, | |
a1bb33af | 45 | |
fed16f06 | 46 | START_STATUS = 0x20, |
bb7ef793 | 47 | DEV_STATUS = 0x21, |
fed16f06 | 48 | FREQUENCY_REG0 = 0x30, |
a1bb33af UH |
49 | FREQUENCY_REG1, |
50 | FREQUENCY_REG2, | |
51 | FREQUENCY_REG3, | |
52 | FREQUENCY_REG4, | |
53 | MEMORY_LENGTH, | |
54 | CLOCK_SOURCE, | |
55 | ||
fed16f06 | 56 | TRIGGER_STATUS0 = 0x40, |
a1bb33af UH |
57 | TRIGGER_STATUS1, |
58 | TRIGGER_STATUS2, | |
59 | TRIGGER_STATUS3, | |
60 | TRIGGER_STATUS4, | |
61 | TRIGGER_STATUS5, | |
62 | TRIGGER_STATUS6, | |
63 | TRIGGER_STATUS7, | |
64 | TRIGGER_STATUS8, | |
65 | ||
fed16f06 | 66 | TRIGGER_COUNT0 = 0x50, |
a1bb33af UH |
67 | TRIGGER_COUNT1, |
68 | ||
fed16f06 | 69 | TRIGGER_LEVEL0 = 0x55, |
a1bb33af UH |
70 | TRIGGER_LEVEL1, |
71 | TRIGGER_LEVEL2, | |
72 | TRIGGER_LEVEL3, | |
73 | ||
74 | RAMSIZE_TRIGGERBAR_ADDRESS0 = 0x60, | |
75 | RAMSIZE_TRIGGERBAR_ADDRESS1, | |
76 | RAMSIZE_TRIGGERBAR_ADDRESS2, | |
77 | TRIGGERBAR_ADDRESS0, | |
78 | TRIGGERBAR_ADDRESS1, | |
79 | TRIGGERBAR_ADDRESS2, | |
80 | DONT_CARE_TRIGGERBAR, | |
81 | ||
82 | FILTER_ENABLE = 0x70, | |
83 | FILTER_STATUS, | |
84 | ||
fed16f06 | 85 | ENABLE_DELAY_TIME0 = 0x7a, |
a1bb33af UH |
86 | ENABLE_DELAY_TIME1, |
87 | ||
fed16f06 | 88 | ENABLE_INSERT_DATA0 = 0x80, |
a1bb33af UH |
89 | ENABLE_INSERT_DATA1, |
90 | ENABLE_INSERT_DATA2, | |
91 | ENABLE_INSERT_DATA3, | |
92 | COMPRESSION_TYPE0, | |
93 | COMPRESSION_TYPE1, | |
94 | ||
fed16f06 | 95 | TRIGGER_ADDRESS0 = 0x90, |
a1bb33af UH |
96 | TRIGGER_ADDRESS1, |
97 | TRIGGER_ADDRESS2, | |
98 | ||
fed16f06 | 99 | NOW_ADDRESS0 = 0x96, |
a1bb33af UH |
100 | NOW_ADDRESS1, |
101 | NOW_ADDRESS2, | |
102 | ||
fed16f06 | 103 | STOP_ADDRESS0 = 0x9b, |
a1bb33af UH |
104 | STOP_ADDRESS1, |
105 | STOP_ADDRESS2, | |
106 | ||
fed16f06 | 107 | READ_RAM_STATUS = 0xa0, |
a1bb33af UH |
108 | }; |
109 | ||
fed16f06 | 110 | static int g_trigger_status[9] = { 0 }; |
a1bb33af | 111 | static int g_trigger_count = 1; |
fed16f06 | 112 | static int g_filter_status[8] = { 0 }; |
a1bb33af UH |
113 | static int g_filter_enable = 0; |
114 | ||
0ab0cb94 | 115 | static int g_freq_value = 1; |
a1bb33af | 116 | static int g_freq_scale = FREQ_SCALE_MHZ; |
0ab0cb94 TY |
117 | static int g_memory_size = MEMORY_SIZE_8K; |
118 | static int g_ramsize_triggerbar_addr = 2 * 1024; | |
119 | static int g_triggerbar_addr = 0; | |
a1bb33af | 120 | static int g_compression = COMPRESSION_NONE; |
7142d6b9 | 121 | static int g_thresh = 0x31; /* 1.5V */ |
a1bb33af | 122 | |
fed16f06 UH |
123 | /* Maybe unk specifies an "endpoint" or "register" of sorts. */ |
124 | static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk, | |
125 | unsigned char flags) | |
a1bb33af UH |
126 | { |
127 | assert(unk <= 3); | |
128 | return gl_reg_write(devh, START_STATUS, unk << 6 | flags); | |
129 | } | |
130 | ||
0ab0cb94 | 131 | #if 0 |
a1bb33af UH |
132 | static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale) |
133 | { | |
fed16f06 UH |
134 | int reg0 = 0, divisor = 0, reg2 = 0; |
135 | ||
a1bb33af | 136 | switch (scale) { |
fed16f06 UH |
137 | case FREQ_SCALE_MHZ: /* MHz */ |
138 | if (freq >= 100 && freq <= 200) { | |
139 | reg0 = freq * 0.1; | |
140 | divisor = 1; | |
141 | reg2 = 0; | |
142 | break; | |
143 | } | |
144 | if (freq >= 50 && freq < 100) { | |
145 | reg0 = freq * 0.2; | |
146 | divisor = 2; | |
147 | reg2 = 0; | |
148 | break; | |
149 | } | |
150 | if (freq >= 10 && freq < 50) { | |
151 | if (freq == 25) { | |
152 | reg0 = 25; | |
a1bb33af | 153 | divisor = 5; |
fed16f06 | 154 | reg2 = 1; |
a1bb33af | 155 | break; |
fed16f06 UH |
156 | } else { |
157 | reg0 = freq * 0.5; | |
a1bb33af | 158 | divisor = 5; |
fed16f06 | 159 | reg2 = 1; |
a1bb33af UH |
160 | break; |
161 | } | |
fed16f06 UH |
162 | } |
163 | if (freq >= 2 && freq < 10) { | |
a1bb33af | 164 | divisor = 5; |
fed16f06 UH |
165 | reg0 = freq * 2; |
166 | reg2 = 2; | |
a1bb33af | 167 | break; |
fed16f06 UH |
168 | } |
169 | if (freq == 1) { | |
a1bb33af | 170 | divisor = 5; |
fed16f06 | 171 | reg2 = 16; |
a1bb33af | 172 | reg0 = 5; |
fed16f06 UH |
173 | break; |
174 | } | |
175 | divisor = 5; | |
176 | reg0 = 5; | |
177 | reg2 = 64; | |
178 | break; | |
179 | case FREQ_SCALE_HZ: /* Hz */ | |
180 | if (freq >= 500 && freq < 1000) { | |
181 | reg0 = freq * 0.01; | |
182 | divisor = 10; | |
a1bb33af UH |
183 | reg2 = 64; |
184 | break; | |
fed16f06 UH |
185 | } |
186 | if (freq >= 300 && freq < 500) { | |
187 | reg0 = freq * 0.005 * 8; | |
188 | divisor = 5; | |
189 | reg2 = 67; | |
190 | break; | |
191 | } | |
192 | if (freq >= 100 && freq < 300) { | |
193 | reg0 = freq * 0.005 * 16; | |
194 | divisor = 5; | |
195 | reg2 = 68; | |
196 | break; | |
197 | } | |
198 | divisor = 5; | |
199 | reg0 = 5; | |
200 | reg2 = 64; | |
201 | break; | |
38ba2522 | 202 | case FREQ_SCALE_KHZ: /* kHz */ |
fed16f06 UH |
203 | if (freq >= 500 && freq < 1000) { |
204 | reg0 = freq * 0.01; | |
205 | divisor = 5; | |
206 | reg2 = 17; | |
207 | break; | |
208 | } | |
209 | if (freq >= 100 && freq < 500) { | |
210 | reg0 = freq * 0.05; | |
211 | divisor = 5; | |
212 | reg2 = 32; | |
213 | break; | |
214 | } | |
215 | if (freq >= 50 && freq < 100) { | |
216 | reg0 = freq * 0.1; | |
217 | divisor = 5; | |
218 | reg2 = 33; | |
219 | break; | |
220 | } | |
221 | if (freq >= 10 && freq < 50) { | |
222 | if (freq == 25) { | |
223 | reg0 = 25; | |
a1bb33af | 224 | divisor = 5; |
fed16f06 | 225 | reg2 = 49; |
a1bb33af UH |
226 | break; |
227 | } | |
fed16f06 | 228 | reg0 = freq * 0.5; |
a1bb33af | 229 | divisor = 5; |
fed16f06 | 230 | reg2 = 48; |
a1bb33af | 231 | break; |
fed16f06 UH |
232 | } |
233 | if (freq >= 2 && freq < 10) { | |
a1bb33af | 234 | divisor = 5; |
fed16f06 UH |
235 | reg0 = freq * 2; |
236 | reg2 = 50; | |
a1bb33af | 237 | break; |
fed16f06 UH |
238 | } |
239 | divisor = 5; | |
240 | reg0 = 5; | |
241 | reg2 = 64; | |
242 | break; | |
243 | default: | |
244 | divisor = 5; | |
245 | reg0 = 5; | |
246 | reg2 = 64; | |
247 | break; | |
a1bb33af | 248 | } |
c13536fa | 249 | |
6d116114 | 250 | sr_dbg("Setting samplerate regs (freq=%d, scale=%d): " |
c13536fa UH |
251 | "reg0: %d, reg1: %d, reg2: %d, reg3: %d.", |
252 | freq, scale, divisor, reg0, 0x02, reg2); | |
253 | ||
a1bb33af | 254 | if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0) |
fed16f06 | 255 | return -1; /* Divisor maybe? */ |
a1bb33af UH |
256 | |
257 | if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0) | |
fed16f06 | 258 | return -1; /* 10 / 0.2 */ |
a1bb33af UH |
259 | |
260 | if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0) | |
fed16f06 | 261 | return -1; /* Always 2 */ |
a1bb33af UH |
262 | |
263 | if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0) | |
264 | return -1; | |
265 | ||
266 | return 0; | |
267 | } | |
0ab0cb94 TY |
268 | #endif |
269 | ||
270 | /* | |
271 | * It seems that ... | |
272 | * FREQUENCT_REG0 - division factor (?) | |
273 | * FREQUENCT_REG1 - multiplication factor (?) | |
274 | * FREQUENCT_REG4 - clock selection (?) | |
275 | * | |
276 | * clock selection | |
277 | * 0 10MHz 16 1MHz 32 100kHz 48 10kHz 64 1kHz | |
278 | * 1 5MHz 17 500kHz 33 50kHz 49 5kHz 65 500Hz | |
279 | * 2 2.5MHz . . 50 2.5kHz 66 250Hz | |
280 | * . . . . 67 125Hz | |
281 | * . . . . 68 62.5Hz | |
282 | */ | |
283 | static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale) | |
284 | { | |
285 | struct freq_factor { | |
286 | int freq; | |
287 | int scale; | |
288 | int sel; | |
289 | int div; | |
290 | int mul; | |
291 | }; | |
292 | ||
293 | static const struct freq_factor f[] = { | |
294 | { 200, FREQ_SCALE_MHZ, 0, 1, 20 }, | |
295 | { 150, FREQ_SCALE_MHZ, 0, 1, 15 }, | |
296 | { 100, FREQ_SCALE_MHZ, 0, 1, 10 }, | |
297 | { 80, FREQ_SCALE_MHZ, 0, 2, 16 }, | |
298 | { 50, FREQ_SCALE_MHZ, 0, 2, 10 }, | |
299 | { 25, FREQ_SCALE_MHZ, 1, 5, 25 }, | |
300 | { 10, FREQ_SCALE_MHZ, 1, 5, 10 }, | |
301 | { 1, FREQ_SCALE_MHZ, 16, 5, 5 }, | |
302 | { 800, FREQ_SCALE_KHZ, 17, 5, 8 }, | |
303 | { 400, FREQ_SCALE_KHZ, 32, 5, 20 }, | |
304 | { 200, FREQ_SCALE_KHZ, 32, 5, 10 }, | |
305 | { 100, FREQ_SCALE_KHZ, 32, 5, 5 }, | |
306 | { 50, FREQ_SCALE_KHZ, 33, 5, 5 }, | |
307 | { 25, FREQ_SCALE_KHZ, 49, 5, 25 }, | |
308 | { 5, FREQ_SCALE_KHZ, 50, 5, 10 }, | |
309 | { 1, FREQ_SCALE_KHZ, 64, 5, 5 }, | |
310 | { 500, FREQ_SCALE_HZ, 64, 10, 5 }, | |
311 | { 100, FREQ_SCALE_HZ, 68, 5, 8 }, | |
312 | { 0, 0, 0, 0, 0 } | |
313 | }; | |
314 | ||
315 | int i; | |
316 | ||
317 | for (i = 0; f[i].freq; i++) { | |
318 | if (scale == f[i].scale && freq == f[i].freq) | |
319 | break; | |
320 | } | |
321 | if (!f[i].freq) | |
322 | return -1; | |
323 | ||
6d116114 | 324 | sr_dbg("Setting samplerate regs (freq=%d, scale=%d): " |
0ab0cb94 TY |
325 | "reg0: %d, reg1: %d, reg2: %d, reg3: %d.", |
326 | freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel); | |
327 | ||
328 | if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0) | |
329 | return -1; | |
330 | ||
331 | if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0) | |
332 | return -1; | |
333 | ||
334 | if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0) | |
335 | return -1; | |
336 | ||
337 | if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0) | |
338 | return -1; | |
339 | ||
340 | return 0; | |
341 | } | |
a1bb33af | 342 | |
fed16f06 UH |
343 | static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh, |
344 | unsigned int address) | |
a1bb33af | 345 | { |
fed16f06 UH |
346 | gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF); |
347 | gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF); | |
a1bb33af UH |
348 | gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF); |
349 | } | |
350 | ||
fed16f06 UH |
351 | static void __analyzer_set_triggerbar_address(libusb_device_handle *devh, |
352 | unsigned int address) | |
a1bb33af | 353 | { |
fed16f06 UH |
354 | gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF); |
355 | gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF); | |
a1bb33af UH |
356 | gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF); |
357 | } | |
358 | ||
fed16f06 UH |
359 | static void __analyzer_set_compression(libusb_device_handle *devh, |
360 | unsigned int type) | |
a1bb33af UH |
361 | { |
362 | gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF); | |
363 | gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF); | |
364 | } | |
365 | ||
fed16f06 UH |
366 | static void __analyzer_set_trigger_count(libusb_device_handle *devh, |
367 | unsigned int count) | |
a1bb33af UH |
368 | { |
369 | gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF); | |
370 | gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF); | |
371 | } | |
372 | ||
373 | static void analyzer_write_enable_insert_data(libusb_device_handle *devh) | |
374 | { | |
375 | gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12); | |
376 | gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34); | |
377 | gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56); | |
378 | gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78); | |
379 | } | |
380 | ||
381 | static void analyzer_set_filter(libusb_device_handle *devh) | |
382 | { | |
383 | int i; | |
384 | gl_reg_write(devh, FILTER_ENABLE, g_filter_enable); | |
385 | for (i = 0; i < 8; i++) | |
386 | gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]); | |
387 | } | |
388 | ||
ca070ed9 | 389 | SR_PRIV void analyzer_reset(libusb_device_handle *devh) |
a1bb33af | 390 | { |
fed16f06 UH |
391 | analyzer_write_status(devh, 3, STATUS_FLAG_NONE); // reset device |
392 | analyzer_write_status(devh, 3, STATUS_FLAG_RESET); // reset device | |
a1bb33af UH |
393 | } |
394 | ||
ca070ed9 | 395 | SR_PRIV void analyzer_initialize(libusb_device_handle *devh) |
a1bb33af UH |
396 | { |
397 | analyzer_write_status(devh, 1, STATUS_FLAG_NONE); | |
398 | analyzer_write_status(devh, 1, STATUS_FLAG_INIT); | |
399 | analyzer_write_status(devh, 1, STATUS_FLAG_NONE); | |
400 | } | |
401 | ||
ca070ed9 | 402 | SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset) |
a1bb33af UH |
403 | { |
404 | int status; | |
6d116114 | 405 | |
fed16f06 | 406 | while (1) { |
bb7ef793 | 407 | status = gl_reg_read(devh, DEV_STATUS); |
d20844e2 | 408 | if ((!set || (status & set)) && ((status & unset) == 0)) |
a1bb33af UH |
409 | return; |
410 | } | |
411 | } | |
412 | ||
ca070ed9 | 413 | SR_PRIV void analyzer_read_start(libusb_device_handle *devh) |
a1bb33af | 414 | { |
a1bb33af UH |
415 | analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ); |
416 | ||
aad03192 RD |
417 | /* Prep for bulk reads */ |
418 | gl_reg_read_buf(devh, READ_RAM_STATUS, NULL, 0); | |
a1bb33af UH |
419 | } |
420 | ||
ca070ed9 | 421 | SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer, |
fed16f06 | 422 | unsigned int size) |
a1bb33af UH |
423 | { |
424 | return gl_read_bulk(devh, buffer, size); | |
425 | } | |
426 | ||
ca070ed9 | 427 | SR_PRIV void analyzer_read_stop(libusb_device_handle *devh) |
a1bb33af UH |
428 | { |
429 | analyzer_write_status(devh, 3, STATUS_FLAG_20); | |
430 | analyzer_write_status(devh, 3, STATUS_FLAG_NONE); | |
431 | } | |
432 | ||
ca070ed9 | 433 | SR_PRIV void analyzer_start(libusb_device_handle *devh) |
a1bb33af UH |
434 | { |
435 | analyzer_write_status(devh, 1, STATUS_FLAG_NONE); | |
436 | analyzer_write_status(devh, 1, STATUS_FLAG_INIT); | |
437 | analyzer_write_status(devh, 1, STATUS_FLAG_NONE); | |
438 | analyzer_write_status(devh, 1, STATUS_FLAG_GO); | |
439 | } | |
440 | ||
ca070ed9 | 441 | SR_PRIV void analyzer_configure(libusb_device_handle *devh) |
a1bb33af | 442 | { |
fed16f06 UH |
443 | int i; |
444 | ||
445 | /* Write_Start_Status */ | |
a1bb33af UH |
446 | analyzer_write_status(devh, 1, STATUS_FLAG_RESET); |
447 | analyzer_write_status(devh, 1, STATUS_FLAG_NONE); | |
448 | ||
fed16f06 | 449 | /* Start_Config_Outside_Device ? */ |
a1bb33af UH |
450 | analyzer_write_status(devh, 1, STATUS_FLAG_INIT); |
451 | analyzer_write_status(devh, 1, STATUS_FLAG_NONE); | |
452 | ||
fed16f06 | 453 | /* SetData_To_Frequence_Reg */ |
a1bb33af UH |
454 | __analyzer_set_freq(devh, g_freq_value, g_freq_scale); |
455 | ||
fed16f06 | 456 | /* SetMemory_Length */ |
a1bb33af UH |
457 | gl_reg_write(devh, MEMORY_LENGTH, g_memory_size); |
458 | ||
fed16f06 | 459 | /* Sele_Inside_Outside_Clock */ |
a1bb33af UH |
460 | gl_reg_write(devh, CLOCK_SOURCE, 0x03); |
461 | ||
fed16f06 | 462 | /* Set_Trigger_Status */ |
a1bb33af UH |
463 | for (i = 0; i < 9; i++) |
464 | gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]); | |
465 | ||
466 | __analyzer_set_trigger_count(devh, g_trigger_count); | |
467 | ||
fed16f06 | 468 | /* Set_Trigger_Level */ |
7142d6b9 RD |
469 | gl_reg_write(devh, TRIGGER_LEVEL0, g_thresh); |
470 | gl_reg_write(devh, TRIGGER_LEVEL1, g_thresh); | |
471 | gl_reg_write(devh, TRIGGER_LEVEL2, g_thresh); | |
472 | gl_reg_write(devh, TRIGGER_LEVEL3, g_thresh); | |
a1bb33af | 473 | |
fed16f06 UH |
474 | /* Size of actual memory >> 2 */ |
475 | __analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr); | |
a1bb33af UH |
476 | __analyzer_set_triggerbar_address(devh, g_triggerbar_addr); |
477 | ||
fed16f06 | 478 | /* Set_Dont_Care_TriggerBar */ |
bc059b42 | 479 | gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01); |
a1bb33af | 480 | |
fed16f06 | 481 | /* Enable_Status */ |
a1bb33af UH |
482 | analyzer_set_filter(devh); |
483 | ||
fed16f06 | 484 | /* Set_Enable_Delay_Time */ |
a1bb33af UH |
485 | gl_reg_write(devh, 0x7a, 0x00); |
486 | gl_reg_write(devh, 0x7b, 0x00); | |
487 | analyzer_write_enable_insert_data(devh); | |
fed16f06 | 488 | __analyzer_set_compression(devh, g_compression); |
a1bb33af UH |
489 | } |
490 | ||
28731bab | 491 | SR_PRIV int analyzer_add_triggers(const struct sr_dev_inst *sdi) |
a1bb33af | 492 | { |
28731bab BV |
493 | struct dev_context *devc; |
494 | struct sr_trigger *trigger; | |
495 | struct sr_trigger_stage *stage; | |
496 | struct sr_trigger_match *match; | |
497 | GSList *l, *m; | |
498 | int channel; | |
499 | ||
500 | devc = sdi->priv; | |
501 | ||
0812c40e | 502 | if (!(trigger = sr_session_trigger_get(sdi->session))) |
28731bab BV |
503 | return SR_OK; |
504 | ||
505 | for (l = trigger->stages; l; l = l->next) { | |
506 | stage = l->data; | |
507 | for (m = stage->matches; m; m = m->next) { | |
508 | match = m->data; | |
509 | devc->trigger = 1; | |
510 | if (!match->channel->enabled) | |
511 | /* Ignore disabled channels with a trigger. */ | |
512 | continue; | |
513 | channel = match->channel->index; | |
514 | switch (match->match) { | |
515 | case SR_TRIGGER_ZERO: | |
516 | g_trigger_status[channel / 4] |= 2 << (channel % 4 * 2); | |
517 | case SR_TRIGGER_ONE: | |
518 | g_trigger_status[channel / 4] |= 1 << (channel % 4 * 2); | |
519 | break; | |
520 | default: | |
521 | sr_err("Unsupported match %d", match->match); | |
522 | return SR_ERR; | |
523 | } | |
524 | } | |
a1bb33af | 525 | } |
28731bab BV |
526 | |
527 | return SR_OK; | |
a1bb33af UH |
528 | } |
529 | ||
ca070ed9 | 530 | SR_PRIV void analyzer_add_filter(int channel, int type) |
a1bb33af | 531 | { |
fed16f06 UH |
532 | int i; |
533 | ||
a1bb33af UH |
534 | if (type != FILTER_HIGH && type != FILTER_LOW) |
535 | return; | |
536 | if ((channel & 0xf) >= 8) | |
537 | return; | |
538 | ||
a1bb33af UH |
539 | if (channel & CHANNEL_A) |
540 | i = 0; | |
541 | else if (channel & CHANNEL_B) | |
542 | i = 2; | |
543 | else if (channel & CHANNEL_C) | |
544 | i = 4; | |
545 | else if (channel & CHANNEL_D) | |
546 | i = 6; | |
547 | else | |
548 | return; | |
fed16f06 | 549 | |
a1bb33af UH |
550 | if ((channel & 0xf) >= 4) { |
551 | i++; | |
552 | channel -= 4; | |
553 | } | |
fed16f06 UH |
554 | |
555 | g_filter_status[i] |= | |
556 | 1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0)); | |
557 | ||
a1bb33af UH |
558 | g_filter_enable = 1; |
559 | } | |
560 | ||
ca070ed9 | 561 | SR_PRIV void analyzer_set_trigger_count(int count) |
a1bb33af UH |
562 | { |
563 | g_trigger_count = count; | |
564 | } | |
565 | ||
ca070ed9 | 566 | SR_PRIV void analyzer_set_freq(int freq, int scale) |
a1bb33af UH |
567 | { |
568 | g_freq_value = freq; | |
569 | g_freq_scale = scale; | |
570 | } | |
571 | ||
ca070ed9 | 572 | SR_PRIV void analyzer_set_memory_size(unsigned int size) |
a1bb33af UH |
573 | { |
574 | g_memory_size = size; | |
575 | } | |
576 | ||
ca070ed9 | 577 | SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address) |
a1bb33af UH |
578 | { |
579 | g_ramsize_triggerbar_addr = address; | |
580 | } | |
581 | ||
a864a05b RD |
582 | SR_PRIV unsigned int analyzer_get_ramsize_trigger_address(void) |
583 | { | |
584 | return g_ramsize_triggerbar_addr; | |
585 | } | |
586 | ||
ca070ed9 | 587 | SR_PRIV void analyzer_set_triggerbar_address(unsigned int address) |
a1bb33af UH |
588 | { |
589 | g_triggerbar_addr = address; | |
590 | } | |
591 | ||
a864a05b RD |
592 | SR_PRIV unsigned int analyzer_get_triggerbar_address(void) |
593 | { | |
594 | return g_triggerbar_addr; | |
595 | } | |
596 | ||
0ab0cb94 TY |
597 | SR_PRIV unsigned int analyzer_read_status(libusb_device_handle *devh) |
598 | { | |
599 | return gl_reg_read(devh, DEV_STATUS); | |
600 | } | |
601 | ||
ca070ed9 | 602 | SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh) |
a1bb33af | 603 | { |
bb7ef793 | 604 | return gl_reg_read(devh, DEV_ID1) << 8 | gl_reg_read(devh, DEV_ID0); |
a1bb33af UH |
605 | } |
606 | ||
ca070ed9 | 607 | SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh) |
a1bb33af | 608 | { |
fed16f06 UH |
609 | return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh, |
610 | STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0); | |
a1bb33af UH |
611 | } |
612 | ||
ca070ed9 | 613 | SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh) |
a1bb33af | 614 | { |
fed16f06 UH |
615 | return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh, |
616 | NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0); | |
a1bb33af UH |
617 | } |
618 | ||
ca070ed9 | 619 | SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh) |
a1bb33af | 620 | { |
fed16f06 UH |
621 | return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh, |
622 | TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0); | |
a1bb33af UH |
623 | } |
624 | ||
ca070ed9 | 625 | SR_PRIV void analyzer_set_compression(unsigned int type) |
a1bb33af UH |
626 | { |
627 | g_compression = type; | |
628 | } | |
629 | ||
7142d6b9 RD |
630 | SR_PRIV void analyzer_set_voltage_threshold(int thresh) |
631 | { | |
632 | g_thresh = thresh; | |
633 | } | |
634 | ||
ca070ed9 | 635 | SR_PRIV void analyzer_wait_button(libusb_device_handle *devh) |
a1bb33af UH |
636 | { |
637 | analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0); | |
638 | } | |
639 | ||
ca070ed9 | 640 | SR_PRIV void analyzer_wait_data(libusb_device_handle *devh) |
a1bb33af | 641 | { |
d20844e2 | 642 | analyzer_wait(devh, 0, STATUS_BUSY); |
a1bb33af UH |
643 | } |
644 | ||
ca070ed9 UH |
645 | SR_PRIV int analyzer_decompress(void *input, unsigned int input_len, |
646 | void *output, unsigned int output_len) | |
a1bb33af UH |
647 | { |
648 | unsigned char *in = input; | |
649 | unsigned char *out = output; | |
650 | unsigned int A, B, C, count; | |
651 | unsigned int written = 0; | |
652 | ||
653 | while (input_len > 0) { | |
654 | A = *in++; | |
655 | B = *in++; | |
656 | C = *in++; | |
657 | count = (*in++) + 1; | |
658 | ||
659 | if (count > output_len) | |
660 | count = output_len; | |
661 | output_len -= count; | |
662 | written += count; | |
663 | ||
664 | while (count--) { | |
665 | *out++ = A; | |
666 | *out++ = B; | |
667 | *out++ = C; | |
fed16f06 | 668 | *out++ = 0; /* Channel D */ |
a1bb33af UH |
669 | } |
670 | ||
671 | input_len -= 4; | |
672 | if (output_len == 0) | |
673 | break; | |
674 | } | |
675 | ||
676 | return written; | |
677 | } |