]>
Commit | Line | Data |
---|---|---|
be64f90b DE |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2015 Daniel Elstner <daniel.kitta@gmail.com> | |
5 | * | |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 3 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <config.h> | |
21 | #include "lwla.h" | |
22 | #include "protocol.h" | |
23 | ||
ca314e06 | 24 | /* Number of logic channels. */ |
be64f90b DE |
25 | #define NUM_CHANNELS 34 |
26 | ||
ca314e06 | 27 | /* Bit mask covering all logic channels. */ |
be64f90b DE |
28 | #define ALL_CHANNELS_MASK ((UINT64_C(1) << NUM_CHANNELS) - 1) |
29 | ||
ca314e06 | 30 | /* Unit size for the sigrok logic datafeed. */ |
be64f90b DE |
31 | #define UNIT_SIZE ((NUM_CHANNELS + 7) / 8) |
32 | ||
ca314e06 | 33 | /* Size of the acquisition buffer in device memory units. */ |
be64f90b DE |
34 | #define MEMORY_DEPTH (256 * 1024) /* 256k x 36 bit */ |
35 | ||
ca314e06 | 36 | /* Capture memory read start address. */ |
78648577 | 37 | #define READ_START_ADDR 4 |
be64f90b DE |
38 | |
39 | /* Number of device memory units (36 bit) to read at a time. Slices of 8 | |
40 | * consecutive 36-bit words are mapped to 9 32-bit words each, so the chunk | |
41 | * length should be a multiple of 8 to ensure alignment to slice boundaries. | |
42 | * | |
43 | * Experimentation has shown that reading chunks larger than about 1024 bytes | |
44 | * is unreliable. The threshold seems to relate to the buffer size on the FX2 | |
45 | * USB chip: The configured endpoint buffer size is 512, and with double or | |
46 | * triple buffering enabled a multiple of 512 bytes can be kept in fly. | |
47 | * | |
48 | * The vendor software limits reads to 120 words (15 slices, 540 bytes) at | |
49 | * a time. So far, it appears safe to increase this to 224 words (28 slices, | |
50 | * 1008 bytes), thus making the most of two 512 byte buffers. | |
51 | */ | |
78648577 | 52 | #define READ_CHUNK_LEN (28 * 8) |
be64f90b | 53 | |
ca314e06 | 54 | /* Bit mask for the RLE repeat-count-follows flag. */ |
be64f90b DE |
55 | #define RLE_FLAG_LEN_FOLLOWS (UINT64_C(1) << 35) |
56 | ||
940805ce DE |
57 | /* Start index and count for bulk long register reads. |
58 | * The first five long registers do not return useful values when read, | |
59 | * so skip over them to reduce the transfer size of status poll responses. | |
60 | */ | |
61 | #define READ_LREGS_START LREG_MEM_FILL | |
62 | #define READ_LREGS_COUNT (LREG_STATUS + 1 - READ_LREGS_START) | |
63 | ||
ca314e06 | 64 | /** LWLA1034 register addresses. */ |
be64f90b DE |
65 | enum reg_addr { |
66 | REG_MEM_CTRL = 0x1074, /* capture buffer control */ | |
67 | REG_MEM_FILL = 0x1078, /* capture buffer fill level */ | |
68 | REG_MEM_START = 0x107C, /* capture buffer start address */ | |
69 | ||
70 | REG_CLK_BOOST = 0x1094, /* logic clock boost flag */ | |
71 | ||
72 | REG_LONG_STROBE = 0x10B0, /* long register read/write strobe */ | |
73 | REG_LONG_ADDR = 0x10B4, /* long register address */ | |
74 | REG_LONG_LOW = 0x10B8, /* long register low word */ | |
75 | REG_LONG_HIGH = 0x10BC, /* long register high word */ | |
76 | }; | |
77 | ||
ca314e06 | 78 | /** Flag bits for REG_MEM_CTRL. */ |
be64f90b DE |
79 | enum mem_ctrl_flag { |
80 | MEM_CTRL_WRITE = 1 << 0, /* "wr1rd0" bit */ | |
81 | MEM_CTRL_CLR_IDX = 1 << 1, /* "clr_idx" bit */ | |
82 | }; | |
83 | ||
ca314e06 | 84 | /* LWLA1034 long register addresses. */ |
be64f90b DE |
85 | enum long_reg_addr { |
86 | LREG_CHAN_MASK = 0, /* channel enable mask */ | |
87 | LREG_DIV_COUNT = 1, /* clock divider max count */ | |
88 | LREG_TRG_VALUE = 2, /* trigger level/slope bits */ | |
89 | LREG_TRG_TYPE = 3, /* trigger type bits (level or edge) */ | |
90 | LREG_TRG_ENABLE = 4, /* trigger enable mask */ | |
91 | LREG_MEM_FILL = 5, /* capture memory fill level or limit */ | |
92 | ||
93 | LREG_DURATION = 7, /* elapsed time in ms (0.8 ms at 125 MS/s) */ | |
94 | LREG_CHAN_STATE = 8, /* current logic levels at the inputs */ | |
95 | LREG_STATUS = 9, /* capture status flags */ | |
96 | ||
97 | LREG_CAP_CTRL = 10, /* capture control bits */ | |
98 | LREG_TEST_ID = 100, /* constant test ID */ | |
99 | }; | |
100 | ||
ca314e06 | 101 | /** Flag bits for LREG_CAP_CTRL. */ |
be64f90b DE |
102 | enum cap_ctrl_flag { |
103 | CAP_CTRL_TRG_EN = 1 << 0, /* "trg_en" bit */ | |
104 | CAP_CTRL_CLR_TIMEBASE = 1 << 2, /* "do_clr_timebase" bit */ | |
105 | CAP_CTRL_FLUSH_FIFO = 1 << 4, /* "flush_fifo" bit */ | |
106 | CAP_CTRL_CLR_FIFOFULL = 1 << 5, /* "clr_fifo32_ful" bit */ | |
107 | CAP_CTRL_CLR_COUNTER = 1 << 6, /* "clr_cntr0" bit */ | |
108 | }; | |
109 | ||
ca314e06 | 110 | /* Available FPGA configurations. */ |
be64f90b DE |
111 | enum fpga_config { |
112 | FPGA_OFF = 0, /* FPGA shutdown config */ | |
113 | FPGA_INT, /* internal clock config */ | |
114 | FPGA_EXTPOS, /* external clock, rising edge config */ | |
115 | FPGA_EXTNEG, /* external clock, falling edge config */ | |
116 | }; | |
117 | ||
ca314e06 | 118 | /* FPGA bitstream resource filenames. */ |
be64f90b DE |
119 | static const char bitstream_map[][32] = { |
120 | [FPGA_OFF] = "sysclk-lwla1034-off.rbf", | |
121 | [FPGA_INT] = "sysclk-lwla1034-int.rbf", | |
122 | [FPGA_EXTPOS] = "sysclk-lwla1034-extpos.rbf", | |
123 | [FPGA_EXTNEG] = "sysclk-lwla1034-extneg.rbf", | |
124 | }; | |
125 | ||
ca314e06 | 126 | /* Read 64-bit long register. */ |
be64f90b DE |
127 | static int read_long_reg(const struct sr_usb_dev_inst *usb, |
128 | uint32_t addr, uint64_t *value) | |
129 | { | |
130 | uint32_t low, high, dummy; | |
131 | int ret; | |
132 | ||
133 | ret = lwla_write_reg(usb, REG_LONG_ADDR, addr); | |
134 | if (ret != SR_OK) | |
135 | return ret; | |
136 | ||
137 | ret = lwla_read_reg(usb, REG_LONG_STROBE, &dummy); | |
138 | if (ret != SR_OK) | |
139 | return ret; | |
140 | ||
141 | ret = lwla_read_reg(usb, REG_LONG_HIGH, &high); | |
142 | if (ret != SR_OK) | |
143 | return ret; | |
144 | ||
145 | ret = lwla_read_reg(usb, REG_LONG_LOW, &low); | |
146 | if (ret != SR_OK) | |
147 | return ret; | |
148 | ||
149 | *value = ((uint64_t)high << 32) | low; | |
150 | ||
151 | return SR_OK; | |
152 | } | |
153 | ||
ca314e06 | 154 | /* Queue access sequence for a long register write. */ |
be64f90b DE |
155 | static void queue_long_regval(struct acquisition_state *acq, |
156 | uint32_t addr, uint64_t value) | |
157 | { | |
158 | lwla_queue_regval(acq, REG_LONG_ADDR, addr); | |
159 | lwla_queue_regval(acq, REG_LONG_LOW, value & 0xFFFFFFFF); | |
160 | lwla_queue_regval(acq, REG_LONG_HIGH, value >> 32); | |
161 | lwla_queue_regval(acq, REG_LONG_STROBE, 0); | |
162 | } | |
163 | ||
ca314e06 | 164 | /* Helper to fill in the long register bulk write command. */ |
be64f90b | 165 | static inline void bulk_long_set(struct acquisition_state *acq, |
7ed80817 | 166 | unsigned int idx, uint64_t value) |
be64f90b DE |
167 | { |
168 | acq->xfer_buf_out[4 * idx + 3] = LWLA_WORD_0(value); | |
169 | acq->xfer_buf_out[4 * idx + 4] = LWLA_WORD_1(value); | |
170 | acq->xfer_buf_out[4 * idx + 5] = LWLA_WORD_2(value); | |
171 | acq->xfer_buf_out[4 * idx + 6] = LWLA_WORD_3(value); | |
172 | } | |
173 | ||
ca314e06 | 174 | /* Helper for dissecting the response to a long register bulk read. */ |
be64f90b | 175 | static inline uint64_t bulk_long_get(const struct acquisition_state *acq, |
7ed80817 | 176 | unsigned int idx) |
be64f90b DE |
177 | { |
178 | uint64_t low, high; | |
179 | ||
940805ce DE |
180 | low = LWLA_TO_UINT32(acq->xfer_buf_in[2 * (idx - READ_LREGS_START)]); |
181 | high = LWLA_TO_UINT32(acq->xfer_buf_in[2 * (idx - READ_LREGS_START) + 1]); | |
be64f90b DE |
182 | |
183 | return (high << 32) | low; | |
184 | } | |
185 | ||
186 | /* Demangle and decompress incoming sample data from the transfer buffer. | |
187 | * The data chunk is taken from the acquisition state, and is expected to | |
188 | * contain a multiple of 8 packed 36-bit words. | |
189 | */ | |
190 | static void read_response(struct acquisition_state *acq) | |
191 | { | |
192 | uint64_t sample, high_nibbles, word; | |
193 | uint32_t *slice; | |
194 | uint8_t *out_p; | |
d64b5f43 | 195 | unsigned int words_left, max_samples, run_samples, wi, ri, si; |
be64f90b DE |
196 | |
197 | /* Number of 36-bit words remaining in the transfer buffer. */ | |
198 | words_left = MIN(acq->mem_addr_next, acq->mem_addr_stop) | |
199 | - acq->mem_addr_done; | |
200 | ||
201 | for (wi = 0;; wi++) { | |
202 | /* Calculate number of samples to write into packet. */ | |
203 | max_samples = MIN(acq->samples_max - acq->samples_done, | |
204 | PACKET_SIZE / UNIT_SIZE - acq->out_index); | |
205 | run_samples = MIN(max_samples, acq->run_len); | |
206 | ||
207 | /* Expand run-length samples into session packet. */ | |
208 | sample = acq->sample; | |
209 | out_p = &acq->out_packet[acq->out_index * UNIT_SIZE]; | |
210 | ||
211 | for (ri = 0; ri < run_samples; ri++) { | |
212 | out_p[0] = sample & 0xFF; | |
213 | out_p[1] = (sample >> 8) & 0xFF; | |
214 | out_p[2] = (sample >> 16) & 0xFF; | |
215 | out_p[3] = (sample >> 24) & 0xFF; | |
216 | out_p[4] = (sample >> 32) & 0xFF; | |
217 | out_p += UNIT_SIZE; | |
218 | } | |
219 | acq->run_len -= run_samples; | |
220 | acq->out_index += run_samples; | |
221 | acq->samples_done += run_samples; | |
222 | ||
223 | if (run_samples == max_samples) | |
d64b5f43 | 224 | break; /* Packet full or sample limit reached. */ |
be64f90b | 225 | if (wi >= words_left) |
d64b5f43 | 226 | break; /* Done with current transfer. */ |
be64f90b DE |
227 | |
228 | /* Get the current slice of 8 packed 36-bit words. */ | |
229 | slice = &acq->xfer_buf_in[(acq->in_index + wi) / 8 * 9]; | |
d64b5f43 | 230 | si = (acq->in_index + wi) % 8; /* Word index within slice. */ |
be64f90b DE |
231 | |
232 | /* Extract the next 36-bit word. */ | |
233 | high_nibbles = LWLA_TO_UINT32(slice[8]); | |
234 | word = LWLA_TO_UINT32(slice[si]); | |
235 | word |= (high_nibbles << (4 * si + 4)) & (UINT64_C(0xF) << 32); | |
236 | ||
237 | if (acq->rle == RLE_STATE_DATA) { | |
238 | acq->sample = word & ALL_CHANNELS_MASK; | |
239 | acq->run_len = ((word >> NUM_CHANNELS) & 1) + 1; | |
240 | acq->rle = ((word & RLE_FLAG_LEN_FOLLOWS) != 0) | |
241 | ? RLE_STATE_LEN : RLE_STATE_DATA; | |
242 | } else { | |
243 | acq->run_len += word << 1; | |
244 | acq->rle = RLE_STATE_DATA; | |
245 | } | |
246 | } | |
d64b5f43 | 247 | |
be64f90b DE |
248 | acq->in_index += wi; |
249 | acq->mem_addr_done += wi; | |
250 | } | |
251 | ||
78648577 DE |
252 | /* Check whether we can receive responses of more than 64 bytes. |
253 | * The FX2 firmware of the LWLA1034 has a bug in the reset logic which | |
254 | * sometimes causes the response endpoint to be limited to transfers of | |
255 | * 64 bytes at a time, instead of the expected 2*512 bytes. The problem | |
256 | * can be worked around by never requesting more than 64 bytes. | |
257 | * This quirk manifests itself only under certain conditions, and some | |
258 | * users seem to see it more frequently than others. Detect it here in | |
259 | * order to avoid paying the penalty unnecessarily. | |
260 | */ | |
261 | static int detect_short_transfer_quirk(const struct sr_dev_inst *sdi) | |
262 | { | |
263 | struct dev_context *devc; | |
264 | struct sr_usb_dev_inst *usb; | |
d64b5f43 | 265 | int xfer_len, ret; |
78648577 DE |
266 | uint16_t command[3]; |
267 | unsigned char buf[512]; | |
78648577 DE |
268 | const int lreg_count = 10; |
269 | ||
270 | devc = sdi->priv; | |
d9251a2c | 271 | usb = sdi->conn; |
78648577 DE |
272 | |
273 | command[0] = LWLA_WORD(CMD_READ_LREGS); | |
274 | command[1] = LWLA_WORD(0); | |
275 | command[2] = LWLA_WORD(lreg_count); | |
276 | ||
53012da6 | 277 | ret = lwla_send_command(usb, ARRAY_AND_SIZE(command)); |
78648577 DE |
278 | if (ret != SR_OK) |
279 | return ret; | |
280 | ||
281 | ret = lwla_receive_reply(usb, buf, sizeof(buf), &xfer_len); | |
282 | if (ret != SR_OK) | |
283 | return ret; | |
284 | ||
285 | devc->short_transfer_quirk = (xfer_len == 64); | |
286 | ||
287 | if (xfer_len == 8 * lreg_count) | |
288 | return SR_OK; | |
289 | ||
290 | if (xfer_len == 64) { | |
291 | /* Drain the tailing portion of the split transfer. */ | |
292 | ret = lwla_receive_reply(usb, buf, sizeof(buf), &xfer_len); | |
293 | if (ret != SR_OK) | |
294 | return ret; | |
295 | ||
296 | if (xfer_len == 8 * lreg_count - 64) | |
297 | return SR_OK; | |
298 | } | |
299 | sr_err("Received response of unexpected length %d.", xfer_len); | |
300 | ||
301 | return SR_ERR; | |
302 | } | |
303 | ||
ca314e06 | 304 | /* Select and transfer FPGA bitstream for the current configuration. */ |
be64f90b DE |
305 | static int apply_fpga_config(const struct sr_dev_inst *sdi) |
306 | { | |
307 | struct dev_context *devc; | |
308 | struct drv_context *drvc; | |
d64b5f43 | 309 | int config, ret; |
be64f90b DE |
310 | |
311 | devc = sdi->priv; | |
312 | drvc = sdi->driver->context; | |
313 | ||
314 | if (sdi->status == SR_ST_INACTIVE) | |
315 | config = FPGA_OFF; | |
316 | else if (devc->cfg_clock_source == CLOCK_INTERNAL) | |
317 | config = FPGA_INT; | |
318 | else if (devc->cfg_clock_edge == EDGE_POSITIVE) | |
319 | config = FPGA_EXTPOS; | |
320 | else | |
321 | config = FPGA_EXTNEG; | |
322 | ||
323 | if (config == devc->active_fpga_config) | |
d64b5f43 | 324 | return SR_OK; /* No change. */ |
be64f90b DE |
325 | |
326 | ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn, | |
327 | bitstream_map[config]); | |
328 | devc->active_fpga_config = (ret == SR_OK) ? config : FPGA_NOCONF; | |
329 | ||
330 | return ret; | |
331 | } | |
332 | ||
ca314e06 | 333 | /* Perform initialization self test. */ |
be64f90b DE |
334 | static int device_init_check(const struct sr_dev_inst *sdi) |
335 | { | |
336 | uint64_t value; | |
337 | int ret; | |
338 | ||
e35a4592 | 339 | read_long_reg(sdi->conn, LREG_TEST_ID, &value); |
be64f90b DE |
340 | |
341 | /* Ignore the value returned by the first read. */ | |
342 | ret = read_long_reg(sdi->conn, LREG_TEST_ID, &value); | |
343 | if (ret != SR_OK) | |
344 | return ret; | |
345 | ||
346 | if (value != UINT64_C(0x1234567887654321)) { | |
347 | sr_err("Received invalid test word 0x%016" PRIX64 ".", value); | |
348 | return SR_ERR; | |
349 | } | |
78648577 DE |
350 | |
351 | return detect_short_transfer_quirk(sdi); | |
be64f90b DE |
352 | } |
353 | ||
ca314e06 | 354 | /* Set up the device in preparation for an acquisition session. */ |
be64f90b DE |
355 | static int setup_acquisition(const struct sr_dev_inst *sdi) |
356 | { | |
1d80e1c6 DE |
357 | static const struct regval capture_init[] = { |
358 | {REG_MEM_CTRL, MEM_CTRL_CLR_IDX}, | |
359 | {REG_MEM_CTRL, MEM_CTRL_WRITE}, | |
360 | {REG_LONG_ADDR, LREG_CAP_CTRL}, | |
361 | {REG_LONG_LOW, CAP_CTRL_CLR_TIMEBASE | CAP_CTRL_FLUSH_FIFO | | |
362 | CAP_CTRL_CLR_FIFOFULL | CAP_CTRL_CLR_COUNTER}, | |
363 | {REG_LONG_HIGH, 0}, | |
364 | {REG_LONG_STROBE, 0}, | |
365 | }; | |
d64b5f43 | 366 | uint64_t divider_count, trigger_mask; |
be64f90b DE |
367 | struct dev_context *devc; |
368 | struct sr_usb_dev_inst *usb; | |
369 | struct acquisition_state *acq; | |
370 | int ret; | |
371 | ||
372 | devc = sdi->priv; | |
d9251a2c UH |
373 | usb = sdi->conn; |
374 | acq = devc->acquisition; | |
be64f90b | 375 | |
53012da6 | 376 | ret = lwla_write_regs(usb, ARRAY_AND_SIZE(capture_init)); |
1d80e1c6 DE |
377 | if (ret != SR_OK) |
378 | return ret; | |
be64f90b | 379 | |
1d80e1c6 | 380 | ret = lwla_write_reg(usb, REG_CLK_BOOST, acq->clock_boost); |
be64f90b DE |
381 | if (ret != SR_OK) |
382 | return ret; | |
383 | ||
384 | acq->xfer_buf_out[0] = LWLA_WORD(CMD_WRITE_LREGS); | |
385 | acq->xfer_buf_out[1] = LWLA_WORD(0); | |
386 | acq->xfer_buf_out[2] = LWLA_WORD(LREG_STATUS + 1); | |
387 | ||
388 | bulk_long_set(acq, LREG_CHAN_MASK, devc->channel_mask); | |
389 | ||
390 | if (devc->samplerate > 0 && devc->samplerate <= SR_MHZ(100) | |
391 | && !acq->clock_boost) | |
392 | divider_count = SR_MHZ(100) / devc->samplerate - 1; | |
393 | else | |
394 | divider_count = 0; | |
395 | ||
396 | bulk_long_set(acq, LREG_DIV_COUNT, divider_count); | |
397 | bulk_long_set(acq, LREG_TRG_VALUE, devc->trigger_values); | |
d9251a2c | 398 | bulk_long_set(acq, LREG_TRG_TYPE, devc->trigger_edge_mask); |
be64f90b DE |
399 | |
400 | trigger_mask = devc->trigger_mask; | |
401 | ||
402 | /* Set bits to select external TRG input edge. */ | |
403 | if (devc->cfg_trigger_source == TRIGGER_EXT_TRG) | |
404 | switch (devc->cfg_trigger_slope) { | |
405 | case EDGE_POSITIVE: | |
406 | trigger_mask |= UINT64_C(1) << 35; | |
407 | break; | |
408 | case EDGE_NEGATIVE: | |
409 | trigger_mask |= UINT64_C(1) << 34; | |
410 | break; | |
411 | } | |
412 | ||
413 | bulk_long_set(acq, LREG_TRG_ENABLE, trigger_mask); | |
414 | ||
415 | /* Set the capture memory full threshold. This is slightly less | |
416 | * than the actual maximum, most likely in order to compensate for | |
417 | * pipeline latency. | |
418 | */ | |
419 | bulk_long_set(acq, LREG_MEM_FILL, MEMORY_DEPTH - 16); | |
420 | ||
421 | /* Fill remaining words with zeroes. */ | |
422 | bulk_long_set(acq, 6, 0); | |
423 | bulk_long_set(acq, LREG_DURATION, 0); | |
424 | bulk_long_set(acq, LREG_CHAN_STATE, 0); | |
425 | bulk_long_set(acq, LREG_STATUS, 0); | |
426 | ||
427 | return lwla_send_command(sdi->conn, acq->xfer_buf_out, | |
428 | 3 + (LREG_STATUS + 1) * 4); | |
429 | } | |
430 | ||
431 | static int prepare_request(const struct sr_dev_inst *sdi) | |
432 | { | |
433 | struct dev_context *devc; | |
434 | struct acquisition_state *acq; | |
78648577 | 435 | unsigned int chunk_len, remaining, count; |
be64f90b DE |
436 | |
437 | devc = sdi->priv; | |
438 | acq = devc->acquisition; | |
439 | ||
440 | acq->xfer_out->length = 0; | |
441 | acq->reg_seq_pos = 0; | |
442 | acq->reg_seq_len = 0; | |
443 | ||
444 | switch (devc->state) { | |
445 | case STATE_START_CAPTURE: | |
446 | queue_long_regval(acq, LREG_CAP_CTRL, CAP_CTRL_TRG_EN); | |
447 | break; | |
448 | case STATE_STOP_CAPTURE: | |
449 | queue_long_regval(acq, LREG_CAP_CTRL, 0); | |
450 | lwla_queue_regval(acq, REG_CLK_BOOST, 0); | |
451 | break; | |
452 | case STATE_READ_PREPARE: | |
453 | lwla_queue_regval(acq, REG_CLK_BOOST, 1); | |
454 | lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_CLR_IDX); | |
455 | lwla_queue_regval(acq, REG_MEM_START, READ_START_ADDR); | |
456 | break; | |
457 | case STATE_READ_FINISH: | |
458 | lwla_queue_regval(acq, REG_CLK_BOOST, 0); | |
459 | break; | |
460 | case STATE_STATUS_REQUEST: | |
461 | acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_LREGS); | |
940805ce DE |
462 | acq->xfer_buf_out[1] = LWLA_WORD(READ_LREGS_START); |
463 | acq->xfer_buf_out[2] = LWLA_WORD(READ_LREGS_COUNT); | |
be64f90b DE |
464 | acq->xfer_out->length = 3 * sizeof(acq->xfer_buf_out[0]); |
465 | break; | |
466 | case STATE_LENGTH_REQUEST: | |
467 | lwla_queue_regval(acq, REG_MEM_FILL, 0); | |
468 | break; | |
469 | case STATE_READ_REQUEST: | |
78648577 DE |
470 | /* Limit reads to 8 device words (36 bytes) at a time if the |
471 | * device firmware has the short transfer quirk. */ | |
472 | chunk_len = (devc->short_transfer_quirk) ? 8 : READ_CHUNK_LEN; | |
be64f90b | 473 | /* Always read a multiple of 8 device words. */ |
78648577 DE |
474 | remaining = (acq->mem_addr_stop - acq->mem_addr_next + 7) / 8 * 8; |
475 | count = MIN(chunk_len, remaining); | |
be64f90b DE |
476 | |
477 | acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM36); | |
478 | acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next); | |
479 | acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next); | |
480 | acq->xfer_buf_out[3] = LWLA_WORD_0(count); | |
481 | acq->xfer_buf_out[4] = LWLA_WORD_1(count); | |
482 | acq->xfer_out->length = 5 * sizeof(acq->xfer_buf_out[0]); | |
483 | ||
484 | acq->mem_addr_next += count; | |
485 | break; | |
486 | default: | |
487 | sr_err("BUG: unhandled request state %d.", devc->state); | |
488 | return SR_ERR_BUG; | |
489 | } | |
490 | ||
491 | return SR_OK; | |
492 | } | |
493 | ||
494 | static int handle_response(const struct sr_dev_inst *sdi) | |
495 | { | |
496 | struct dev_context *devc; | |
497 | struct acquisition_state *acq; | |
498 | int expect_len; | |
499 | ||
500 | devc = sdi->priv; | |
d9251a2c | 501 | acq = devc->acquisition; |
be64f90b DE |
502 | |
503 | switch (devc->state) { | |
504 | case STATE_STATUS_REQUEST: | |
940805ce | 505 | if (acq->xfer_in->actual_length != READ_LREGS_COUNT * 8) { |
be64f90b | 506 | sr_err("Received size %d doesn't match expected size %d.", |
940805ce | 507 | acq->xfer_in->actual_length, READ_LREGS_COUNT * 8); |
be64f90b DE |
508 | return SR_ERR; |
509 | } | |
510 | acq->mem_addr_fill = bulk_long_get(acq, LREG_MEM_FILL) & 0xFFFFFFFF; | |
d9251a2c | 511 | acq->duration_now = bulk_long_get(acq, LREG_DURATION); |
be64f90b DE |
512 | /* Shift left by one so the bit positions match the LWLA1016. */ |
513 | acq->status = (bulk_long_get(acq, LREG_STATUS) & 0x3F) << 1; | |
514 | /* | |
515 | * It seems that the 125 MS/s mode is implemented simply by | |
516 | * running the FPGA logic at a 25% higher clock rate. As a | |
517 | * result, the millisecond counter for the capture duration | |
518 | * is also off by 25%, and thus needs to be corrected here. | |
519 | */ | |
520 | if (acq->clock_boost) | |
521 | acq->duration_now = acq->duration_now * 4 / 5; | |
522 | break; | |
523 | case STATE_LENGTH_REQUEST: | |
524 | acq->mem_addr_next = READ_START_ADDR; | |
525 | acq->mem_addr_stop = acq->reg_sequence[0].val; | |
526 | break; | |
527 | case STATE_READ_REQUEST: | |
528 | /* Expect a multiple of 8 36-bit words packed into 9 32-bit | |
529 | * words. */ | |
530 | expect_len = (acq->mem_addr_next - acq->mem_addr_done | |
531 | + acq->in_index + 7) / 8 * 9 * sizeof(acq->xfer_buf_in[0]); | |
532 | ||
533 | if (acq->xfer_in->actual_length != expect_len) { | |
534 | sr_err("Received size %d does not match expected size %d.", | |
535 | acq->xfer_in->actual_length, expect_len); | |
536 | devc->transfer_error = TRUE; | |
537 | return SR_ERR; | |
538 | } | |
539 | read_response(acq); | |
540 | break; | |
541 | default: | |
542 | sr_err("BUG: unhandled response state %d.", devc->state); | |
543 | return SR_ERR_BUG; | |
544 | } | |
545 | ||
546 | return SR_OK; | |
547 | } | |
548 | ||
ca314e06 | 549 | /** Model descriptor for the LWLA1034. */ |
be64f90b DE |
550 | SR_PRIV const struct model_info lwla1034_info = { |
551 | .name = "LWLA1034", | |
552 | .num_channels = NUM_CHANNELS, | |
553 | ||
554 | .num_devopts = 8, | |
555 | .devopts = { | |
556 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, | |
557 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
558 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
559 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, | |
560 | SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET, | |
561 | SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
562 | SR_CONF_TRIGGER_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
563 | SR_CONF_TRIGGER_SLOPE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
564 | }, | |
565 | .num_samplerates = 20, | |
566 | .samplerates = { | |
567 | SR_MHZ(125), SR_MHZ(100), | |
568 | SR_MHZ(50), SR_MHZ(20), SR_MHZ(10), | |
569 | SR_MHZ(5), SR_MHZ(2), SR_MHZ(1), | |
570 | SR_KHZ(500), SR_KHZ(200), SR_KHZ(100), | |
571 | SR_KHZ(50), SR_KHZ(20), SR_KHZ(10), | |
572 | SR_KHZ(5), SR_KHZ(2), SR_KHZ(1), | |
573 | SR_HZ(500), SR_HZ(200), SR_HZ(100), | |
574 | }, | |
575 | ||
576 | .apply_fpga_config = &apply_fpga_config, | |
577 | .device_init_check = &device_init_check, | |
578 | .setup_acquisition = &setup_acquisition, | |
579 | ||
580 | .prepare_request = &prepare_request, | |
581 | .handle_response = &handle_response, | |
582 | }; |