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f4816ac6 ML |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2012 Martin Ling <martin-git@earth.li> | |
88e429c9 | 5 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> |
bafd4890 | 6 | * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de> |
f4816ac6 ML |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include <stdlib.h> | |
e0b7d23c ML |
23 | #include <stdarg.h> |
24 | #include <unistd.h> | |
25 | #include <errno.h> | |
a3df166f | 26 | #include <string.h> |
254dd102 | 27 | #include <math.h> |
bafd4890 ML |
28 | #include <ctype.h> |
29 | #include <time.h> | |
f4816ac6 ML |
30 | #include <glib.h> |
31 | #include "libsigrok.h" | |
32 | #include "libsigrok-internal.h" | |
33 | #include "protocol.h" | |
34 | ||
bafd4890 ML |
35 | /* |
36 | * This is a unified protocol driver for the DS1000 and DS2000 series. | |
37 | * | |
38 | * DS1000 support tested with a Rigol DS1102D. | |
39 | * | |
40 | * DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02. | |
41 | * | |
42 | * The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think) | |
43 | * standard. If you want to read it - it costs real money... | |
44 | * | |
45 | * Every response from the scope has a linefeed appended because the | |
46 | * standard says so. In principle this could be ignored because sending the | |
47 | * next command clears the output queue of the scope. This driver tries to | |
48 | * avoid doing that because it may cause an error being generated inside the | |
49 | * scope and who knows what bugs the firmware has WRT this. | |
50 | * | |
51 | * Waveform data is transferred in a format called "arbitrary block program | |
52 | * data" specified in IEEE 488.2. See Agilents programming manuals for their | |
53 | * 2000/3000 series scopes for a nice description. | |
54 | * | |
55 | * Each data block from the scope has a header, e.g. "#900000001400". | |
56 | * The '#' marks the start of a block. | |
57 | * Next is one ASCII decimal digit between 1 and 9, this gives the number of | |
58 | * ASCII decimal digits following. | |
59 | * Last are the ASCII decimal digits giving the number of bytes (not | |
60 | * samples!) in the block. | |
61 | * | |
62 | * After this header as many data bytes as indicated follow. | |
63 | * | |
64 | * Each data block has a trailing linefeed too. | |
65 | */ | |
66 | ||
bafd4890 ML |
67 | static int parse_int(const char *str, int *ret) |
68 | { | |
69 | char *e; | |
70 | long tmp; | |
71 | ||
72 | errno = 0; | |
73 | tmp = strtol(str, &e, 10); | |
74 | if (e == str || *e != '\0') { | |
75 | sr_dbg("Failed to parse integer: '%s'", str); | |
76 | return SR_ERR; | |
77 | } | |
78 | if (errno) { | |
79 | sr_dbg("Failed to parse integer: '%s', numerical overflow", str); | |
80 | return SR_ERR; | |
81 | } | |
82 | if (tmp > INT_MAX || tmp < INT_MIN) { | |
83 | sr_dbg("Failed to parse integer: '%s', value to large/small", str); | |
84 | return SR_ERR; | |
85 | } | |
86 | ||
87 | *ret = (int)tmp; | |
88 | return SR_OK; | |
89 | } | |
90 | ||
babab622 ML |
91 | /* Set the next event to wait for in rigol_ds_receive */ |
92 | static void rigol_ds_set_wait_event(struct dev_context *devc, enum wait_events event) | |
93 | { | |
94 | if (event == WAIT_STOP) | |
95 | devc->wait_status = 2; | |
96 | else | |
97 | devc->wait_status = 1; | |
98 | devc->wait_event = event; | |
99 | } | |
100 | ||
bafd4890 | 101 | /* |
babab622 ML |
102 | * Waiting for a event will return a timeout after 2 to 3 seconds in order |
103 | * to not block the application. | |
bafd4890 | 104 | */ |
babab622 | 105 | static int rigol_ds_event_wait(const struct sr_dev_inst *sdi, char status1, char status2) |
bafd4890 | 106 | { |
334fbc2a | 107 | char *buf; |
bafd4890 ML |
108 | struct dev_context *devc; |
109 | time_t start; | |
110 | ||
111 | if (!(devc = sdi->priv)) | |
112 | return SR_ERR; | |
113 | ||
114 | start = time(NULL); | |
115 | ||
116 | /* | |
117 | * Trigger status may return: | |
babab622 ML |
118 | * "TD" or "T'D" - triggered |
119 | * "AUTO" - autotriggered | |
120 | * "RUN" - running | |
121 | * "WAIT" - waiting for trigger | |
122 | * "STOP" - stopped | |
bafd4890 ML |
123 | */ |
124 | ||
babab622 | 125 | if (devc->wait_status == 1) { |
bafd4890 ML |
126 | do { |
127 | if (time(NULL) - start >= 3) { | |
128 | sr_dbg("Timeout waiting for trigger"); | |
129 | return SR_ERR_TIMEOUT; | |
130 | } | |
131 | ||
334fbc2a | 132 | if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK) |
bafd4890 | 133 | return SR_ERR; |
babab622 | 134 | } while (buf[0] == status1 || buf[0] == status2); |
bafd4890 | 135 | |
babab622 | 136 | devc->wait_status = 2; |
bafd4890 | 137 | } |
babab622 | 138 | if (devc->wait_status == 2) { |
bafd4890 ML |
139 | do { |
140 | if (time(NULL) - start >= 3) { | |
141 | sr_dbg("Timeout waiting for trigger"); | |
142 | return SR_ERR_TIMEOUT; | |
143 | } | |
144 | ||
334fbc2a | 145 | if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK) |
bafd4890 | 146 | return SR_ERR; |
babab622 | 147 | } while (buf[0] != status1 && buf[0] != status2); |
bafd4890 | 148 | |
babab622 | 149 | rigol_ds_set_wait_event(devc, WAIT_NONE); |
bafd4890 ML |
150 | } |
151 | ||
152 | return SR_OK; | |
153 | } | |
154 | ||
155 | /* | |
babab622 ML |
156 | * For live capture we need to wait for a new trigger event to ensure that |
157 | * sample data is not returned twice. | |
bafd4890 ML |
158 | * |
159 | * Unfortunately this will never really work because for sufficiently fast | |
babab622 | 160 | * timebases and trigger rates it just can't catch the status changes. |
bafd4890 ML |
161 | * |
162 | * What would be needed is a trigger event register with autoreset like the | |
163 | * Agilents have. The Rigols don't seem to have anything like this. | |
164 | * | |
165 | * The workaround is to only wait for the trigger when the timebase is slow | |
166 | * enough. Of course this means that for faster timebases sample data can be | |
babab622 ML |
167 | * returned multiple times, this effect is mitigated somewhat by sleeping |
168 | * for about one sweep time in that case. | |
bafd4890 | 169 | */ |
babab622 | 170 | static int rigol_ds_trigger_wait(const struct sr_dev_inst *sdi) |
bafd4890 ML |
171 | { |
172 | struct dev_context *devc; | |
babab622 | 173 | long s; |
bafd4890 ML |
174 | |
175 | if (!(devc = sdi->priv)) | |
176 | return SR_ERR; | |
177 | ||
babab622 ML |
178 | /* |
179 | * If timebase < 50 msecs/DIV just sleep about one sweep time except | |
180 | * for really fast sweeps. | |
181 | */ | |
c2b394d5 | 182 | if (devc->timebase < 0.0499) { |
babab622 ML |
183 | if (devc->timebase > 0.99e-6) { |
184 | /* | |
185 | * Timebase * num hor. divs * 85(%) * 1e6(usecs) / 100 | |
186 | * -> 85 percent of sweep time | |
187 | */ | |
569d4dbd | 188 | s = (devc->timebase * devc->model->series->num_horizontal_divs |
babab622 ML |
189 | * 85e6) / 100L; |
190 | sr_spew("Sleeping for %ld usecs instead of trigger-wait", s); | |
191 | g_usleep(s); | |
192 | } | |
193 | rigol_ds_set_wait_event(devc, WAIT_NONE); | |
194 | return SR_OK; | |
195 | } else { | |
196 | return rigol_ds_event_wait(sdi, 'T', 'A'); | |
197 | } | |
198 | } | |
bafd4890 | 199 | |
babab622 ML |
200 | /* Wait for scope to got to "Stop" in single shot mode */ |
201 | static int rigol_ds_stop_wait(const struct sr_dev_inst *sdi) | |
202 | { | |
203 | return rigol_ds_event_wait(sdi, 'S', 'S'); | |
204 | } | |
205 | ||
206 | /* Check that a single shot acquisition actually succeeded on the DS2000 */ | |
207 | static int rigol_ds_check_stop(const struct sr_dev_inst *sdi) | |
208 | { | |
209 | struct dev_context *devc; | |
ba7dd8bb | 210 | struct sr_channel *ch; |
babab622 ML |
211 | int tmp; |
212 | ||
213 | if (!(devc = sdi->priv)) | |
bafd4890 | 214 | return SR_ERR; |
babab622 | 215 | |
ba7dd8bb | 216 | ch = devc->channel_entry->data; |
821fbcad | 217 | |
702f42e8 | 218 | if (devc->model->series->protocol != PROTOCOL_V3) |
e086b750 ML |
219 | return SR_OK; |
220 | ||
38354d9d | 221 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", |
ba7dd8bb | 222 | ch->index + 1) != SR_OK) |
babab622 ML |
223 | return SR_ERR; |
224 | /* Check that the number of samples will be accepted */ | |
38354d9d | 225 | if (rigol_ds_config_set(sdi, ":WAV:POIN %d", devc->analog_frame_size) != SR_OK) |
babab622 | 226 | return SR_ERR; |
334fbc2a | 227 | if (sr_scpi_get_int(sdi->conn, "*ESR?", &tmp) != SR_OK) |
bafd4890 | 228 | return SR_ERR; |
babab622 ML |
229 | /* |
230 | * If we get an "Execution error" the scope went from "Single" to | |
231 | * "Stop" without actually triggering. There is no waveform | |
232 | * displayed and trying to download one will fail - the scope thinks | |
233 | * it has 1400 samples (like display memory) and the driver thinks | |
234 | * it has a different number of samples. | |
235 | * | |
236 | * In that case just try to capture something again. Might still | |
237 | * fail in interesting ways. | |
238 | * | |
239 | * Ain't firmware fun? | |
240 | */ | |
241 | if (tmp & 0x10) { | |
242 | sr_warn("Single shot acquisition failed, retrying..."); | |
243 | /* Sleep a bit, otherwise the single shot will often fail */ | |
1a46cc62 | 244 | g_usleep(500 * 1000); |
38354d9d | 245 | rigol_ds_config_set(sdi, ":SING"); |
babab622 | 246 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
bafd4890 | 247 | return SR_ERR; |
babab622 | 248 | } |
bafd4890 | 249 | |
babab622 ML |
250 | return SR_OK; |
251 | } | |
bafd4890 | 252 | |
babab622 ML |
253 | /* Wait for enough data becoming available in scope output buffer */ |
254 | static int rigol_ds_block_wait(const struct sr_dev_inst *sdi) | |
255 | { | |
334fbc2a | 256 | char *buf; |
babab622 ML |
257 | struct dev_context *devc; |
258 | time_t start; | |
259 | int len; | |
260 | ||
261 | if (!(devc = sdi->priv)) | |
262 | return SR_ERR; | |
263 | ||
702f42e8 | 264 | if (devc->model->series->protocol == PROTOCOL_V3) { |
babab622 | 265 | |
4472867a ML |
266 | start = time(NULL); |
267 | ||
268 | do { | |
269 | if (time(NULL) - start >= 3) { | |
270 | sr_dbg("Timeout waiting for data block"); | |
271 | return SR_ERR_TIMEOUT; | |
272 | } | |
babab622 | 273 | |
4472867a ML |
274 | /* |
275 | * The scope copies data really slowly from sample | |
276 | * memory to its output buffer, so try not to bother | |
277 | * it too much with SCPI requests but don't wait too | |
278 | * long for short sample frame sizes. | |
279 | */ | |
1a46cc62 | 280 | g_usleep(devc->analog_frame_size < (15 * 1000) ? (100 * 1000) : (1000 * 1000)); |
4472867a ML |
281 | |
282 | /* "READ,nnnn" (still working) or "IDLE,nnnn" (finished) */ | |
283 | if (sr_scpi_get_string(sdi->conn, ":WAV:STAT?", &buf) != SR_OK) | |
284 | return SR_ERR; | |
285 | ||
286 | if (parse_int(buf + 5, &len) != SR_OK) | |
287 | return SR_ERR; | |
1a46cc62 | 288 | } while (buf[0] == 'R' && len < (1000 * 1000)); |
4472867a | 289 | } |
babab622 ML |
290 | |
291 | rigol_ds_set_wait_event(devc, WAIT_NONE); | |
292 | ||
293 | return SR_OK; | |
294 | } | |
295 | ||
38354d9d ML |
296 | /* Send a configuration setting. */ |
297 | SR_PRIV int rigol_ds_config_set(const struct sr_dev_inst *sdi, const char *format, ...) | |
298 | { | |
299 | struct dev_context *devc = sdi->priv; | |
300 | va_list args; | |
301 | int ret; | |
302 | ||
303 | va_start(args, format); | |
304 | ret = sr_scpi_send_variadic(sdi->conn, format, args); | |
305 | va_end(args); | |
306 | ||
307 | if (ret != SR_OK) | |
308 | return SR_ERR; | |
309 | ||
569d4dbd | 310 | if (devc->model->series->protocol == PROTOCOL_V2) { |
38354d9d ML |
311 | /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */ |
312 | sr_spew("delay %dms", 100); | |
1a46cc62 | 313 | g_usleep(100 * 1000); |
38354d9d ML |
314 | return SR_OK; |
315 | } else { | |
316 | return sr_scpi_get_opc(sdi->conn); | |
317 | } | |
318 | } | |
319 | ||
babab622 ML |
320 | /* Start capturing a new frameset */ |
321 | SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi) | |
322 | { | |
323 | struct dev_context *devc; | |
e086b750 | 324 | gchar *trig_mode; |
702f42e8 | 325 | unsigned int num_channels, i, j; |
babab622 ML |
326 | |
327 | if (!(devc = sdi->priv)) | |
328 | return SR_ERR; | |
329 | ||
330 | sr_dbg("Starting data capture for frameset %lu of %lu", | |
331 | devc->num_frames + 1, devc->limit_frames); | |
332 | ||
569d4dbd ML |
333 | switch (devc->model->series->protocol) { |
334 | case PROTOCOL_V1: | |
335 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); | |
336 | break; | |
337 | case PROTOCOL_V2: | |
338 | if (devc->data_source == DATA_SOURCE_LIVE) { | |
339 | if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE NORMAL") != SR_OK) | |
e086b750 | 340 | return SR_ERR; |
569d4dbd | 341 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); |
e086b750 | 342 | } else { |
e086b750 ML |
343 | if (rigol_ds_config_set(sdi, ":STOP") != SR_OK) |
344 | return SR_ERR; | |
345 | if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE RAW") != SR_OK) | |
346 | return SR_ERR; | |
347 | if (sr_scpi_get_string(sdi->conn, ":TRIG:MODE?", &trig_mode) != SR_OK) | |
348 | return SR_ERR; | |
349 | if (rigol_ds_config_set(sdi, ":TRIG:%s:SWE SING", trig_mode) != SR_OK) | |
350 | return SR_ERR; | |
351 | if (rigol_ds_config_set(sdi, ":RUN") != SR_OK) | |
352 | return SR_ERR; | |
569d4dbd ML |
353 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
354 | } | |
355 | break; | |
356 | case PROTOCOL_V3: | |
702f42e8 | 357 | case PROTOCOL_V4: |
569d4dbd ML |
358 | if (rigol_ds_config_set(sdi, ":WAV:FORM BYTE") != SR_OK) |
359 | return SR_ERR; | |
360 | if (devc->data_source == DATA_SOURCE_LIVE) { | |
361 | if (rigol_ds_config_set(sdi, ":WAV:MODE NORM") != SR_OK) | |
362 | return SR_ERR; | |
702f42e8 ML |
363 | devc->analog_frame_size = devc->model->series->live_samples; |
364 | devc->digital_frame_size = devc->model->series->live_samples; | |
569d4dbd | 365 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); |
e086b750 | 366 | } else { |
702f42e8 ML |
367 | if (devc->model->series->protocol == PROTOCOL_V3) { |
368 | if (rigol_ds_config_set(sdi, ":WAV:MODE RAW") != SR_OK) | |
369 | return SR_ERR; | |
370 | } else if (devc->model->series->protocol == PROTOCOL_V4) { | |
371 | num_channels = 0; | |
372 | ||
373 | /* Channels 3 and 4 are multiplexed with D0-7 and D8-15 */ | |
374 | for (i = 0; i < devc->model->analog_channels; i++) { | |
375 | if (devc->analog_channels[i]) { | |
376 | num_channels++; | |
377 | } else if (i >= 2 && devc->model->has_digital) { | |
378 | for (j = 0; j < 8; j++) { | |
379 | if (devc->digital_channels[8 * (i - 2) + j]) { | |
380 | num_channels++; | |
381 | break; | |
382 | } | |
383 | } | |
384 | } | |
385 | } | |
386 | ||
387 | devc->analog_frame_size = devc->digital_frame_size = | |
388 | num_channels == 1 ? | |
389 | devc->model->series->buffer_samples : | |
390 | num_channels == 2 ? | |
391 | devc->model->series->buffer_samples / 2 : | |
392 | devc->model->series->buffer_samples / 4; | |
393 | } | |
394 | ||
e086b750 ML |
395 | if (rigol_ds_config_set(sdi, ":SING") != SR_OK) |
396 | return SR_ERR; | |
569d4dbd | 397 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
e086b750 | 398 | } |
569d4dbd | 399 | break; |
bafd4890 ML |
400 | } |
401 | ||
402 | return SR_OK; | |
403 | } | |
404 | ||
babab622 ML |
405 | /* Start reading data from the current channel */ |
406 | SR_PRIV int rigol_ds_channel_start(const struct sr_dev_inst *sdi) | |
407 | { | |
408 | struct dev_context *devc; | |
ba7dd8bb | 409 | struct sr_channel *ch; |
babab622 ML |
410 | |
411 | if (!(devc = sdi->priv)) | |
412 | return SR_ERR; | |
413 | ||
ba7dd8bb | 414 | ch = devc->channel_entry->data; |
821fbcad | 415 | |
ba7dd8bb | 416 | sr_dbg("Starting reading data from channel %d", ch->index + 1); |
babab622 | 417 | |
2ea67fc9 | 418 | switch (devc->model->series->protocol) { |
702f42e8 ML |
419 | case PROTOCOL_V1: |
420 | case PROTOCOL_V2: | |
3f239f08 | 421 | if (ch->type == SR_CHANNEL_LOGIC) { |
677f85d0 ML |
422 | if (sr_scpi_send(sdi->conn, ":WAV:DATA? DIG") != SR_OK) |
423 | return SR_ERR; | |
424 | } else { | |
821fbcad | 425 | if (sr_scpi_send(sdi->conn, ":WAV:DATA? CHAN%d", |
ba7dd8bb | 426 | ch->index + 1) != SR_OK) |
677f85d0 ML |
427 | return SR_ERR; |
428 | } | |
e086b750 | 429 | rigol_ds_set_wait_event(devc, WAIT_NONE); |
702f42e8 ML |
430 | break; |
431 | case PROTOCOL_V3: | |
38354d9d | 432 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", |
ba7dd8bb | 433 | ch->index + 1) != SR_OK) |
babab622 | 434 | return SR_ERR; |
677f85d0 | 435 | if (devc->data_source != DATA_SOURCE_LIVE) { |
38354d9d | 436 | if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK) |
677f85d0 | 437 | return SR_ERR; |
38354d9d | 438 | if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK) |
677f85d0 | 439 | return SR_ERR; |
aff00e40 | 440 | } |
702f42e8 ML |
441 | break; |
442 | case PROTOCOL_V4: | |
443 | if (ch->type == SR_CHANNEL_ANALOG) { | |
444 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", | |
445 | ch->index + 1) != SR_OK) | |
446 | return SR_ERR; | |
447 | } else { | |
448 | if (rigol_ds_config_set(sdi, ":WAV:SOUR D%d", | |
449 | ch->index) != SR_OK) | |
450 | return SR_ERR; | |
451 | } | |
452 | ||
453 | if (rigol_ds_config_set(sdi, | |
454 | devc->data_source == DATA_SOURCE_LIVE ? | |
455 | ":WAV:MODE NORM" :":WAV:MODE RAW") != SR_OK) | |
456 | return SR_ERR; | |
457 | break; | |
458 | } | |
459 | ||
460 | if (devc->model->series->protocol >= PROTOCOL_V3 && | |
461 | ch->type == SR_CHANNEL_ANALOG) { | |
462 | /* Vertical reference. */ | |
463 | if (sr_scpi_get_int(sdi->conn, ":WAV:YREF?", | |
464 | &devc->vert_reference[ch->index]) != SR_OK) | |
465 | return SR_ERR; | |
677f85d0 | 466 | } |
babab622 | 467 | |
aff00e40 ML |
468 | rigol_ds_set_wait_event(devc, WAIT_BLOCK); |
469 | ||
f76c24f6 | 470 | devc->num_channel_bytes = 0; |
aff00e40 | 471 | devc->num_header_bytes = 0; |
babab622 ML |
472 | devc->num_block_bytes = 0; |
473 | ||
474 | return SR_OK; | |
475 | } | |
476 | ||
477 | /* Read the header of a data block */ | |
aff00e40 | 478 | static int rigol_ds_read_header(struct sr_dev_inst *sdi) |
bafd4890 | 479 | { |
aff00e40 ML |
480 | struct sr_scpi_dev_inst *scpi = sdi->conn; |
481 | struct dev_context *devc = sdi->priv; | |
482 | char *buf = (char *) devc->buffer; | |
fe0d9caa ML |
483 | size_t header_length; |
484 | int ret; | |
aff00e40 ML |
485 | |
486 | /* Try to read the hashsign and length digit. */ | |
487 | if (devc->num_header_bytes < 2) { | |
fe0d9caa | 488 | ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes, |
aff00e40 | 489 | 2 - devc->num_header_bytes); |
fe0d9caa | 490 | if (ret < 0) { |
aff00e40 ML |
491 | sr_err("Read error while reading data header."); |
492 | return SR_ERR; | |
493 | } | |
fe0d9caa | 494 | devc->num_header_bytes += ret; |
bafd4890 | 495 | } |
aff00e40 ML |
496 | |
497 | if (devc->num_header_bytes < 2) | |
498 | return 0; | |
499 | ||
500 | if (buf[0] != '#' || !isdigit(buf[1]) || buf[1] == '0') { | |
501 | sr_err("Received invalid data block header '%c%c'.", buf[0], buf[1]); | |
502 | return SR_ERR; | |
bafd4890 | 503 | } |
bafd4890 | 504 | |
fe0d9caa | 505 | header_length = 2 + buf[1] - '0'; |
aff00e40 ML |
506 | |
507 | /* Try to read the length. */ | |
fe0d9caa ML |
508 | if (devc->num_header_bytes < header_length) { |
509 | ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes, | |
510 | header_length - devc->num_header_bytes); | |
511 | if (ret < 0) { | |
aff00e40 ML |
512 | sr_err("Read error while reading data header."); |
513 | return SR_ERR; | |
514 | } | |
fe0d9caa | 515 | devc->num_header_bytes += ret; |
bafd4890 | 516 | } |
aff00e40 | 517 | |
fe0d9caa | 518 | if (devc->num_header_bytes < header_length) |
aff00e40 ML |
519 | return 0; |
520 | ||
521 | /* Read the data length. */ | |
fe0d9caa | 522 | buf[header_length] = '\0'; |
aff00e40 | 523 | |
fe0d9caa | 524 | if (parse_int(buf + 2, &ret) != SR_OK) { |
aff00e40 | 525 | sr_err("Received invalid data block length '%s'.", buf + 2); |
bafd4890 ML |
526 | return -1; |
527 | } | |
528 | ||
fe0d9caa | 529 | sr_dbg("Received data block header: '%s' -> block length %d", buf, ret); |
bafd4890 | 530 | |
fe0d9caa | 531 | return ret; |
bafd4890 ML |
532 | } |
533 | ||
3086efdd | 534 | SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data) |
f4816ac6 | 535 | { |
e0b7d23c | 536 | struct sr_dev_inst *sdi; |
ae1bc1cc | 537 | struct sr_scpi_dev_inst *scpi; |
f4816ac6 | 538 | struct dev_context *devc; |
e0b7d23c ML |
539 | struct sr_datafeed_packet packet; |
540 | struct sr_datafeed_analog analog; | |
6bb192bc | 541 | struct sr_datafeed_logic logic; |
254dd102 | 542 | double vdiv, offset; |
f80a0bf2 | 543 | int len, i, vref; |
ba7dd8bb | 544 | struct sr_channel *ch; |
bac11aeb | 545 | gsize expected_data_bytes; |
f4816ac6 | 546 | |
decfe89d | 547 | (void)fd; |
9bd4c956 | 548 | |
f4816ac6 ML |
549 | if (!(sdi = cb_data)) |
550 | return TRUE; | |
551 | ||
552 | if (!(devc = sdi->priv)) | |
553 | return TRUE; | |
554 | ||
ae1bc1cc | 555 | scpi = sdi->conn; |
9bd4c956 | 556 | |
d5876cfb | 557 | if (revents == G_IO_IN || revents == 0) { |
0c5f2abc | 558 | switch (devc->wait_event) { |
e086b750 ML |
559 | case WAIT_NONE: |
560 | break; | |
561 | case WAIT_TRIGGER: | |
562 | if (rigol_ds_trigger_wait(sdi) != SR_OK) | |
bafd4890 | 563 | return TRUE; |
e086b750 ML |
564 | if (rigol_ds_channel_start(sdi) != SR_OK) |
565 | return TRUE; | |
3918fbb0 | 566 | return TRUE; |
e086b750 ML |
567 | case WAIT_BLOCK: |
568 | if (rigol_ds_block_wait(sdi) != SR_OK) | |
569 | return TRUE; | |
570 | break; | |
571 | case WAIT_STOP: | |
572 | if (rigol_ds_stop_wait(sdi) != SR_OK) | |
573 | return TRUE; | |
574 | if (rigol_ds_check_stop(sdi) != SR_OK) | |
575 | return TRUE; | |
576 | if (rigol_ds_channel_start(sdi) != SR_OK) | |
577 | return TRUE; | |
578 | return TRUE; | |
579 | default: | |
580 | sr_err("BUG: Unknown event target encountered"); | |
f44f7e61 | 581 | break; |
f80a0bf2 ML |
582 | } |
583 | ||
ba7dd8bb | 584 | ch = devc->channel_entry->data; |
bac11aeb | 585 | |
3f239f08 | 586 | expected_data_bytes = ch->type == SR_CHANNEL_ANALOG ? |
bac11aeb | 587 | devc->analog_frame_size : devc->digital_frame_size; |
f76c24f6 | 588 | |
e086b750 | 589 | if (devc->num_block_bytes == 0) { |
702f42e8 ML |
590 | if (devc->model->series->protocol >= PROTOCOL_V4) { |
591 | if (sr_scpi_send(sdi->conn, ":WAV:START %d", | |
592 | devc->num_channel_bytes + 1) != SR_OK) | |
593 | return TRUE; | |
594 | if (sr_scpi_send(sdi->conn, ":WAV:STOP %d", | |
595 | MIN(devc->num_channel_bytes + ACQ_BLOCK_SIZE, | |
596 | devc->analog_frame_size)) != SR_OK) | |
597 | return TRUE; | |
598 | } | |
599 | ||
569d4dbd | 600 | if (devc->model->series->protocol >= PROTOCOL_V3) |
a53278de AJ |
601 | if (sr_scpi_send(sdi->conn, ":WAV:DATA?") != SR_OK) |
602 | return TRUE; | |
bac11aeb | 603 | |
05c644ea ML |
604 | if (sr_scpi_read_begin(scpi) != SR_OK) |
605 | return TRUE; | |
bac11aeb | 606 | |
569d4dbd | 607 | if (devc->format == FORMAT_IEEE488_2) { |
babab622 | 608 | sr_dbg("New block header expected"); |
aff00e40 ML |
609 | len = rigol_ds_read_header(sdi); |
610 | if (len == 0) | |
611 | /* Still reading the header. */ | |
612 | return TRUE; | |
613 | if (len == -1) { | |
614 | sr_err("Read error, aborting capture."); | |
615 | packet.type = SR_DF_FRAME_END; | |
616 | sr_session_send(cb_data, &packet); | |
617 | sdi->driver->dev_acquisition_stop(sdi, cb_data); | |
babab622 | 618 | return TRUE; |
aff00e40 | 619 | } |
babab622 ML |
620 | /* At slow timebases in live capture the DS2072 |
621 | * sometimes returns "short" data blocks, with | |
622 | * apparently no way to get the rest of the data. | |
623 | * Discard these, the complete data block will | |
624 | * appear eventually. | |
625 | */ | |
626 | if (devc->data_source == DATA_SOURCE_LIVE | |
bac11aeb | 627 | && (unsigned)len < expected_data_bytes) { |
babab622 | 628 | sr_dbg("Discarding short data block"); |
05c644ea | 629 | sr_scpi_read_data(scpi, (char *)devc->buffer, len + 1); |
babab622 ML |
630 | return TRUE; |
631 | } | |
632 | devc->num_block_bytes = len; | |
f80a0bf2 | 633 | } else { |
bac11aeb | 634 | devc->num_block_bytes = expected_data_bytes; |
f80a0bf2 ML |
635 | } |
636 | devc->num_block_read = 0; | |
bafd4890 | 637 | } |
f80a0bf2 ML |
638 | |
639 | len = devc->num_block_bytes - devc->num_block_read; | |
ae3a1913 ML |
640 | if (len > ACQ_BUFFER_SIZE) |
641 | len = ACQ_BUFFER_SIZE; | |
642 | sr_dbg("Requesting read of %d bytes", len); | |
643 | ||
644 | len = sr_scpi_read_data(scpi, (char *)devc->buffer, len); | |
f80a0bf2 | 645 | |
7d63347e ML |
646 | if (len == -1) { |
647 | sr_err("Read error, aborting capture."); | |
648 | packet.type = SR_DF_FRAME_END; | |
649 | sr_session_send(cb_data, &packet); | |
650 | sdi->driver->dev_acquisition_stop(sdi, cb_data); | |
651 | return TRUE; | |
652 | } | |
ae3a1913 ML |
653 | |
654 | sr_dbg("Received %d bytes.", len); | |
75d8a4e5 | 655 | |
48460c6f ML |
656 | devc->num_block_read += len; |
657 | ||
3f239f08 | 658 | if (ch->type == SR_CHANNEL_ANALOG) { |
ba7dd8bb UH |
659 | vref = devc->vert_reference[ch->index]; |
660 | vdiv = devc->vdiv[ch->index] / 25.6; | |
661 | offset = devc->vert_offset[ch->index]; | |
569d4dbd | 662 | if (devc->model->series->protocol >= PROTOCOL_V3) |
bafd4890 | 663 | for (i = 0; i < len; i++) |
babab622 | 664 | devc->data[i] = ((int)devc->buffer[i] - vref) * vdiv - offset; |
bafd4890 ML |
665 | else |
666 | for (i = 0; i < len; i++) | |
babab622 | 667 | devc->data[i] = (128 - devc->buffer[i]) * vdiv - offset; |
ba7dd8bb | 668 | analog.channels = g_slist_append(NULL, ch); |
6bb192bc | 669 | analog.num_samples = len; |
babab622 | 670 | analog.data = devc->data; |
6bb192bc ML |
671 | analog.mq = SR_MQ_VOLTAGE; |
672 | analog.unit = SR_UNIT_VOLT; | |
673 | analog.mqflags = 0; | |
674 | packet.type = SR_DF_ANALOG; | |
675 | packet.payload = &analog; | |
676 | sr_session_send(cb_data, &packet); | |
ba7dd8bb | 677 | g_slist_free(analog.channels); |
6bb192bc | 678 | } else { |
470140fc | 679 | logic.length = len; |
702f42e8 ML |
680 | // TODO: For the MSO1000Z series, we need a way to express that |
681 | // this data is in fact just for a single channel, with the valid | |
682 | // data for that channel in the LSB of each byte. | |
683 | logic.unitsize = devc->model->series->protocol == PROTOCOL_V4 ? 1 : 2; | |
470140fc | 684 | logic.data = devc->buffer; |
6bb192bc ML |
685 | packet.type = SR_DF_LOGIC; |
686 | packet.payload = &logic; | |
687 | sr_session_send(cb_data, &packet); | |
48460c6f | 688 | } |
6bb192bc | 689 | |
48460c6f ML |
690 | if (devc->num_block_read == devc->num_block_bytes) { |
691 | sr_dbg("Block has been completed"); | |
2b399703 | 692 | if (devc->model->series->protocol >= PROTOCOL_V3) { |
470140fc | 693 | /* Discard the terminating linefeed */ |
05c644ea | 694 | sr_scpi_read_data(scpi, (char *)devc->buffer, 1); |
2b399703 ML |
695 | } |
696 | if (devc->format == FORMAT_IEEE488_2) { | |
470140fc | 697 | /* Prepare for possible next block */ |
aff00e40 | 698 | devc->num_header_bytes = 0; |
48460c6f ML |
699 | devc->num_block_bytes = 0; |
700 | if (devc->data_source != DATA_SOURCE_LIVE) | |
701 | rigol_ds_set_wait_event(devc, WAIT_BLOCK); | |
702 | } | |
3ed7a40c ML |
703 | if (!sr_scpi_read_complete(scpi)) { |
704 | sr_err("Read should have been completed"); | |
7d63347e ML |
705 | packet.type = SR_DF_FRAME_END; |
706 | sr_session_send(cb_data, &packet); | |
3ed7a40c ML |
707 | sdi->driver->dev_acquisition_stop(sdi, cb_data); |
708 | return TRUE; | |
709 | } | |
48460c6f ML |
710 | devc->num_block_read = 0; |
711 | } else { | |
712 | sr_dbg("%d of %d block bytes read", devc->num_block_read, devc->num_block_bytes); | |
ee7e9bee | 713 | } |
75d8a4e5 | 714 | |
f76c24f6 | 715 | devc->num_channel_bytes += len; |
48460c6f | 716 | |
f76c24f6 ML |
717 | if (devc->num_channel_bytes < expected_data_bytes) |
718 | /* Don't have the full data for this channel yet, re-run. */ | |
48460c6f ML |
719 | return TRUE; |
720 | ||
f76c24f6 | 721 | /* End of data for this channel. */ |
702f42e8 | 722 | if (devc->model->series->protocol == PROTOCOL_V3) { |
babab622 ML |
723 | /* Signal end of data download to scope */ |
724 | if (devc->data_source != DATA_SOURCE_LIVE) | |
725 | /* | |
726 | * This causes a query error, without it switching | |
727 | * to the next channel causes an error. Fun with | |
728 | * firmware... | |
729 | */ | |
38354d9d | 730 | rigol_ds_config_set(sdi, ":WAV:END"); |
babab622 | 731 | } |
254dd102 | 732 | |
702f42e8 ML |
733 | if (devc->channel_entry->next) { |
734 | /* We got the frame for this channel, now get the next channel. */ | |
821fbcad | 735 | devc->channel_entry = devc->channel_entry->next; |
677f85d0 | 736 | rigol_ds_channel_start(sdi); |
254dd102 | 737 | } else { |
702f42e8 ML |
738 | /* Done with this frame. */ |
739 | packet.type = SR_DF_FRAME_END; | |
740 | sr_session_send(cb_data, &packet); | |
f76c24f6 | 741 | |
702f42e8 ML |
742 | if (++devc->num_frames == devc->limit_frames) { |
743 | /* Last frame, stop capture. */ | |
744 | sdi->driver->dev_acquisition_stop(sdi, cb_data); | |
745 | } else { | |
746 | /* Get the next frame, starting with the first channel. */ | |
747 | devc->channel_entry = devc->enabled_channels; | |
f76c24f6 | 748 | |
702f42e8 | 749 | rigol_ds_capture_start(sdi); |
f76c24f6 | 750 | |
702f42e8 ML |
751 | /* Start of next frame. */ |
752 | packet.type = SR_DF_FRAME_BEGIN; | |
753 | sr_session_send(cb_data, &packet); | |
254dd102 | 754 | } |
75d8a4e5 | 755 | } |
f4816ac6 ML |
756 | } |
757 | ||
758 | return TRUE; | |
759 | } | |
e0b7d23c | 760 | |
3086efdd | 761 | SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi) |
254dd102 BV |
762 | { |
763 | struct dev_context *devc; | |
98bfc474 | 764 | char *cmd; |
821fbcad ML |
765 | unsigned int i; |
766 | int res; | |
254dd102 BV |
767 | |
768 | devc = sdi->priv; | |
769 | ||
6bb192bc | 770 | /* Analog channel state. */ |
821fbcad ML |
771 | for (i = 0; i < devc->model->analog_channels; i++) { |
772 | cmd = g_strdup_printf(":CHAN%d:DISP?", i + 1); | |
98bfc474 | 773 | res = sr_scpi_get_bool(sdi->conn, cmd, &devc->analog_channels[i]); |
821fbcad ML |
774 | g_free(cmd); |
775 | if (res != SR_OK) | |
776 | return SR_ERR; | |
821fbcad ML |
777 | } |
778 | sr_dbg("Current analog channel state:"); | |
779 | for (i = 0; i < devc->model->analog_channels; i++) | |
780 | sr_dbg("CH%d %s", i + 1, devc->analog_channels[i] ? "on" : "off"); | |
6bb192bc ML |
781 | |
782 | /* Digital channel state. */ | |
bafd4890 | 783 | if (devc->model->has_digital) { |
702f42e8 ML |
784 | if (sr_scpi_get_bool(sdi->conn, |
785 | devc->model->series->protocol >= PROTOCOL_V4 ? | |
786 | ":LA:STAT?" : ":LA:DISP?", | |
98bfc474 | 787 | &devc->la_enabled) != SR_OK) |
04e8e01e | 788 | return SR_ERR; |
04e8e01e ML |
789 | sr_dbg("Logic analyzer %s, current digital channel state:", |
790 | devc->la_enabled ? "enabled" : "disabled"); | |
effb9dd1 | 791 | for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) { |
702f42e8 ML |
792 | cmd = g_strdup_printf( |
793 | devc->model->series->protocol >= PROTOCOL_V4 ? | |
794 | ":LA:DIG%d:DISP?" : ":DIG%d:TURN?", i); | |
98bfc474 | 795 | res = sr_scpi_get_bool(sdi->conn, cmd, &devc->digital_channels[i]); |
6bb192bc ML |
796 | g_free(cmd); |
797 | if (res != SR_OK) | |
798 | return SR_ERR; | |
bfaf112b | 799 | sr_dbg("D%d: %s", i, devc->digital_channels[i] ? "on" : "off"); |
6bb192bc ML |
800 | } |
801 | } | |
254dd102 BV |
802 | |
803 | /* Timebase. */ | |
334fbc2a | 804 | if (sr_scpi_get_float(sdi->conn, ":TIM:SCAL?", &devc->timebase) != SR_OK) |
254dd102 | 805 | return SR_ERR; |
bafd4890 | 806 | sr_dbg("Current timebase %g", devc->timebase); |
254dd102 BV |
807 | |
808 | /* Vertical gain. */ | |
821fbcad ML |
809 | for (i = 0; i < devc->model->analog_channels; i++) { |
810 | cmd = g_strdup_printf(":CHAN%d:SCAL?", i + 1); | |
334fbc2a | 811 | res = sr_scpi_get_float(sdi->conn, cmd, &devc->vdiv[i]); |
821fbcad ML |
812 | g_free(cmd); |
813 | if (res != SR_OK) | |
814 | return SR_ERR; | |
815 | } | |
816 | sr_dbg("Current vertical gain:"); | |
817 | for (i = 0; i < devc->model->analog_channels; i++) | |
818 | sr_dbg("CH%d %g", i + 1, devc->vdiv[i]); | |
bafd4890 | 819 | |
254dd102 | 820 | /* Vertical offset. */ |
821fbcad ML |
821 | for (i = 0; i < devc->model->analog_channels; i++) { |
822 | cmd = g_strdup_printf(":CHAN%d:OFFS?", i + 1); | |
334fbc2a | 823 | res = sr_scpi_get_float(sdi->conn, cmd, &devc->vert_offset[i]); |
821fbcad ML |
824 | g_free(cmd); |
825 | if (res != SR_OK) | |
826 | return SR_ERR; | |
827 | } | |
828 | sr_dbg("Current vertical offset:"); | |
829 | for (i = 0; i < devc->model->analog_channels; i++) | |
830 | sr_dbg("CH%d %g", i + 1, devc->vert_offset[i]); | |
254dd102 BV |
831 | |
832 | /* Coupling. */ | |
821fbcad ML |
833 | for (i = 0; i < devc->model->analog_channels; i++) { |
834 | cmd = g_strdup_printf(":CHAN%d:COUP?", i + 1); | |
334fbc2a | 835 | res = sr_scpi_get_string(sdi->conn, cmd, &devc->coupling[i]); |
821fbcad ML |
836 | g_free(cmd); |
837 | if (res != SR_OK) | |
838 | return SR_ERR; | |
839 | } | |
840 | sr_dbg("Current coupling:"); | |
841 | for (i = 0; i < devc->model->analog_channels; i++) | |
842 | sr_dbg("CH%d %s", i + 1, devc->coupling[i]); | |
254dd102 BV |
843 | |
844 | /* Trigger source. */ | |
334fbc2a | 845 | if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SOUR?", &devc->trigger_source) != SR_OK) |
254dd102 BV |
846 | return SR_ERR; |
847 | sr_dbg("Current trigger source %s", devc->trigger_source); | |
848 | ||
849 | /* Horizontal trigger position. */ | |
334fbc2a | 850 | if (sr_scpi_get_float(sdi->conn, ":TIM:OFFS?", &devc->horiz_triggerpos) != SR_OK) |
254dd102 | 851 | return SR_ERR; |
bafd4890 | 852 | sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos); |
254dd102 BV |
853 | |
854 | /* Trigger slope. */ | |
334fbc2a | 855 | if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SLOP?", &devc->trigger_slope) != SR_OK) |
254dd102 BV |
856 | return SR_ERR; |
857 | sr_dbg("Current trigger slope %s", devc->trigger_slope); | |
858 | ||
859 | return SR_OK; | |
860 | } |