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f2cd2deb FS |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de> | |
5 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
6 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
7 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
8 | * | |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <config.h> | |
24 | #include <stdint.h> | |
25 | #include <string.h> | |
26 | #include <glib.h> | |
27 | #include <glib/gstdio.h> | |
28 | #include <stdio.h> | |
29 | #include <errno.h> | |
30 | #include <math.h> | |
3f48ab02 | 31 | #include <inttypes.h> |
f2cd2deb FS |
32 | #include <libsigrok/libsigrok.h> |
33 | #include "libsigrok-internal.h" | |
34 | #include "protocol.h" | |
35 | ||
f2cd2deb | 36 | #define UC_FIRMWARE "kingst-la-%04x.fw" |
9de389b1 KG |
37 | #define FPGA_FW_LA2016 "kingst-la2016-fpga.bitstream" |
38 | #define FPGA_FW_LA2016A "kingst-la2016a1-fpga.bitstream" | |
f2cd2deb FS |
39 | |
40 | #define MAX_SAMPLE_RATE SR_MHZ(200) | |
41 | #define MAX_SAMPLE_DEPTH 10e9 | |
42 | #define MAX_PWM_FREQ SR_MHZ(20) | |
43 | #define PWM_CLOCK SR_MHZ(200) | |
44 | ||
00849545 KG |
45 | /* usb vendor class control requests to the cypress FX2 microcontroller */ |
46 | #define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */ | |
47 | #define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */ | |
48 | #define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */ | |
49 | #define CMD_FPGA_ENABLE 0x10 | |
50 | #define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */ | |
51 | #define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */ | |
52 | #define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */ | |
53 | ||
42f6dd55 KG |
54 | /* |
55 | * fpga spi register addresses for control request CMD_FPGA_SPI: | |
56 | * There are around 60 byte-wide registers within the fpga and | |
57 | * these are the base addresses used for accessing them. | |
58 | * On the spi bus, the msb of the address byte is set for read | |
59 | * and cleared for write, but that is handled by the fx2 mcu | |
60 | * as appropriate. In this driver code just use IN transactions | |
61 | * to read, OUT to write. | |
62 | */ | |
63 | #define REG_RUN 0x00 /* read capture status, write capture start */ | |
64 | #define REG_PWM_EN 0x02 /* user pwm channels on/off */ | |
65 | #define REG_CAPT_MODE 0x03 /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */ | |
66 | #define REG_BULK 0x08 /* write start address and number of bytes for capture data bulk upload */ | |
67 | #define REG_SAMPLING 0x10 /* write capture config, read capture data location in sdram */ | |
68 | #define REG_TRIGGER 0x20 /* write level and edge trigger config */ | |
69 | #define REG_THRESHOLD 0x68 /* write two pwm configs to control input threshold dac */ | |
70 | #define REG_PWM1 0x70 /* write config for user pwm1 */ | |
71 | #define REG_PWM2 0x78 /* write config for user pwm2 */ | |
f2cd2deb FS |
72 | |
73 | static int ctrl_in(const struct sr_dev_inst *sdi, | |
74 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, | |
75 | void *data, uint16_t wLength) | |
76 | { | |
77 | struct sr_usb_dev_inst *usb; | |
78 | int ret; | |
79 | ||
80 | usb = sdi->conn; | |
81 | ||
82 | if ((ret = libusb_control_transfer( | |
83 | usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, | |
84 | bRequest, wValue, wIndex, (unsigned char *)data, wLength, | |
85 | DEFAULT_TIMEOUT_MS)) != wLength) { | |
86 | sr_err("failed to read %d bytes via ctrl-in %d %#x, %d: %s.", | |
87 | wLength, bRequest, wValue, wIndex, | |
88 | libusb_error_name(ret)); | |
89 | return SR_ERR; | |
90 | } | |
91 | ||
92 | return SR_OK; | |
93 | } | |
94 | ||
95 | static int ctrl_out(const struct sr_dev_inst *sdi, | |
96 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, | |
97 | void *data, uint16_t wLength) | |
98 | { | |
99 | struct sr_usb_dev_inst *usb; | |
100 | int ret; | |
101 | ||
102 | usb = sdi->conn; | |
103 | ||
104 | if ((ret = libusb_control_transfer( | |
105 | usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, | |
106 | bRequest, wValue, wIndex, (unsigned char*)data, wLength, | |
107 | DEFAULT_TIMEOUT_MS)) != wLength) { | |
108 | sr_err("failed to write %d bytes via ctrl-out %d %#x, %d: %s.", | |
109 | wLength, bRequest, wValue, wIndex, | |
110 | libusb_error_name(ret)); | |
111 | return SR_ERR; | |
112 | } | |
113 | ||
114 | return SR_OK; | |
115 | } | |
116 | ||
9de389b1 | 117 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bitstream_fname) |
f2cd2deb | 118 | { |
3f48ab02 | 119 | struct dev_context *devc; |
f2cd2deb FS |
120 | struct drv_context *drvc; |
121 | struct sr_usb_dev_inst *usb; | |
122 | struct sr_resource bitstream; | |
c3d40037 HK |
123 | uint8_t buffer[sizeof(uint32_t)]; |
124 | uint8_t *wrptr; | |
f2cd2deb FS |
125 | uint8_t cmd_resp; |
126 | uint8_t block[4096]; | |
3f48ab02 FS |
127 | int len, act_len; |
128 | unsigned int pos; | |
f2cd2deb | 129 | int ret; |
3f48ab02 | 130 | unsigned int zero_pad_to = 0x2c000; |
f2cd2deb | 131 | |
3f48ab02 | 132 | devc = sdi->priv; |
f2cd2deb FS |
133 | drvc = sdi->driver->context; |
134 | usb = sdi->conn; | |
135 | ||
9de389b1 | 136 | sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); |
f2cd2deb | 137 | |
9de389b1 | 138 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, bitstream_fname); |
f2cd2deb | 139 | if (ret != SR_OK) { |
9de389b1 | 140 | sr_err("could not find fpga firmware %s!", bitstream_fname); |
f2cd2deb FS |
141 | return ret; |
142 | } | |
143 | ||
3f48ab02 | 144 | devc->bitstream_size = (uint32_t)bitstream.size; |
c3d40037 HK |
145 | wrptr = buffer; |
146 | write_u32le_inc(&wrptr, devc->bitstream_size); | |
00849545 | 147 | if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) { |
f2cd2deb FS |
148 | sr_err("failed to give upload init command"); |
149 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
150 | return ret; | |
151 | } | |
152 | ||
153 | pos = 0; | |
154 | while (1) { | |
3f48ab02 FS |
155 | if (pos < bitstream.size) { |
156 | len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block)); | |
157 | if (len < 0) { | |
158 | sr_err("failed to read from fpga bitstream!"); | |
159 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
160 | return SR_ERR; | |
161 | } | |
162 | } else { | |
163 | // fill with zero's until zero_pad_to | |
164 | len = zero_pad_to - pos; | |
165 | if ((unsigned)len > sizeof(block)) | |
166 | len = sizeof(block); | |
167 | memset(&block, 0, len); | |
f2cd2deb FS |
168 | } |
169 | if (len == 0) | |
170 | break; | |
171 | ||
172 | ret = libusb_bulk_transfer(usb->devhdl, 2, (unsigned char*)&block[0], len, &act_len, DEFAULT_TIMEOUT_MS); | |
173 | if (ret != 0) { | |
174 | sr_dbg("failed to write fpga bitstream block at %#x len %d: %s.", pos, (int)len, libusb_error_name(ret)); | |
175 | ret = SR_ERR; | |
176 | break; | |
177 | } | |
178 | if (act_len != len) { | |
179 | sr_dbg("failed to write fpga bitstream block at %#x len %d: act_len is %d.", pos, (int)len, act_len); | |
180 | ret = SR_ERR; | |
181 | break; | |
182 | } | |
183 | pos += len; | |
184 | } | |
185 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
186 | if (ret != 0) | |
187 | return ret; | |
3f48ab02 | 188 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", bitstream.size); |
f2cd2deb | 189 | |
00849545 | 190 | if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) { |
f2cd2deb FS |
191 | sr_err("failed to read response after FPGA bitstream upload"); |
192 | return ret; | |
193 | } | |
3f48ab02 FS |
194 | if (cmd_resp != 0) { |
195 | sr_err("after fpga bitstream upload command response is 0x%02x, expect 0!", cmd_resp); | |
196 | return SR_ERR; | |
197 | } | |
198 | ||
199 | g_usleep(30000); | |
f2cd2deb | 200 | |
00849545 | 201 | if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) { |
f2cd2deb FS |
202 | sr_err("failed enable fpga"); |
203 | return ret; | |
204 | } | |
205 | ||
3f48ab02 | 206 | g_usleep(40000); |
f2cd2deb FS |
207 | return SR_OK; |
208 | } | |
209 | ||
210 | static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) | |
211 | { | |
212 | struct dev_context *devc; | |
f2cd2deb FS |
213 | int ret; |
214 | ||
215 | devc = sdi->priv; | |
f2cd2deb | 216 | |
f2ad79d1 KG |
217 | uint16_t duty_R79,duty_R56; |
218 | uint8_t buf[2 * sizeof(uint16_t)]; | |
219 | uint8_t *wrptr; | |
220 | ||
221 | /* clamp threshold setting within valid range for LA2016 */ | |
222 | if (voltage > 4.0) { | |
223 | voltage = 4.0; | |
224 | } | |
225 | else if (voltage < -4.0) { | |
226 | voltage = -4.0; | |
227 | } | |
228 | ||
229 | /* | |
230 | * The fpga has two programmable pwm outputs which feed a dac that | |
231 | * is used to adjust input offset. The dac changes the input | |
232 | * swing around the fixed fpga input threshold. | |
233 | * The two pwm outputs can be seen on R79 and R56 respectvely. | |
234 | * Frequency is fixed at 100kHz and duty is varied. | |
235 | * The R79 pwm uses just three settings. | |
236 | * The R56 pwm varies with required threshold and its behaviour | |
237 | * also changes depending on the setting of R79 PWM. | |
238 | */ | |
239 | ||
240 | /* | |
241 | * calculate required pwm duty register values from requested threshold voltage | |
242 | * see last page of schematic (on wiki) for an explanation of these numbers | |
243 | */ | |
244 | if (voltage >= 2.9) { | |
245 | duty_R79 = 0; /* this pwm is off (0V)*/ | |
246 | duty_R56 = (uint16_t)(302 * voltage - 363); | |
247 | } | |
248 | else if (voltage <= -0.4) { | |
249 | duty_R79 = 0x02D7; /* 72% duty */ | |
250 | duty_R56 = (uint16_t)(302 * voltage + 1090); | |
251 | } | |
252 | else { | |
253 | duty_R79 = 0x00f2; /* 25% duty */ | |
254 | duty_R56 = (uint16_t)(302 * voltage + 121); | |
255 | } | |
256 | ||
257 | /* clamp duty register values at sensible limits */ | |
258 | if (duty_R56 < 10) { | |
259 | duty_R56 = 10; | |
260 | } | |
261 | else if (duty_R56 > 1100) { | |
262 | duty_R56 = 1100; | |
263 | } | |
264 | ||
265 | sr_dbg("set threshold voltage %.2fV", voltage); | |
266 | sr_dbg("duty_R56=0x%04x, duty_R79=0x%04x", duty_R56, duty_R79); | |
267 | ||
268 | wrptr = buf; | |
269 | write_u16le_inc(&wrptr, duty_R56); | |
270 | write_u16le_inc(&wrptr, duty_R79); | |
271 | ||
272 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf); | |
f2cd2deb | 273 | if (ret != SR_OK) { |
f2ad79d1 | 274 | sr_err("error setting new threshold voltage of %.2fV", voltage); |
f2cd2deb FS |
275 | return ret; |
276 | } | |
277 | devc->threshold_voltage = voltage; | |
278 | ||
279 | return SR_OK; | |
280 | } | |
281 | ||
282 | static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2) | |
283 | { | |
284 | struct dev_context *devc; | |
285 | uint8_t cfg; | |
286 | int ret; | |
287 | ||
288 | devc = sdi->priv; | |
289 | cfg = 0; | |
290 | ||
291 | if (p1) cfg |= 1 << 0; | |
292 | if (p2) cfg |= 1 << 1; | |
293 | ||
294 | sr_dbg("set pwm enable %d %d", p1, p2); | |
42f6dd55 | 295 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg)); |
f2cd2deb FS |
296 | if (ret != SR_OK) { |
297 | sr_err("error setting new pwm enable 0x%02x", cfg); | |
298 | return ret; | |
299 | } | |
300 | devc->pwm_setting[0].enabled = (p1) ? 1 : 0; | |
301 | devc->pwm_setting[1].enabled = (p2) ? 1 : 0; | |
302 | ||
303 | return SR_OK; | |
304 | } | |
305 | ||
306 | static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty) | |
307 | { | |
42f6dd55 | 308 | int CTRL_PWM[] = { REG_PWM1, REG_PWM2 }; |
f2cd2deb FS |
309 | struct dev_context *devc; |
310 | pwm_setting_dev_t cfg; | |
311 | pwm_setting_t *setting; | |
312 | int ret; | |
c3d40037 HK |
313 | uint8_t buf[2 * sizeof(uint32_t)]; |
314 | uint8_t *wrptr; | |
f2cd2deb FS |
315 | |
316 | devc = sdi->priv; | |
317 | ||
318 | if (which < 1 || which > 2) { | |
319 | sr_err("invalid pwm channel: %d", which); | |
320 | return SR_ERR; | |
321 | } | |
322 | if (freq > MAX_PWM_FREQ) { | |
323 | sr_err("pwm frequency too high: %.1f", freq); | |
324 | return SR_ERR; | |
325 | } | |
326 | if (duty > 100 || duty < 0) { | |
327 | sr_err("invalid pwm percentage: %f", duty); | |
328 | return SR_ERR; | |
329 | } | |
330 | ||
331 | cfg.period = (uint32_t)(PWM_CLOCK / freq); | |
332 | cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.)); | |
333 | sr_dbg("set pwm%d period %d, duty %d", which, cfg.period, cfg.duty); | |
334 | ||
c3d40037 HK |
335 | wrptr = buf; |
336 | write_u32le_inc(&wrptr, cfg.period); | |
337 | write_u32le_inc(&wrptr, cfg.duty); | |
00849545 | 338 | ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf); |
f2cd2deb FS |
339 | if (ret != SR_OK) { |
340 | sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty); | |
341 | return ret; | |
342 | } | |
343 | setting = &devc->pwm_setting[which - 1]; | |
344 | setting->freq = freq; | |
345 | setting->duty = duty; | |
f2cd2deb FS |
346 | |
347 | return SR_OK; | |
348 | } | |
349 | ||
350 | static int set_defaults(const struct sr_dev_inst *sdi) | |
351 | { | |
352 | struct dev_context *devc; | |
353 | int ret; | |
354 | ||
355 | devc = sdi->priv; | |
356 | ||
357 | devc->capture_ratio = 5; /* percent */ | |
358 | devc->cur_channels = 0xffff; | |
359 | devc->limit_samples = 5000000; | |
360 | devc->cur_samplerate = 200000000; | |
361 | ||
362 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
363 | if (ret) | |
364 | return ret; | |
365 | ||
366 | ret = enable_pwm(sdi, 0, 0); | |
367 | if (ret) | |
368 | return ret; | |
369 | ||
370 | ret = set_pwm(sdi, 1, 1e3, 50); | |
371 | if (ret) | |
372 | return ret; | |
373 | ||
374 | ret = set_pwm(sdi, 2, 100e3, 50); | |
375 | if (ret) | |
376 | return ret; | |
377 | ||
378 | ret = enable_pwm(sdi, 1, 1); | |
379 | if (ret) | |
380 | return ret; | |
381 | ||
382 | return SR_OK; | |
383 | } | |
384 | ||
385 | static int set_trigger_config(const struct sr_dev_inst *sdi) | |
386 | { | |
387 | struct dev_context *devc; | |
388 | struct sr_trigger *trigger; | |
389 | trigger_cfg_t cfg; | |
390 | GSList *stages; | |
391 | GSList *channel; | |
392 | struct sr_trigger_stage *stage1; | |
393 | struct sr_trigger_match *match; | |
394 | uint16_t ch_mask; | |
395 | int ret; | |
c3d40037 HK |
396 | uint8_t buf[4 * sizeof(uint32_t)]; |
397 | uint8_t *wrptr; | |
f2cd2deb FS |
398 | |
399 | devc = sdi->priv; | |
400 | trigger = sr_session_trigger_get(sdi->session); | |
401 | ||
402 | memset(&cfg, 0, sizeof(cfg)); | |
403 | ||
404 | cfg.channels = devc->cur_channels; | |
405 | ||
406 | if (trigger && trigger->stages) { | |
407 | stages = trigger->stages; | |
408 | stage1 = stages->data; | |
409 | if (stages->next) { | |
410 | sr_err("Only one trigger stage supported for now."); | |
411 | return SR_ERR; | |
412 | } | |
413 | channel = stage1->matches; | |
414 | while (channel) { | |
415 | match = channel->data; | |
416 | ch_mask = 1 << match->channel->index; | |
417 | ||
418 | switch (match->match) { | |
419 | case SR_TRIGGER_ZERO: | |
420 | cfg.level |= ch_mask; | |
421 | cfg.high_or_falling &= ~ch_mask; | |
422 | break; | |
423 | case SR_TRIGGER_ONE: | |
424 | cfg.level |= ch_mask; | |
425 | cfg.high_or_falling |= ch_mask; | |
426 | break; | |
427 | case SR_TRIGGER_RISING: | |
428 | if ((cfg.enabled & ~cfg.level)) { | |
429 | sr_err("Only one trigger signal with falling-/rising-edge allowed."); | |
430 | return SR_ERR; | |
431 | } | |
432 | cfg.level &= ~ch_mask; | |
433 | cfg.high_or_falling &= ~ch_mask; | |
434 | break; | |
435 | case SR_TRIGGER_FALLING: | |
436 | if ((cfg.enabled & ~cfg.level)) { | |
437 | sr_err("Only one trigger signal with falling-/rising-edge allowed."); | |
438 | return SR_ERR; | |
439 | } | |
440 | cfg.level &= ~ch_mask; | |
441 | cfg.high_or_falling |= ch_mask; | |
442 | break; | |
443 | default: | |
444 | sr_err("Unknown trigger value."); | |
445 | return SR_ERR; | |
446 | } | |
447 | cfg.enabled |= ch_mask; | |
448 | channel = channel->next; | |
449 | } | |
450 | } | |
451 | sr_dbg("set trigger configuration channels: 0x%04x, " | |
452 | "trigger-enabled 0x%04x, level-triggered 0x%04x, " | |
453 | "high/falling 0x%04x", cfg.channels, cfg.enabled, cfg.level, | |
454 | cfg.high_or_falling); | |
455 | ||
456 | devc->had_triggers_configured = cfg.enabled != 0; | |
457 | ||
c3d40037 HK |
458 | wrptr = buf; |
459 | write_u32le_inc(&wrptr, cfg.channels); | |
460 | write_u32le_inc(&wrptr, cfg.enabled); | |
461 | write_u32le_inc(&wrptr, cfg.level); | |
462 | write_u32le_inc(&wrptr, cfg.high_or_falling); | |
42f6dd55 | 463 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); |
f2cd2deb FS |
464 | if (ret != SR_OK) { |
465 | sr_err("error setting trigger config!"); | |
466 | return ret; | |
467 | } | |
468 | ||
469 | return SR_OK; | |
470 | } | |
471 | ||
472 | static int set_sample_config(const struct sr_dev_inst *sdi) | |
473 | { | |
474 | struct dev_context *devc; | |
f2cd2deb | 475 | double clock_divisor; |
f2cd2deb FS |
476 | uint64_t total; |
477 | int ret; | |
c3d40037 HK |
478 | uint16_t divisor; |
479 | uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)]; | |
480 | uint8_t *wrptr; | |
f2cd2deb FS |
481 | |
482 | devc = sdi->priv; | |
483 | total = 128 * 1024 * 1024; | |
484 | ||
485 | if (devc->cur_samplerate > MAX_SAMPLE_RATE) { | |
486 | sr_err("too high sample rate: %" PRIu64, devc->cur_samplerate); | |
487 | return SR_ERR; | |
488 | } | |
489 | ||
490 | clock_divisor = MAX_SAMPLE_RATE / (double)devc->cur_samplerate; | |
491 | if (clock_divisor > 0xffff) | |
492 | clock_divisor = 0xffff; | |
c3d40037 HK |
493 | divisor = (uint16_t)(clock_divisor + 0.5); |
494 | devc->cur_samplerate = MAX_SAMPLE_RATE / divisor; | |
f2cd2deb FS |
495 | |
496 | if (devc->limit_samples > MAX_SAMPLE_DEPTH) { | |
497 | sr_err("too high sample depth: %" PRIu64, devc->limit_samples); | |
498 | return SR_ERR; | |
499 | } | |
f2cd2deb FS |
500 | |
501 | devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100; | |
502 | ||
f2cd2deb | 503 | sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%", |
955ab604 | 504 | devc->cur_samplerate / 1e3, (unsigned int)devc->limit_samples, (unsigned int)devc->capture_ratio); |
f2cd2deb | 505 | |
c3d40037 HK |
506 | wrptr = buf; |
507 | write_u32le_inc(&wrptr, devc->limit_samples); | |
0d8e1ffc KG |
508 | write_u8_inc(&wrptr, 0); |
509 | write_u32le_inc(&wrptr, devc->pre_trigger_size); | |
510 | write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xFFFFFF00 ); | |
511 | write_u16le_inc(&wrptr, divisor); | |
512 | write_u8_inc(&wrptr, 0); | |
c3d40037 | 513 | |
42f6dd55 | 514 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); |
f2cd2deb FS |
515 | if (ret != SR_OK) { |
516 | sr_err("error setting sample config!"); | |
517 | return ret; | |
518 | } | |
519 | ||
520 | return SR_OK; | |
521 | } | |
522 | ||
523 | /** | |
524 | * lowest 2 bit are probably: | |
525 | * 2: recording | |
526 | * 1: finished | |
527 | * next 2 bit indicate whether we are still waiting for triggering | |
528 | * 0: waiting | |
529 | * 3: triggered | |
530 | */ | |
531 | static uint16_t run_state(const struct sr_dev_inst *sdi) | |
532 | { | |
533 | uint16_t state; | |
534 | int ret; | |
535 | ||
42f6dd55 | 536 | if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) { |
f2cd2deb FS |
537 | sr_err("failed to read run state!"); |
538 | return ret; | |
539 | } | |
540 | sr_dbg("run_state: 0x%04x", state); | |
541 | ||
542 | return state; | |
543 | } | |
544 | ||
545 | static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking) | |
546 | { | |
547 | int ret; | |
548 | ||
42f6dd55 | 549 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) { |
f2cd2deb FS |
550 | sr_err("failed to send set-run-mode command %d", fast_blinking); |
551 | return ret; | |
552 | } | |
553 | ||
554 | return SR_OK; | |
555 | } | |
556 | ||
557 | static int get_capture_info(const struct sr_dev_inst *sdi) | |
558 | { | |
559 | struct dev_context *devc; | |
560 | int ret; | |
c3d40037 HK |
561 | uint8_t buf[3 * sizeof(uint32_t)]; |
562 | const uint8_t *rdptr; | |
f2cd2deb FS |
563 | |
564 | devc = sdi->priv; | |
565 | ||
42f6dd55 | 566 | if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf))) != SR_OK) { |
f2cd2deb FS |
567 | sr_err("failed to read capture info!"); |
568 | return ret; | |
569 | } | |
c3d40037 HK |
570 | |
571 | rdptr = buf; | |
572 | devc->info.n_rep_packets = read_u32le_inc(&rdptr); | |
573 | devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); | |
574 | devc->info.write_pos = read_u32le_inc(&rdptr); | |
f2cd2deb FS |
575 | |
576 | sr_dbg("capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d", | |
577 | devc->info.n_rep_packets, devc->info.n_rep_packets, | |
578 | devc->info.n_rep_packets_before_trigger, devc->info.n_rep_packets_before_trigger, | |
579 | devc->info.write_pos, devc->info.write_pos); | |
580 | ||
581 | if (devc->info.n_rep_packets % 5) | |
582 | sr_warn("number of packets is not as expected multiples of 5: %d", devc->info.n_rep_packets); | |
583 | ||
584 | return SR_OK; | |
585 | } | |
586 | ||
587 | SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id) | |
588 | { | |
589 | char fw_file[1024]; | |
590 | snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id); | |
40a0b2f4 | 591 | return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file); |
f2cd2deb FS |
592 | } |
593 | ||
594 | SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) | |
595 | { | |
596 | struct dev_context *devc; | |
597 | int ret; | |
598 | uint8_t cmd; | |
599 | ||
600 | devc = sdi->priv; | |
601 | ||
602 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
603 | if (ret != SR_OK) | |
604 | return ret; | |
605 | ||
606 | cmd = 0; | |
42f6dd55 | 607 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd))) != SR_OK) { |
f2cd2deb FS |
608 | sr_err("failed to send stop sampling command"); |
609 | return ret; | |
610 | } | |
611 | ||
612 | ret = set_trigger_config(sdi); | |
613 | if (ret != SR_OK) | |
614 | return ret; | |
615 | ||
616 | ret = set_sample_config(sdi); | |
617 | if (ret != SR_OK) | |
618 | return ret; | |
619 | ||
620 | return SR_OK; | |
621 | } | |
622 | ||
623 | SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) | |
624 | { | |
625 | return set_run_mode(sdi, 3); | |
626 | } | |
627 | ||
628 | SR_PRIV int la2016_stop_acquisition(const struct sr_dev_inst *sdi) | |
629 | { | |
630 | return set_run_mode(sdi, 0); | |
631 | } | |
632 | ||
633 | SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) | |
634 | { | |
635 | return la2016_stop_acquisition(sdi); | |
636 | } | |
637 | ||
638 | SR_PRIV int la2016_has_triggered(const struct sr_dev_inst *sdi) | |
639 | { | |
640 | uint16_t state; | |
641 | ||
642 | state = run_state(sdi); | |
643 | ||
644 | return (state & 0x3) == 1; | |
645 | } | |
646 | ||
647 | SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb) | |
648 | { | |
649 | struct dev_context *devc; | |
650 | struct sr_usb_dev_inst *usb; | |
651 | int ret; | |
c3d40037 HK |
652 | uint8_t wrbuf[2 * sizeof(uint32_t)]; |
653 | uint8_t *wrptr; | |
f2cd2deb FS |
654 | uint32_t to_read; |
655 | uint8_t *buffer; | |
656 | ||
657 | devc = sdi->priv; | |
658 | usb = sdi->conn; | |
659 | ||
660 | if ((ret = get_capture_info(sdi)) != SR_OK) | |
661 | return ret; | |
662 | ||
c3d40037 HK |
663 | devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK; |
664 | devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH; | |
f2cd2deb FS |
665 | devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; |
666 | devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; | |
667 | ||
668 | sr_dbg("want to read %d tfer-packets starting from pos %d", | |
669 | devc->n_transfer_packets_to_read, devc->read_pos); | |
670 | ||
00849545 | 671 | if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { |
f2cd2deb FS |
672 | sr_err("failed to reset bulk state"); |
673 | return ret; | |
674 | } | |
f2cd2deb | 675 | sr_dbg("will read from 0x%08x, 0x%08x bytes", devc->read_pos, devc->n_bytes_to_read); |
c3d40037 HK |
676 | wrptr = wrbuf; |
677 | write_u32le_inc(&wrptr, devc->read_pos); | |
678 | write_u32le_inc(&wrptr, devc->n_bytes_to_read); | |
42f6dd55 | 679 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) { |
f2cd2deb FS |
680 | sr_err("failed to send bulk config"); |
681 | return ret; | |
682 | } | |
00849545 | 683 | if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) { |
f2cd2deb FS |
684 | sr_err("failed to unblock bulk transfers"); |
685 | return ret; | |
686 | } | |
687 | ||
688 | to_read = devc->n_bytes_to_read; | |
689 | if (to_read > LA2016_BULK_MAX) | |
690 | to_read = LA2016_BULK_MAX; | |
691 | ||
692 | buffer = g_try_malloc(to_read); | |
693 | if (!buffer) { | |
694 | sr_err("Failed to allocate %d bytes for bulk transfer", to_read); | |
695 | return SR_ERR_MALLOC; | |
696 | } | |
697 | ||
698 | devc->transfer = libusb_alloc_transfer(0); | |
699 | libusb_fill_bulk_transfer( | |
700 | devc->transfer, usb->devhdl, | |
701 | 0x86, buffer, to_read, | |
702 | cb, (void *)sdi, DEFAULT_TIMEOUT_MS); | |
703 | ||
704 | if ((ret = libusb_submit_transfer(devc->transfer)) != 0) { | |
705 | sr_err("Failed to submit transfer: %s.", libusb_error_name(ret)); | |
706 | libusb_free_transfer(devc->transfer); | |
707 | devc->transfer = NULL; | |
708 | g_free(buffer); | |
709 | return SR_ERR; | |
710 | } | |
711 | ||
712 | return SR_OK; | |
713 | } | |
714 | ||
715 | SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) | |
716 | { | |
f2cd2deb | 717 | uint16_t state; |
9de389b1 KG |
718 | uint8_t buf[8]; |
719 | int16_t purchase_date_bcd[2]; | |
720 | uint8_t magic; | |
721 | int ret; | |
f2cd2deb | 722 | |
9de389b1 KG |
723 | /* Four bytes of eeprom at 0x20 are purchase year & month in BCD format, with 16bit |
724 | * complemented checksum; e.g. 2004DFFB = 2020-April. | |
725 | * This helps to identify the age of devices if unknown magic numbers occur. | |
726 | */ | |
727 | if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, purchase_date_bcd, sizeof(purchase_date_bcd))) != SR_OK) { | |
728 | sr_err("failed to read eeprom purchase_date_bcd"); | |
729 | } | |
730 | else { | |
731 | sr_dbg("purchase date: 20%02hx-%02hx", (purchase_date_bcd[0]) & 0x00ff, (purchase_date_bcd[0] >> 8) & 0x00ff); | |
732 | if( purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1]) ) { | |
733 | sr_err("purchase date: checksum failure"); | |
734 | } | |
f2cd2deb | 735 | } |
f2cd2deb | 736 | |
9de389b1 KG |
737 | /* |
738 | * There are four known kingst logic analyser devices which use this same usb vid and pid: | |
739 | * LA2016, LA1016 and the older revision of each of these. They all use the same hardware | |
740 | * and the same FX2 mcu firmware but each requires a different fpga bitstream. They are | |
741 | * differentiated by a 'magic' byte within the 8 bytes of EEPROM from address 0x08. | |
742 | * For example; | |
743 | * | |
744 | * magic=0x08 | |
745 | * | ~magic=0xf7 | |
746 | * | | | |
747 | * 08F7000008F710EF | |
748 | * | | | |
749 | * | ~magic-backup | |
750 | * magic-backup | |
751 | * | |
752 | * It seems that only these magic bytes are used, other bytes shown above are 'don't care'. | |
753 | * Changing the magic byte on newer device to older magic causes OEM software to load | |
754 | * the older fpga bitstream. The device then functions but has channels out of order. | |
755 | * It's likely the bitstreams were changed to move input channel pins due to PCB changes. | |
756 | * | |
757 | * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others) | |
758 | * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others) | |
759 | * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" | |
760 | * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" | |
761 | * | |
762 | * This was all determined by altering the eeprom contents of an LA2016 and LA1016 and observing | |
763 | * the vendor software actions, either raising errors or loading specific bitstreams. | |
764 | * | |
765 | * Note: | |
766 | * An LA1016 cannot be converted to an LA2016 by changing the magic number - the bitstream | |
767 | * will not authenticate with ic U10, which has different security coding for each device type. | |
768 | */ | |
769 | ||
770 | if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &buf, sizeof(buf))) != SR_OK) { | |
771 | sr_err("failed to read eeprom device identifier bytes"); | |
f2cd2deb FS |
772 | return ret; |
773 | } | |
f2cd2deb | 774 | |
9de389b1 KG |
775 | magic = 0; |
776 | if (buf[0] == (0x0ff & ~buf[1])) { | |
777 | /* primary copy of magic passes complement check */ | |
778 | magic = buf[0]; | |
779 | } | |
780 | else if (buf[4] == (0x0ff & ~buf[5])) { | |
781 | /* backup copy of magic passes complement check */ | |
782 | sr_dbg("device_type: using backup copy of magic number"); | |
783 | magic = buf[4]; | |
f2cd2deb FS |
784 | } |
785 | ||
9de389b1 KG |
786 | sr_dbg("device_type: magic number is %hhu", magic); |
787 | ||
788 | /* select the correct fpga bitstream for this device */ | |
789 | switch (magic) { | |
790 | case 2: | |
791 | ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016); | |
792 | break; | |
793 | case 8: | |
794 | ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016A); | |
795 | break; | |
796 | default: | |
797 | sr_err("device_type: device not supported; magic number indicates this is not an LA2016"); | |
3f48ab02 FS |
798 | return SR_ERR; |
799 | } | |
f2cd2deb | 800 | |
9de389b1 KG |
801 | if (ret != SR_OK) { |
802 | sr_err("failed to upload fpga bitstream"); | |
803 | return ret; | |
804 | } | |
805 | ||
f2cd2deb | 806 | state = run_state(sdi); |
9de389b1 | 807 | if (state != 0x85e9) { |
f2cd2deb | 808 | sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state); |
9de389b1 | 809 | } |
f2cd2deb | 810 | |
00849545 | 811 | if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { |
bb706a76 | 812 | sr_err("failed to send CMD_BULK_RESET"); |
f2cd2deb FS |
813 | return ret; |
814 | } | |
9de389b1 | 815 | |
f2cd2deb FS |
816 | sr_dbg("device should be initialized"); |
817 | ||
818 | return set_defaults(sdi); | |
819 | } | |
820 | ||
821 | SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi) | |
822 | { | |
823 | int ret; | |
824 | ||
00849545 | 825 | if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) { |
f2cd2deb FS |
826 | sr_err("failed to send deinit command"); |
827 | return ret; | |
828 | } | |
829 | ||
830 | return SR_OK; | |
831 | } |