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f2cd2deb FS |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de> | |
5 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
6 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
7 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
8 | * | |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <config.h> | |
24 | #include <stdint.h> | |
25 | #include <string.h> | |
26 | #include <glib.h> | |
27 | #include <glib/gstdio.h> | |
28 | #include <stdio.h> | |
29 | #include <errno.h> | |
30 | #include <math.h> | |
31 | #include <libsigrok/libsigrok.h> | |
32 | #include "libsigrok-internal.h" | |
33 | #include "protocol.h" | |
34 | ||
35 | #define FPGA_FIRMWARE "kingst-la2016a-fpga.bitstream" | |
36 | #define UC_FIRMWARE "kingst-la-%04x.fw" | |
37 | ||
38 | #define MAX_SAMPLE_RATE SR_MHZ(200) | |
39 | #define MAX_SAMPLE_DEPTH 10e9 | |
40 | #define MAX_PWM_FREQ SR_MHZ(20) | |
41 | #define PWM_CLOCK SR_MHZ(200) | |
42 | ||
43 | /* registers for control request 32: */ | |
44 | #define CTRL_RUN 0x00 | |
45 | #define CTRL_PWM_EN 0x02 | |
46 | #define CTRL_BULK 0x10 /* can be read to get 12 byte sampling_info (III) */ | |
47 | #define CTRL_SAMPLING 0x20 | |
48 | #define CTRL_TRIGGER 0x30 | |
49 | #define CTRL_THRESHOLD 0x48 | |
50 | #define CTRL_PWM1 0x70 | |
51 | #define CTRL_PWM2 0x78 | |
52 | ||
53 | static int ctrl_in(const struct sr_dev_inst *sdi, | |
54 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, | |
55 | void *data, uint16_t wLength) | |
56 | { | |
57 | struct sr_usb_dev_inst *usb; | |
58 | int ret; | |
59 | ||
60 | usb = sdi->conn; | |
61 | ||
62 | if ((ret = libusb_control_transfer( | |
63 | usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, | |
64 | bRequest, wValue, wIndex, (unsigned char *)data, wLength, | |
65 | DEFAULT_TIMEOUT_MS)) != wLength) { | |
66 | sr_err("failed to read %d bytes via ctrl-in %d %#x, %d: %s.", | |
67 | wLength, bRequest, wValue, wIndex, | |
68 | libusb_error_name(ret)); | |
69 | return SR_ERR; | |
70 | } | |
71 | ||
72 | return SR_OK; | |
73 | } | |
74 | ||
75 | static int ctrl_out(const struct sr_dev_inst *sdi, | |
76 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, | |
77 | void *data, uint16_t wLength) | |
78 | { | |
79 | struct sr_usb_dev_inst *usb; | |
80 | int ret; | |
81 | ||
82 | usb = sdi->conn; | |
83 | ||
84 | if ((ret = libusb_control_transfer( | |
85 | usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, | |
86 | bRequest, wValue, wIndex, (unsigned char*)data, wLength, | |
87 | DEFAULT_TIMEOUT_MS)) != wLength) { | |
88 | sr_err("failed to write %d bytes via ctrl-out %d %#x, %d: %s.", | |
89 | wLength, bRequest, wValue, wIndex, | |
90 | libusb_error_name(ret)); | |
91 | return SR_ERR; | |
92 | } | |
93 | ||
94 | return SR_OK; | |
95 | } | |
96 | ||
97 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi) | |
98 | { | |
99 | struct drv_context *drvc; | |
100 | struct sr_usb_dev_inst *usb; | |
101 | struct sr_resource bitstream; | |
102 | uint32_t cmd; | |
103 | uint8_t cmd_resp; | |
104 | uint8_t block[4096]; | |
105 | int pos, len, act_len; | |
106 | int ret; | |
107 | ||
108 | drvc = sdi->driver->context; | |
109 | usb = sdi->conn; | |
110 | ||
111 | sr_info("Uploading FPGA bitstream '%s'.", FPGA_FIRMWARE); | |
112 | ||
113 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, FPGA_FIRMWARE); | |
114 | if (ret != SR_OK) { | |
115 | sr_err("could not find la2016 firmware %s!", FPGA_FIRMWARE); | |
116 | return ret; | |
117 | } | |
118 | ||
119 | WL32(&cmd, 0x2b602); | |
120 | if ((ret = ctrl_out(sdi, 80, 0x00, 0, &cmd, sizeof(cmd))) != SR_OK) { | |
121 | sr_err("failed to give upload init command"); | |
122 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
123 | return ret; | |
124 | } | |
125 | ||
126 | pos = 0; | |
127 | while (1) { | |
128 | len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block)); | |
129 | if (len < 0) { | |
130 | sr_err("failed to read from fpga bitstream!"); | |
131 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
132 | return SR_ERR; | |
133 | } | |
134 | if (len == 0) | |
135 | break; | |
136 | ||
137 | ret = libusb_bulk_transfer(usb->devhdl, 2, (unsigned char*)&block[0], len, &act_len, DEFAULT_TIMEOUT_MS); | |
138 | if (ret != 0) { | |
139 | sr_dbg("failed to write fpga bitstream block at %#x len %d: %s.", pos, (int)len, libusb_error_name(ret)); | |
140 | ret = SR_ERR; | |
141 | break; | |
142 | } | |
143 | if (act_len != len) { | |
144 | sr_dbg("failed to write fpga bitstream block at %#x len %d: act_len is %d.", pos, (int)len, act_len); | |
145 | ret = SR_ERR; | |
146 | break; | |
147 | } | |
148 | pos += len; | |
149 | } | |
150 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
151 | if (ret != 0) | |
152 | return ret; | |
153 | sr_info("FPGA bitstream upload (%d bytes) done.", pos); | |
154 | ||
155 | if ((ret = ctrl_in(sdi, 80, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) { | |
156 | sr_err("failed to read response after FPGA bitstream upload"); | |
157 | return ret; | |
158 | } | |
159 | if (cmd_resp != 0) | |
160 | sr_warn("after fpga bitstream upload command response is 0x%02x, expect 0", cmd_resp); | |
161 | ||
162 | if ((ret = ctrl_out(sdi, 16, 0x01, 0, NULL, 0)) != SR_OK) { | |
163 | sr_err("failed enable fpga"); | |
164 | return ret; | |
165 | } | |
166 | ||
167 | return SR_OK; | |
168 | } | |
169 | ||
170 | static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) | |
171 | { | |
172 | struct dev_context *devc; | |
173 | float o1, o2, v1, v2, f; | |
174 | uint32_t cfg; | |
175 | int ret; | |
176 | ||
177 | devc = sdi->priv; | |
178 | o1 = 15859969; v1 = 0.45; | |
179 | o2 = 15860333; v2 = 1.65; | |
180 | f = (o2 - o1) / (v2 - v1); | |
181 | WL32(&cfg, (uint32_t)(o1 + (voltage - v1) * f)); | |
182 | ||
183 | sr_dbg("set threshold voltage %.2fV", voltage); | |
184 | ret = ctrl_out(sdi, 32, CTRL_THRESHOLD, 0, &cfg, sizeof(cfg)); | |
185 | if (ret != SR_OK) { | |
186 | sr_err("error setting new threshold voltage of %.2fV (%d)", voltage, RL16(&cfg)); | |
187 | return ret; | |
188 | } | |
189 | devc->threshold_voltage = voltage; | |
190 | ||
191 | return SR_OK; | |
192 | } | |
193 | ||
194 | static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2) | |
195 | { | |
196 | struct dev_context *devc; | |
197 | uint8_t cfg; | |
198 | int ret; | |
199 | ||
200 | devc = sdi->priv; | |
201 | cfg = 0; | |
202 | ||
203 | if (p1) cfg |= 1 << 0; | |
204 | if (p2) cfg |= 1 << 1; | |
205 | ||
206 | sr_dbg("set pwm enable %d %d", p1, p2); | |
207 | ret = ctrl_out(sdi, 32, CTRL_PWM_EN, 0, &cfg, sizeof(cfg)); | |
208 | if (ret != SR_OK) { | |
209 | sr_err("error setting new pwm enable 0x%02x", cfg); | |
210 | return ret; | |
211 | } | |
212 | devc->pwm_setting[0].enabled = (p1) ? 1 : 0; | |
213 | devc->pwm_setting[1].enabled = (p2) ? 1 : 0; | |
214 | ||
215 | return SR_OK; | |
216 | } | |
217 | ||
218 | static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty) | |
219 | { | |
220 | int CTRL_PWM[] = { CTRL_PWM1, CTRL_PWM2 }; | |
221 | struct dev_context *devc; | |
222 | pwm_setting_dev_t cfg; | |
223 | pwm_setting_t *setting; | |
224 | int ret; | |
225 | ||
226 | devc = sdi->priv; | |
227 | ||
228 | if (which < 1 || which > 2) { | |
229 | sr_err("invalid pwm channel: %d", which); | |
230 | return SR_ERR; | |
231 | } | |
232 | if (freq > MAX_PWM_FREQ) { | |
233 | sr_err("pwm frequency too high: %.1f", freq); | |
234 | return SR_ERR; | |
235 | } | |
236 | if (duty > 100 || duty < 0) { | |
237 | sr_err("invalid pwm percentage: %f", duty); | |
238 | return SR_ERR; | |
239 | } | |
240 | ||
241 | cfg.period = (uint32_t)(PWM_CLOCK / freq); | |
242 | cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.)); | |
243 | sr_dbg("set pwm%d period %d, duty %d", which, cfg.period, cfg.duty); | |
244 | ||
245 | pwm_setting_dev_le(cfg); | |
246 | ret = ctrl_out(sdi, 32, CTRL_PWM[which - 1], 0, &cfg, sizeof(cfg)); | |
247 | if (ret != SR_OK) { | |
248 | sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty); | |
249 | return ret; | |
250 | } | |
251 | setting = &devc->pwm_setting[which - 1]; | |
252 | setting->freq = freq; | |
253 | setting->duty = duty; | |
254 | setting->dev = cfg; | |
255 | ||
256 | return SR_OK; | |
257 | } | |
258 | ||
259 | static int set_defaults(const struct sr_dev_inst *sdi) | |
260 | { | |
261 | struct dev_context *devc; | |
262 | int ret; | |
263 | ||
264 | devc = sdi->priv; | |
265 | ||
266 | devc->capture_ratio = 5; /* percent */ | |
267 | devc->cur_channels = 0xffff; | |
268 | devc->limit_samples = 5000000; | |
269 | devc->cur_samplerate = 200000000; | |
270 | ||
271 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
272 | if (ret) | |
273 | return ret; | |
274 | ||
275 | ret = enable_pwm(sdi, 0, 0); | |
276 | if (ret) | |
277 | return ret; | |
278 | ||
279 | ret = set_pwm(sdi, 1, 1e3, 50); | |
280 | if (ret) | |
281 | return ret; | |
282 | ||
283 | ret = set_pwm(sdi, 2, 100e3, 50); | |
284 | if (ret) | |
285 | return ret; | |
286 | ||
287 | ret = enable_pwm(sdi, 1, 1); | |
288 | if (ret) | |
289 | return ret; | |
290 | ||
291 | return SR_OK; | |
292 | } | |
293 | ||
294 | static int set_trigger_config(const struct sr_dev_inst *sdi) | |
295 | { | |
296 | struct dev_context *devc; | |
297 | struct sr_trigger *trigger; | |
298 | trigger_cfg_t cfg; | |
299 | GSList *stages; | |
300 | GSList *channel; | |
301 | struct sr_trigger_stage *stage1; | |
302 | struct sr_trigger_match *match; | |
303 | uint16_t ch_mask; | |
304 | int ret; | |
305 | ||
306 | devc = sdi->priv; | |
307 | trigger = sr_session_trigger_get(sdi->session); | |
308 | ||
309 | memset(&cfg, 0, sizeof(cfg)); | |
310 | ||
311 | cfg.channels = devc->cur_channels; | |
312 | ||
313 | if (trigger && trigger->stages) { | |
314 | stages = trigger->stages; | |
315 | stage1 = stages->data; | |
316 | if (stages->next) { | |
317 | sr_err("Only one trigger stage supported for now."); | |
318 | return SR_ERR; | |
319 | } | |
320 | channel = stage1->matches; | |
321 | while (channel) { | |
322 | match = channel->data; | |
323 | ch_mask = 1 << match->channel->index; | |
324 | ||
325 | switch (match->match) { | |
326 | case SR_TRIGGER_ZERO: | |
327 | cfg.level |= ch_mask; | |
328 | cfg.high_or_falling &= ~ch_mask; | |
329 | break; | |
330 | case SR_TRIGGER_ONE: | |
331 | cfg.level |= ch_mask; | |
332 | cfg.high_or_falling |= ch_mask; | |
333 | break; | |
334 | case SR_TRIGGER_RISING: | |
335 | if ((cfg.enabled & ~cfg.level)) { | |
336 | sr_err("Only one trigger signal with falling-/rising-edge allowed."); | |
337 | return SR_ERR; | |
338 | } | |
339 | cfg.level &= ~ch_mask; | |
340 | cfg.high_or_falling &= ~ch_mask; | |
341 | break; | |
342 | case SR_TRIGGER_FALLING: | |
343 | if ((cfg.enabled & ~cfg.level)) { | |
344 | sr_err("Only one trigger signal with falling-/rising-edge allowed."); | |
345 | return SR_ERR; | |
346 | } | |
347 | cfg.level &= ~ch_mask; | |
348 | cfg.high_or_falling |= ch_mask; | |
349 | break; | |
350 | default: | |
351 | sr_err("Unknown trigger value."); | |
352 | return SR_ERR; | |
353 | } | |
354 | cfg.enabled |= ch_mask; | |
355 | channel = channel->next; | |
356 | } | |
357 | } | |
358 | sr_dbg("set trigger configuration channels: 0x%04x, " | |
359 | "trigger-enabled 0x%04x, level-triggered 0x%04x, " | |
360 | "high/falling 0x%04x", cfg.channels, cfg.enabled, cfg.level, | |
361 | cfg.high_or_falling); | |
362 | ||
363 | devc->had_triggers_configured = cfg.enabled != 0; | |
364 | ||
365 | trigger_cfg_le(cfg); | |
366 | ret = ctrl_out(sdi, 32, CTRL_TRIGGER, 16, &cfg, sizeof(cfg)); | |
367 | if (ret != SR_OK) { | |
368 | sr_err("error setting trigger config!"); | |
369 | return ret; | |
370 | } | |
371 | ||
372 | return SR_OK; | |
373 | } | |
374 | ||
375 | static int set_sample_config(const struct sr_dev_inst *sdi) | |
376 | { | |
377 | struct dev_context *devc; | |
378 | sample_config_t cfg; | |
379 | double clock_divisor; | |
380 | uint64_t psa; | |
381 | uint64_t total; | |
382 | int ret; | |
383 | ||
384 | devc = sdi->priv; | |
385 | total = 128 * 1024 * 1024; | |
386 | ||
387 | if (devc->cur_samplerate > MAX_SAMPLE_RATE) { | |
388 | sr_err("too high sample rate: %" PRIu64, devc->cur_samplerate); | |
389 | return SR_ERR; | |
390 | } | |
391 | ||
392 | clock_divisor = MAX_SAMPLE_RATE / (double)devc->cur_samplerate; | |
393 | if (clock_divisor > 0xffff) | |
394 | clock_divisor = 0xffff; | |
395 | cfg.clock_divisor = (uint16_t)(clock_divisor + 0.5); | |
396 | devc->cur_samplerate = MAX_SAMPLE_RATE / cfg.clock_divisor; | |
397 | ||
398 | if (devc->limit_samples > MAX_SAMPLE_DEPTH) { | |
399 | sr_err("too high sample depth: %" PRIu64, devc->limit_samples); | |
400 | return SR_ERR; | |
401 | } | |
402 | cfg.sample_depth = devc->limit_samples; | |
403 | ||
404 | devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100; | |
405 | ||
406 | psa = devc->pre_trigger_size * 256; | |
407 | cfg.psa = (uint32_t)(psa & 0xffffffff); | |
408 | cfg.u1 = (uint16_t)((psa >> 32) & 0xffff); | |
409 | cfg.u2 = (uint32_t)((total * devc->capture_ratio) / 100); | |
410 | ||
411 | sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%", | |
412 | devc->cur_samplerate/1e3, (unsigned int)cfg.sample_depth, (unsigned int)devc->capture_ratio); | |
413 | ||
414 | sample_config_le(cfg); | |
415 | ret = ctrl_out(sdi, 32, CTRL_SAMPLING, 0, &cfg, sizeof(cfg)); | |
416 | if (ret != SR_OK) { | |
417 | sr_err("error setting sample config!"); | |
418 | return ret; | |
419 | } | |
420 | ||
421 | return SR_OK; | |
422 | } | |
423 | ||
424 | /** | |
425 | * lowest 2 bit are probably: | |
426 | * 2: recording | |
427 | * 1: finished | |
428 | * next 2 bit indicate whether we are still waiting for triggering | |
429 | * 0: waiting | |
430 | * 3: triggered | |
431 | */ | |
432 | static uint16_t run_state(const struct sr_dev_inst *sdi) | |
433 | { | |
434 | uint16_t state; | |
435 | int ret; | |
436 | ||
437 | if ((ret = ctrl_in(sdi, 32, CTRL_RUN, 0, &state, sizeof(state))) != SR_OK) { | |
438 | sr_err("failed to read run state!"); | |
439 | return ret; | |
440 | } | |
441 | sr_dbg("run_state: 0x%04x", state); | |
442 | ||
443 | return state; | |
444 | } | |
445 | ||
446 | static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking) | |
447 | { | |
448 | int ret; | |
449 | ||
450 | if ((ret = ctrl_out(sdi, 32, CTRL_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) { | |
451 | sr_err("failed to send set-run-mode command %d", fast_blinking); | |
452 | return ret; | |
453 | } | |
454 | ||
455 | return SR_OK; | |
456 | } | |
457 | ||
458 | static int get_capture_info(const struct sr_dev_inst *sdi) | |
459 | { | |
460 | struct dev_context *devc; | |
461 | int ret; | |
462 | ||
463 | devc = sdi->priv; | |
464 | ||
465 | if ((ret = ctrl_in(sdi, 32, CTRL_BULK, 0, &devc->info, sizeof(devc->info))) != SR_OK) { | |
466 | sr_err("failed to read capture info!"); | |
467 | return ret; | |
468 | } | |
469 | capture_info_host(devc->info); | |
470 | ||
471 | sr_dbg("capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d", | |
472 | devc->info.n_rep_packets, devc->info.n_rep_packets, | |
473 | devc->info.n_rep_packets_before_trigger, devc->info.n_rep_packets_before_trigger, | |
474 | devc->info.write_pos, devc->info.write_pos); | |
475 | ||
476 | if (devc->info.n_rep_packets % 5) | |
477 | sr_warn("number of packets is not as expected multiples of 5: %d", devc->info.n_rep_packets); | |
478 | ||
479 | return SR_OK; | |
480 | } | |
481 | ||
482 | SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id) | |
483 | { | |
484 | char fw_file[1024]; | |
485 | snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id); | |
486 | return ezusb_upload_firmware(sr_ctx, dev, 0, fw_file); | |
487 | } | |
488 | ||
489 | SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) | |
490 | { | |
491 | struct dev_context *devc; | |
492 | int ret; | |
493 | uint8_t cmd; | |
494 | ||
495 | devc = sdi->priv; | |
496 | ||
497 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
498 | if (ret != SR_OK) | |
499 | return ret; | |
500 | ||
501 | cmd = 0; | |
502 | if ((ret = ctrl_out(sdi, 32, 0x03, 0, &cmd, sizeof(cmd))) != SR_OK) { | |
503 | sr_err("failed to send stop sampling command"); | |
504 | return ret; | |
505 | } | |
506 | ||
507 | ret = set_trigger_config(sdi); | |
508 | if (ret != SR_OK) | |
509 | return ret; | |
510 | ||
511 | ret = set_sample_config(sdi); | |
512 | if (ret != SR_OK) | |
513 | return ret; | |
514 | ||
515 | return SR_OK; | |
516 | } | |
517 | ||
518 | SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) | |
519 | { | |
520 | return set_run_mode(sdi, 3); | |
521 | } | |
522 | ||
523 | SR_PRIV int la2016_stop_acquisition(const struct sr_dev_inst *sdi) | |
524 | { | |
525 | return set_run_mode(sdi, 0); | |
526 | } | |
527 | ||
528 | SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) | |
529 | { | |
530 | return la2016_stop_acquisition(sdi); | |
531 | } | |
532 | ||
533 | SR_PRIV int la2016_has_triggered(const struct sr_dev_inst *sdi) | |
534 | { | |
535 | uint16_t state; | |
536 | ||
537 | state = run_state(sdi); | |
538 | ||
539 | return (state & 0x3) == 1; | |
540 | } | |
541 | ||
542 | SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb) | |
543 | { | |
544 | struct dev_context *devc; | |
545 | struct sr_usb_dev_inst *usb; | |
546 | int ret; | |
547 | uint32_t bulk_cfg[2]; | |
548 | uint32_t to_read; | |
549 | uint8_t *buffer; | |
550 | ||
551 | devc = sdi->priv; | |
552 | usb = sdi->conn; | |
553 | ||
554 | if ((ret = get_capture_info(sdi)) != SR_OK) | |
555 | return ret; | |
556 | ||
557 | devc->n_transfer_packets_to_read = devc->info.n_rep_packets / 5; | |
558 | devc->n_bytes_to_read = devc->n_transfer_packets_to_read * sizeof(transfer_packet_t); | |
559 | devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; | |
560 | devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; | |
561 | ||
562 | sr_dbg("want to read %d tfer-packets starting from pos %d", | |
563 | devc->n_transfer_packets_to_read, devc->read_pos); | |
564 | ||
565 | if ((ret = ctrl_out(sdi, 56, 0x00, 0, NULL, 0)) != SR_OK) { | |
566 | sr_err("failed to reset bulk state"); | |
567 | return ret; | |
568 | } | |
569 | WL32(&bulk_cfg[0], devc->read_pos); | |
570 | WL32(&bulk_cfg[1], devc->n_bytes_to_read); | |
571 | sr_dbg("will read from 0x%08x, 0x%08x bytes", devc->read_pos, devc->n_bytes_to_read); | |
572 | if ((ret = ctrl_out(sdi, 32, CTRL_BULK, 0, &bulk_cfg, sizeof(bulk_cfg))) != SR_OK) { | |
573 | sr_err("failed to send bulk config"); | |
574 | return ret; | |
575 | } | |
576 | if ((ret = ctrl_out(sdi, 48, 0x00, 0, NULL, 0)) != SR_OK) { | |
577 | sr_err("failed to unblock bulk transfers"); | |
578 | return ret; | |
579 | } | |
580 | ||
581 | to_read = devc->n_bytes_to_read; | |
582 | if (to_read > LA2016_BULK_MAX) | |
583 | to_read = LA2016_BULK_MAX; | |
584 | ||
585 | buffer = g_try_malloc(to_read); | |
586 | if (!buffer) { | |
587 | sr_err("Failed to allocate %d bytes for bulk transfer", to_read); | |
588 | return SR_ERR_MALLOC; | |
589 | } | |
590 | ||
591 | devc->transfer = libusb_alloc_transfer(0); | |
592 | libusb_fill_bulk_transfer( | |
593 | devc->transfer, usb->devhdl, | |
594 | 0x86, buffer, to_read, | |
595 | cb, (void *)sdi, DEFAULT_TIMEOUT_MS); | |
596 | ||
597 | if ((ret = libusb_submit_transfer(devc->transfer)) != 0) { | |
598 | sr_err("Failed to submit transfer: %s.", libusb_error_name(ret)); | |
599 | libusb_free_transfer(devc->transfer); | |
600 | devc->transfer = NULL; | |
601 | g_free(buffer); | |
602 | return SR_ERR; | |
603 | } | |
604 | ||
605 | return SR_OK; | |
606 | } | |
607 | ||
608 | SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) | |
609 | { | |
610 | int ret; | |
611 | uint32_t i1; | |
612 | uint32_t i2[2]; | |
613 | uint16_t state; | |
614 | ||
615 | uint8_t unknown_cmd1[] = { 0xa3, 0x09, 0xc9, 0x8d, 0xe7, 0xad, 0x7a, 0x62, 0xb6, 0xd1, 0xbf }; | |
616 | uint8_t expected_unknown_resp1[] = { 0xa3, 0x10, 0xda, 0x66, 0x6b, 0x93, 0x5c, 0x55, 0x38, 0x50, 0x39, 0x51, 0x98, 0x86, 0x5d, 0x06, 0x7c, 0xea }; | |
617 | uint8_t unknown_resp1[sizeof(expected_unknown_resp1)]; | |
618 | ||
619 | uint8_t unknown_cmd2[] = { 0xa3, 0x01, 0xca }; | |
620 | uint8_t expected_unknown_resp2[] = { 0xa3, 0x08, 0x06, 0x83, 0x96, 0x29, 0x15, 0xe1, 0x92, 0x74, 0x00, 0x00 }; | |
621 | uint8_t unknown_resp2[sizeof(expected_unknown_resp2)]; | |
622 | ||
623 | if ((ret = ctrl_in(sdi, 162, 0x20, 0, &i1, sizeof(i1))) != SR_OK) { | |
624 | sr_err("failed to read i1"); | |
625 | return ret; | |
626 | } | |
627 | sr_dbg("i1: 0x%08x", i1); | |
628 | ||
629 | if ((ret = ctrl_in(sdi, 162, 0x08, 0, &i2, sizeof(i2))) != SR_OK) { | |
630 | sr_err("failed to read i2"); | |
631 | return ret; | |
632 | } | |
633 | sr_dbg("i2: 0x%08x, 0x%08x", i2[0], i2[1]); | |
634 | ||
635 | if ((ret = upload_fpga_bitstream(sdi)) != SR_OK) { | |
636 | sr_err("failed to upload fpga bitstream"); | |
637 | return ret; | |
638 | } | |
639 | ||
640 | run_state(sdi); | |
641 | ||
642 | if ((ret = ctrl_out(sdi, 96, 0x00, 0, unknown_cmd1, sizeof(unknown_cmd1))) != SR_OK) { | |
643 | sr_err("failed to send unknown_cmd1"); | |
644 | return ret; | |
645 | } | |
646 | g_usleep(80 * 1000); | |
647 | if ((ret = ctrl_in(sdi, 96, 0x00, 0, unknown_resp1, sizeof(unknown_resp1))) != SR_OK) { | |
648 | sr_err("failed to read unknown_resp1"); | |
649 | return ret; | |
650 | } | |
651 | if (memcmp(unknown_resp1, expected_unknown_resp1, sizeof(unknown_resp1))) | |
652 | sr_dbg("unknown_cmd1 response is not as expected!"); | |
653 | ||
654 | state = run_state(sdi); | |
655 | if (state != 0x85e9) | |
656 | sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state); | |
657 | ||
658 | if ((ret = ctrl_out(sdi, 96, 0x00, 0, unknown_cmd2, sizeof(unknown_cmd2))) != SR_OK) { | |
659 | sr_err("failed to send unknown_cmd2"); | |
660 | return ret; | |
661 | } | |
662 | g_usleep(80 * 1000); | |
663 | if ((ret = ctrl_in(sdi, 96, 0x00, 0, unknown_resp2, sizeof(unknown_resp2))) != SR_OK) { | |
664 | sr_err("failed to read unknown_resp2"); | |
665 | return ret; | |
666 | } | |
667 | if (memcmp(unknown_resp2, expected_unknown_resp2, sizeof(unknown_resp2))) | |
668 | sr_dbg("unknown_cmd2 response is not as expected!"); | |
669 | ||
670 | if ((ret = ctrl_out(sdi, 56, 0x00, 0, NULL, 0)) != SR_OK) { | |
671 | sr_err("failed to send unknown_cmd3"); | |
672 | return ret; | |
673 | } | |
674 | sr_dbg("device should be initialized"); | |
675 | ||
676 | return set_defaults(sdi); | |
677 | } | |
678 | ||
679 | SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi) | |
680 | { | |
681 | int ret; | |
682 | ||
683 | if ((ret = ctrl_out(sdi, 16, 0x00, 0, NULL, 0)) != SR_OK) { | |
684 | sr_err("failed to send deinit command"); | |
685 | return ret; | |
686 | } | |
687 | ||
688 | return SR_OK; | |
689 | } |