[libsigrok.git] / src / hardware / fx2lafw / dslogic.h

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H
#define LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H

/* Modified protocol commands & flags used by DSLogic */
#define DS_CMD_GET_FW_VERSION		0xb0
#define DS_CMD_GET_REVID_VERSION	0xb1
#define DS_CMD_START			0xb2
#define DS_CMD_CONFIG			0xb3
#define DS_CMD_SETTING			0xb4
#define DS_CMD_CONTROL			0xb5
#define DS_CMD_STATUS			0xb6
#define DS_CMD_STATUS_INFO		0xb7
#define DS_CMD_WR_REG			0xb8
#define DS_CMD_WR_NVM			0xb9
#define DS_CMD_RD_NVM			0xba
#define DS_CMD_RD_NVM_PRE		0xbb
#define DS_CMD_GET_HW_INFO		0xbc

#define DS_NUM_TRIGGER_STAGES		16
#define DS_START_FLAGS_STOP		(1 << 7)
#define DS_START_FLAGS_CLK_48MHZ	(1 << 6)
#define DS_START_FLAGS_SAMPLE_WIDE	(1 << 5)
#define DS_START_FLAGS_MODE_LA		(1 << 4)

#define DS_ADDR_COMB			0x68
#define DS_ADDR_EEWP			0x70
#define DS_ADDR_VTH			0x78

#define DS_MAX_LOGIC_DEPTH		SR_MHZ(16)
#define DS_MAX_LOGIC_SAMPLERATE		SR_MHZ(100)

enum dslogic_operation_modes {
	DS_OP_NORMAL,
	DS_OP_INTERNAL_TEST,
	DS_OP_EXTERNAL_TEST,
	DS_OP_LOOPBACK_TEST,
};

enum {
	DS_VOLTAGE_RANGE_18_33_V,	/* 1.8V and 3.3V logic */
	DS_VOLTAGE_RANGE_5_V,		/* 5V logic */
};

enum {
	DS_EDGE_RISING,
	DS_EDGE_FALLING,
};

struct dslogic_version {
	uint8_t major;
	uint8_t minor;
};

struct dslogic_mode {
	uint8_t flags;
	uint8_t sample_delay_h;
	uint8_t sample_delay_l;
};

struct dslogic_trigger_pos {
	uint32_t real_pos;
	uint32_t ram_saddr;
	uint32_t remain_cnt;
	uint8_t first_block[500];
};

/*
 * The FPGA is configured with TLV tuples. Length is specified as the
 * number of 16-bit words, and the (type, length) header is in some
 * cases padded with 0xffff.
 */
#define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt)
#define _DS_CFG_PAD(variable, wordcnt) ((_DS_CFG(variable, wordcnt) << 16) | 0xffff)
#define DS_CFG_START		0xf5a5f5a5
#define DS_CFG_MODE		_DS_CFG(0, 1)
#define DS_CFG_DIVIDER		_DS_CFG_PAD(1, 2)
#define DS_CFG_COUNT		_DS_CFG_PAD(3, 2)
#define DS_CFG_TRIG_POS		_DS_CFG_PAD(5, 2)
#define DS_CFG_TRIG_GLB		_DS_CFG(7, 1)
#define DS_CFG_TRIG_ADP		_DS_CFG_PAD(10, 2)
#define DS_CFG_TRIG_SDA		_DS_CFG_PAD(12, 2)
#define DS_CFG_TRIG_MASK0	_DS_CFG_PAD(16, 16)
#define DS_CFG_TRIG_MASK1	_DS_CFG_PAD(17, 16)
#define DS_CFG_TRIG_VALUE0	_DS_CFG_PAD(20, 16)
#define DS_CFG_TRIG_VALUE1	_DS_CFG_PAD(21, 16)
#define DS_CFG_TRIG_EDGE0	_DS_CFG_PAD(24, 16)
#define DS_CFG_TRIG_EDGE1	_DS_CFG_PAD(25, 16)
#define DS_CFG_TRIG_COUNT0	_DS_CFG_PAD(28, 16)
#define DS_CFG_TRIG_COUNT1	_DS_CFG_PAD(29, 16)
#define DS_CFG_TRIG_LOGIC0	_DS_CFG_PAD(32, 16)
#define DS_CFG_TRIG_LOGIC1	_DS_CFG_PAD(33, 16)
#define DS_CFG_END		0xfa5afa5a

struct dslogic_fpga_config {
	uint32_t sync;
	uint16_t mode_header;
	uint16_t mode;
	uint32_t divider_header;
	uint32_t divider;
	uint32_t count_header;
	uint32_t count;
	uint32_t trig_pos_header;
	uint32_t trig_pos;
	uint16_t trig_glb_header;
	uint16_t trig_glb;
	uint32_t trig_adp_header;
	uint32_t trig_adp;
	uint32_t trig_sda_header;
	uint32_t trig_sda;
	uint32_t trig_mask0_header;
	uint16_t trig_mask0[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_mask1_header;
	uint16_t trig_mask1[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_value0_header;
	uint16_t trig_value0[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_value1_header;
	uint16_t trig_value1[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_edge0_header;
	uint16_t trig_edge0[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_edge1_header;
	uint16_t trig_edge1[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_count0_header;
	uint16_t trig_count0[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_count1_header;
	uint16_t trig_count1[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_logic0_header;
	uint16_t trig_logic0[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_logic1_header;
	uint16_t trig_logic1[DS_NUM_TRIGGER_STAGES];
	uint32_t end_sync;
};

SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
		const char *name);
SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth);
SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc);

#endif
Commit	Line	Data
b9d53092 BV	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation, either version 3 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
6fcf3f0a	21	#ifndef LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H
	22	#define LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H
	23
b9d53092 BV	24	/* Modified protocol commands & flags used by DSLogic */
	25	#define DS_CMD_GET_FW_VERSION 0xb0
	26	#define DS_CMD_GET_REVID_VERSION 0xb1
6fcf3f0a	27	#define DS_CMD_START 0xb2
9d71f815 JH	28	#define DS_CMD_CONFIG 0xb3
	29	#define DS_CMD_SETTING 0xb4
	30	#define DS_CMD_CONTROL 0xb5
	31	#define DS_CMD_STATUS 0xb6
	32	#define DS_CMD_STATUS_INFO 0xb7
	33	#define DS_CMD_WR_REG 0xb8
	34	#define DS_CMD_WR_NVM 0xb9
	35	#define DS_CMD_RD_NVM 0xba
	36	#define DS_CMD_RD_NVM_PRE 0xbb
	37	#define DS_CMD_GET_HW_INFO 0xbc
b9d53092	38
6fcf3f0a	39	#define DS_NUM_TRIGGER_STAGES 16
	40	#define DS_START_FLAGS_STOP (1 << 7)
	41	#define DS_START_FLAGS_CLK_48MHZ (1 << 6)
	42	#define DS_START_FLAGS_SAMPLE_WIDE (1 << 5)
62974b23	43	#define DS_START_FLAGS_MODE_LA (1 << 4)
b9d53092	44
ac0facf4 JH	45	#define DS_ADDR_COMB 0x68
	46	#define DS_ADDR_EEWP 0x70
	47	#define DS_ADDR_VTH 0x78
	48
9803346f UH	49	#define DS_MAX_LOGIC_DEPTH SR_MHZ(16)
9803346f UH	50	#define DS_MAX_LOGIC_SAMPLERATE SR_MHZ(100)
a9a9bfaa	51
b9d53092 BV	52	enum dslogic_operation_modes {
	53	DS_OP_NORMAL,
	54	DS_OP_INTERNAL_TEST,
	55	DS_OP_EXTERNAL_TEST,
	56	DS_OP_LOOPBACK_TEST,
	57	};
	58
9803346f UH	59	enum {
	60	DS_VOLTAGE_RANGE_18_33_V, /* 1.8V and 3.3V logic */
	61	DS_VOLTAGE_RANGE_5_V, /* 5V logic */
3fc3fbe4 DA	62	};
3fc3fbe4 DA	63
9803346f	64	enum {
d9a58763	65	DS_EDGE_RISING,
9803346f	66	DS_EDGE_FALLING,
d9a58763 DA	67	};
d9a58763 DA	68
b9d53092 BV	69	struct dslogic_version {
	70	uint8_t major;
	71	uint8_t minor;
	72	};
	73
	74	struct dslogic_mode {
	75	uint8_t flags;
	76	uint8_t sample_delay_h;
	77	uint8_t sample_delay_l;
	78	};
	79
	80	struct dslogic_trigger_pos {
	81	uint32_t real_pos;
	82	uint32_t ram_saddr;
4237fbca DA	83	uint32_t remain_cnt;
4237fbca DA	84	uint8_t first_block[500];
b9d53092 BV	85	};
	86
	87	/*
	88	* The FPGA is configured with TLV tuples. Length is specified as the
	89	* number of 16-bit words, and the (type, length) header is in some
	90	* cases padded with 0xffff.
	91	*/
	92	#define _DS_CFG(variable, wordcnt) ((variable << 8) \| wordcnt)
	93	#define _DS_CFG_PAD(variable, wordcnt) ((_DS_CFG(variable, wordcnt) << 16) \| 0xffff)
3f0ff412	94	#define DS_CFG_START 0xf5a5f5a5
6fcf3f0a	95	#define DS_CFG_MODE _DS_CFG(0, 1)
b9d53092 BV	96	#define DS_CFG_DIVIDER _DS_CFG_PAD(1, 2)
	97	#define DS_CFG_COUNT _DS_CFG_PAD(3, 2)
	98	#define DS_CFG_TRIG_POS _DS_CFG_PAD(5, 2)
	99	#define DS_CFG_TRIG_GLB _DS_CFG(7, 1)
	100	#define DS_CFG_TRIG_ADP _DS_CFG_PAD(10, 2)
	101	#define DS_CFG_TRIG_SDA _DS_CFG_PAD(12, 2)
	102	#define DS_CFG_TRIG_MASK0 _DS_CFG_PAD(16, 16)
	103	#define DS_CFG_TRIG_MASK1 _DS_CFG_PAD(17, 16)
	104	#define DS_CFG_TRIG_VALUE0 _DS_CFG_PAD(20, 16)
	105	#define DS_CFG_TRIG_VALUE1 _DS_CFG_PAD(21, 16)
	106	#define DS_CFG_TRIG_EDGE0 _DS_CFG_PAD(24, 16)
	107	#define DS_CFG_TRIG_EDGE1 _DS_CFG_PAD(25, 16)
	108	#define DS_CFG_TRIG_COUNT0 _DS_CFG_PAD(28, 16)
	109	#define DS_CFG_TRIG_COUNT1 _DS_CFG_PAD(29, 16)
	110	#define DS_CFG_TRIG_LOGIC0 _DS_CFG_PAD(32, 16)
	111	#define DS_CFG_TRIG_LOGIC1 _DS_CFG_PAD(33, 16)
3f0ff412	112	#define DS_CFG_END 0xfa5afa5a
b9d53092 BV	113
	114	struct dslogic_fpga_config {
	115	uint32_t sync;
	116	uint16_t mode_header;
	117	uint16_t mode;
	118	uint32_t divider_header;
	119	uint32_t divider;
	120	uint32_t count_header;
	121	uint32_t count;
	122	uint32_t trig_pos_header;
	123	uint32_t trig_pos;
	124	uint16_t trig_glb_header;
	125	uint16_t trig_glb;
	126	uint32_t trig_adp_header;
	127	uint32_t trig_adp;
	128	uint32_t trig_sda_header;
	129	uint32_t trig_sda;
	130	uint32_t trig_mask0_header;
	131	uint16_t trig_mask0[DS_NUM_TRIGGER_STAGES];
	132	uint32_t trig_mask1_header;
	133	uint16_t trig_mask1[DS_NUM_TRIGGER_STAGES];
	134	uint32_t trig_value0_header;
	135	uint16_t trig_value0[DS_NUM_TRIGGER_STAGES];
	136	uint32_t trig_value1_header;
	137	uint16_t trig_value1[DS_NUM_TRIGGER_STAGES];
	138	uint32_t trig_edge0_header;
	139	uint16_t trig_edge0[DS_NUM_TRIGGER_STAGES];
	140	uint32_t trig_edge1_header;
	141	uint16_t trig_edge1[DS_NUM_TRIGGER_STAGES];
	142	uint32_t trig_count0_header;
	143	uint16_t trig_count0[DS_NUM_TRIGGER_STAGES];
	144	uint32_t trig_count1_header;
	145	uint16_t trig_count1[DS_NUM_TRIGGER_STAGES];
	146	uint32_t trig_logic0_header;
	147	uint16_t trig_logic0[DS_NUM_TRIGGER_STAGES];
	148	uint32_t trig_logic1_header;
	149	uint16_t trig_logic1[DS_NUM_TRIGGER_STAGES];
	150	uint32_t end_sync;
	151	};
	152
8e2d6c9d DE	153	SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
	154	const char *name);
	155	SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
	156	SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
	157	SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
3fc3fbe4	158	SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth);
9803346f	159	SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc);
6fcf3f0a	160
6fcf3f0a	161	#endif