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b9d53092 BV |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
5 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation, either version 3 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
6ec6c43b | 21 | #include <config.h> |
b9d53092 BV |
22 | #include <math.h> |
23 | #include <glib.h> | |
24 | #include <glib/gstdio.h> | |
25 | #include "protocol.h" | |
26 | #include "dslogic.h" | |
27 | ||
3f0ff412 DA |
28 | /* |
29 | * This should be larger than the FPGA bitstream image so that it'll get | |
30 | * uploaded in one big operation. There seem to be issues when uploading | |
31 | * it in chunks. | |
32 | */ | |
33 | #define FW_BUFSIZE (1024 * 1024) | |
1a46cc62 | 34 | |
4df5739a UH |
35 | #define FPGA_UPLOAD_DELAY (10 * 1000) |
36 | ||
37 | #define USB_TIMEOUT (3 * 1000) | |
38 | ||
3fc3fbe4 DA |
39 | SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth) |
40 | { | |
41 | struct sr_usb_dev_inst *usb; | |
3fc3fbe4 | 42 | int ret; |
c2f35321 JH |
43 | const uint8_t value = (vth / 5.0) * 255; |
44 | const uint16_t cmd = value | (DS_ADDR_VTH << 8); | |
3fc3fbe4 | 45 | |
9803346f UH |
46 | usb = sdi->conn; |
47 | ||
3fc3fbe4 | 48 | /* Send the control command. */ |
c2f35321 JH |
49 | ret = libusb_control_transfer(usb->devhdl, |
50 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, | |
51 | DS_CMD_WR_REG, 0x0000, 0x0000, | |
9803346f | 52 | (unsigned char *)&cmd, sizeof(cmd), 3000); |
3fc3fbe4 DA |
53 | if (ret < 0) { |
54 | sr_err("Unable to send VTH command: %s.", | |
55 | libusb_error_name(ret)); | |
56 | return SR_ERR; | |
57 | } | |
58 | ||
59 | return SR_OK; | |
60 | } | |
61 | ||
8e2d6c9d DE |
62 | SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi, |
63 | const char *name) | |
b9d53092 | 64 | { |
8e2d6c9d DE |
65 | uint64_t sum; |
66 | struct sr_resource bitstream; | |
67 | struct drv_context *drvc; | |
b9d53092 | 68 | struct sr_usb_dev_inst *usb; |
b9d53092 | 69 | unsigned char *buf; |
8e2d6c9d DE |
70 | ssize_t chunksize; |
71 | int transferred; | |
72 | int result, ret; | |
cd189a44 | 73 | const uint8_t cmd[3] = {0, 0, 0}; |
b9d53092 | 74 | |
8e2d6c9d | 75 | drvc = sdi->driver->context; |
b9d53092 | 76 | usb = sdi->conn; |
8e2d6c9d DE |
77 | |
78 | sr_dbg("Uploading FPGA firmware '%s'.", name); | |
79 | ||
80 | result = sr_resource_open(drvc->sr_ctx, &bitstream, | |
81 | SR_RESOURCE_FIRMWARE, name); | |
82 | if (result != SR_OK) | |
83 | return result; | |
b9d53092 BV |
84 | |
85 | /* Tell the device firmware is coming. */ | |
86 | if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | | |
9d71f815 | 87 | LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000, |
d93c1470 | 88 | (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) { |
b9d53092 | 89 | sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret)); |
8e2d6c9d | 90 | sr_resource_close(drvc->sr_ctx, &bitstream); |
b9d53092 BV |
91 | return SR_ERR; |
92 | } | |
93 | ||
94 | /* Give the FX2 time to get ready for FPGA firmware upload. */ | |
4df5739a | 95 | g_usleep(FPGA_UPLOAD_DELAY); |
b9d53092 | 96 | |
8e2d6c9d | 97 | buf = g_malloc(FW_BUFSIZE); |
b9d53092 BV |
98 | sum = 0; |
99 | result = SR_OK; | |
100 | while (1) { | |
8e2d6c9d DE |
101 | chunksize = sr_resource_read(drvc->sr_ctx, &bitstream, |
102 | buf, FW_BUFSIZE); | |
103 | if (chunksize < 0) | |
104 | result = SR_ERR; | |
105 | if (chunksize <= 0) | |
b9d53092 BV |
106 | break; |
107 | ||
108 | if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT, | |
4df5739a | 109 | buf, chunksize, &transferred, USB_TIMEOUT)) < 0) { |
b9d53092 BV |
110 | sr_err("Unable to configure FPGA firmware: %s.", |
111 | libusb_error_name(ret)); | |
112 | result = SR_ERR; | |
113 | break; | |
114 | } | |
115 | sum += transferred; | |
8e2d6c9d DE |
116 | sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.", |
117 | sum, bitstream.size); | |
b9d53092 BV |
118 | |
119 | if (transferred != chunksize) { | |
120 | sr_err("Short transfer while uploading FPGA firmware."); | |
121 | result = SR_ERR; | |
122 | break; | |
123 | } | |
124 | } | |
b9d53092 | 125 | g_free(buf); |
8e2d6c9d DE |
126 | sr_resource_close(drvc->sr_ctx, &bitstream); |
127 | ||
b9d53092 BV |
128 | if (result == SR_OK) |
129 | sr_dbg("FPGA firmware upload done."); | |
130 | ||
131 | return result; | |
132 | } | |
133 | ||
8e2d6c9d | 134 | SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi) |
b9d53092 BV |
135 | { |
136 | struct dev_context *devc; | |
137 | struct sr_usb_dev_inst *usb; | |
138 | struct dslogic_mode mode; | |
139 | int ret; | |
140 | ||
141 | devc = sdi->priv; | |
62974b23 | 142 | mode.flags = DS_START_FLAGS_MODE_LA; |
b9d53092 BV |
143 | mode.sample_delay_h = mode.sample_delay_l = 0; |
144 | if (devc->sample_wide) | |
145 | mode.flags |= DS_START_FLAGS_SAMPLE_WIDE; | |
146 | ||
147 | usb = sdi->conn; | |
148 | ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | | |
149 | LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000, | |
4df5739a | 150 | (unsigned char *)&mode, sizeof(mode), USB_TIMEOUT); |
b9d53092 BV |
151 | if (ret < 0) { |
152 | sr_err("Failed to send start command: %s.", libusb_error_name(ret)); | |
153 | return SR_ERR; | |
154 | } | |
155 | ||
156 | return SR_OK; | |
157 | } | |
158 | ||
8e2d6c9d | 159 | SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi) |
b9d53092 BV |
160 | { |
161 | struct sr_usb_dev_inst *usb; | |
162 | struct dslogic_mode mode; | |
163 | int ret; | |
164 | ||
165 | mode.flags = DS_START_FLAGS_STOP; | |
166 | mode.sample_delay_h = mode.sample_delay_l = 0; | |
167 | ||
168 | usb = sdi->conn; | |
169 | ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | | |
170 | LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000, | |
4df5739a | 171 | (unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT); |
b9d53092 BV |
172 | if (ret < 0) { |
173 | sr_err("Failed to send stop command: %s.", libusb_error_name(ret)); | |
174 | return SR_ERR; | |
175 | } | |
176 | ||
177 | return SR_OK; | |
178 | } | |
179 | ||
3db03efa DA |
180 | /* |
181 | * Get the session trigger and configure the FPGA structure | |
182 | * accordingly. | |
183 | */ | |
184 | static int dslogic_set_trigger(const struct sr_dev_inst *sdi, | |
185 | struct dslogic_fpga_config *cfg) | |
186 | { | |
187 | struct sr_trigger *trigger; | |
188 | struct sr_trigger_stage *stage; | |
189 | struct sr_trigger_match *match; | |
190 | struct dev_context *devc; | |
191 | const GSList *l, *m; | |
192 | int channelbit, i = 0; | |
193 | uint16_t v16; | |
194 | ||
9803346f UH |
195 | devc = sdi->priv; |
196 | ||
3db03efa DA |
197 | cfg->trig_mask0[0] = 0xffff; |
198 | cfg->trig_mask1[0] = 0xffff; | |
199 | ||
200 | cfg->trig_value0[0] = 0; | |
201 | cfg->trig_value1[0] = 0; | |
202 | ||
203 | cfg->trig_edge0[0] = 0; | |
204 | cfg->trig_edge1[0] = 0; | |
205 | ||
206 | cfg->trig_logic0[0] = 0; | |
207 | cfg->trig_logic1[0] = 0; | |
208 | ||
209 | cfg->trig_count0[0] = 0; | |
210 | cfg->trig_count1[0] = 0; | |
211 | ||
4237fbca DA |
212 | cfg->trig_pos = 0; |
213 | cfg->trig_sda = 0; | |
214 | cfg->trig_glb = 0; | |
215 | cfg->trig_adp = cfg->count - cfg->trig_pos - 1; | |
216 | ||
217 | for (i = 1; i < 16; i++) { | |
218 | cfg->trig_mask0[i] = 0xff; | |
219 | cfg->trig_mask1[i] = 0xff; | |
220 | cfg->trig_value0[i] = 0; | |
221 | cfg->trig_value1[i] = 0; | |
222 | cfg->trig_edge0[i] = 0; | |
223 | cfg->trig_edge1[i] = 0; | |
224 | cfg->trig_count0[i] = 0; | |
225 | cfg->trig_count1[i] = 0; | |
226 | cfg->trig_logic0[i] = 2; | |
227 | cfg->trig_logic1[i] = 2; | |
228 | } | |
229 | ||
230 | cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples); | |
231 | sr_dbg("pos: %d", cfg->trig_pos); | |
232 | ||
233 | sr_dbg("configuring trigger"); | |
234 | ||
9803346f | 235 | if (!(trigger = sr_session_trigger_get(sdi->session))) { |
4237fbca | 236 | sr_dbg("No session trigger found"); |
3db03efa | 237 | return SR_OK; |
4237fbca | 238 | } |
3db03efa DA |
239 | |
240 | for (l = trigger->stages; l; l = l->next) { | |
241 | stage = l->data; | |
242 | for (m = stage->matches; m; m = m->next) { | |
243 | match = m->data; | |
244 | if (!match->channel->enabled) | |
245 | /* Ignore disabled channels with a trigger. */ | |
246 | continue; | |
247 | channelbit = 1 << (match->channel->index); | |
3db03efa DA |
248 | /* Simple trigger support (event). */ |
249 | if (match->match == SR_TRIGGER_ONE) { | |
250 | cfg->trig_mask0[0] &= ~channelbit; | |
251 | cfg->trig_mask1[0] &= ~channelbit; | |
252 | cfg->trig_value0[0] |= channelbit; | |
253 | cfg->trig_value1[0] |= channelbit; | |
254 | } else if (match->match == SR_TRIGGER_ZERO) { | |
255 | cfg->trig_mask0[0] &= ~channelbit; | |
256 | cfg->trig_mask1[0] &= ~channelbit; | |
257 | } else if (match->match == SR_TRIGGER_FALLING) { | |
258 | cfg->trig_mask0[0] &= ~channelbit; | |
259 | cfg->trig_mask1[0] &= ~channelbit; | |
260 | cfg->trig_edge0[0] |= channelbit; | |
261 | cfg->trig_edge1[0] |= channelbit; | |
262 | } else if (match->match == SR_TRIGGER_RISING) { | |
263 | cfg->trig_mask0[0] &= ~channelbit; | |
264 | cfg->trig_mask1[0] &= ~channelbit; | |
265 | cfg->trig_value0[0] |= channelbit; | |
266 | cfg->trig_value1[0] |= channelbit; | |
267 | cfg->trig_edge0[0] |= channelbit; | |
268 | cfg->trig_edge1[0] |= channelbit; | |
9803346f | 269 | } else if (match->match == SR_TRIGGER_EDGE) { |
3db03efa DA |
270 | cfg->trig_edge0[0] |= channelbit; |
271 | cfg->trig_edge1[0] |= channelbit; | |
272 | } | |
273 | } | |
274 | } | |
9803346f | 275 | |
4237fbca DA |
276 | v16 = RL16(&cfg->mode); |
277 | v16 |= 1 << 0; | |
278 | WL16(&cfg->mode, v16); | |
9803346f | 279 | |
3db03efa DA |
280 | return SR_OK; |
281 | } | |
282 | ||
8e2d6c9d | 283 | SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi) |
b9d53092 BV |
284 | { |
285 | struct dev_context *devc; | |
286 | struct sr_usb_dev_inst *usb; | |
287 | uint8_t c[3]; | |
288 | struct dslogic_fpga_config cfg; | |
289 | uint16_t v16; | |
290 | uint32_t v32; | |
291 | int transferred, len, ret; | |
292 | ||
293 | sr_dbg("Configuring FPGA."); | |
9803346f | 294 | |
b9d53092 BV |
295 | usb = sdi->conn; |
296 | devc = sdi->priv; | |
297 | ||
298 | WL32(&cfg.sync, DS_CFG_START); | |
299 | WL16(&cfg.mode_header, DS_CFG_MODE); | |
300 | WL32(&cfg.divider_header, DS_CFG_DIVIDER); | |
301 | WL32(&cfg.count_header, DS_CFG_COUNT); | |
302 | WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS); | |
303 | WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB); | |
304 | WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP); | |
305 | WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA); | |
306 | WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0); | |
307 | WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1); | |
308 | WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0); | |
309 | WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1); | |
310 | WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0); | |
311 | WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1); | |
312 | WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0); | |
313 | WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1); | |
314 | WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0); | |
315 | WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1); | |
316 | WL32(&cfg.end_sync, DS_CFG_END); | |
317 | ||
318 | /* Pass in the length of a fixed-size struct. Really. */ | |
319 | len = sizeof(struct dslogic_fpga_config) / 2; | |
320 | c[0] = len & 0xff; | |
321 | c[1] = (len >> 8) & 0xff; | |
322 | c[2] = (len >> 16) & 0xff; | |
323 | ||
324 | ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | | |
325 | LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000, | |
4df5739a | 326 | c, 3, USB_TIMEOUT); |
b9d53092 | 327 | if (ret < 0) { |
9803346f UH |
328 | sr_err("Failed to send FPGA configure command: %s.", |
329 | libusb_error_name(ret)); | |
b9d53092 BV |
330 | return SR_ERR; |
331 | } | |
332 | ||
333 | /* | |
334 | * 15 1 = internal test mode | |
335 | * 14 1 = external test mode | |
336 | * 13 1 = loopback test mode | |
3db03efa DA |
337 | * 12 1 = stream mode |
338 | * 11 1 = serial trigger | |
41dc2547 | 339 | * 8-10 unused |
b9d53092 BV |
340 | * 7 1 = analog mode |
341 | * 6 1 = samplerate 400MHz | |
342 | * 5 1 = samplerate 200MHz or analog mode | |
343 | * 4 0 = logic, 1 = dso or analog | |
a9a9bfaa | 344 | * 3 1 = RLE encoding (enable for more than 16 Megasamples) |
9803346f UH |
345 | * 1-2 00 = internal clock, |
346 | * 01 = external clock rising, | |
347 | * 11 = external clock falling | |
b9d53092 BV |
348 | * 0 1 = trigger enabled |
349 | */ | |
350 | v16 = 0x0000; | |
351 | if (devc->dslogic_mode == DS_OP_INTERNAL_TEST) | |
352 | v16 = 1 << 15; | |
353 | else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST) | |
354 | v16 = 1 << 14; | |
355 | else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST) | |
356 | v16 = 1 << 13; | |
41dc2547 DA |
357 | if (devc->dslogic_continuous_mode) |
358 | v16 |= 1 << 12; | |
9803346f | 359 | if (devc->dslogic_external_clock) { |
4237fbca | 360 | v16 |= 1 << 1; |
9803346f | 361 | if (devc->dslogic_clock_edge == DS_EDGE_FALLING) |
d9a58763 | 362 | v16 |= 1 << 2; |
d9a58763 | 363 | } |
9803346f | 364 | if (devc->limit_samples > DS_MAX_LOGIC_DEPTH * |
176d785d | 365 | ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE) |
9803346f UH |
366 | && !devc->dslogic_continuous_mode) { |
367 | /* Enable RLE for long captures. | |
368 | * Without this, captured data present errors. | |
369 | */ | |
370 | v16 |= 1 << 3; | |
a9a9bfaa | 371 | } |
3fc3fbe4 | 372 | |
b9d53092 | 373 | WL16(&cfg.mode, v16); |
a04b28ce | 374 | v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate); |
b9d53092 BV |
375 | WL32(&cfg.divider, v32); |
376 | WL32(&cfg.count, devc->limit_samples); | |
377 | ||
3db03efa DA |
378 | dslogic_set_trigger(sdi, &cfg); |
379 | ||
b9d53092 BV |
380 | len = sizeof(struct dslogic_fpga_config); |
381 | ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT, | |
4df5739a | 382 | (unsigned char *)&cfg, len, &transferred, USB_TIMEOUT); |
b9d53092 BV |
383 | if (ret < 0 || transferred != len) { |
384 | sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret)); | |
385 | return SR_ERR; | |
386 | } | |
387 | ||
388 | return SR_OK; | |
389 | } | |
a04b28ce | 390 | |
9803346f UH |
391 | static int to_bytes_per_ms(struct dev_context *devc) |
392 | { | |
a04b28ce | 393 | if (devc->cur_samplerate > SR_MHZ(100)) |
9803346f UH |
394 | return SR_MHZ(100) / 1000 * (devc->sample_wide ? 2 : 1); |
395 | ||
396 | return devc->cur_samplerate / 1000 * (devc->sample_wide ? 2 : 1); | |
a04b28ce DA |
397 | } |
398 | ||
399 | static size_t get_buffer_size(struct dev_context *devc) | |
400 | { | |
9803346f UH |
401 | size_t s; |
402 | ||
403 | /* | |
404 | * The buffer should be large enough to hold 10ms of data and | |
405 | * a multiple of 512. | |
406 | */ | |
407 | s = 10 * to_bytes_per_ms(devc); | |
408 | // s = to_bytes_per_ms(devc->cur_samplerate); | |
409 | return (s + 511) & ~511; | |
a04b28ce DA |
410 | } |
411 | ||
9803346f UH |
412 | SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc) |
413 | { | |
a04b28ce | 414 | unsigned int n; |
9803346f | 415 | |
a04b28ce | 416 | /* Total buffer size should be able to hold about 100ms of data. */ |
9803346f | 417 | n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc)); |
a04b28ce DA |
418 | sr_info("New calculation: %d", n); |
419 | ||
420 | if (n > NUM_SIMUL_TRANSFERS) | |
421 | return NUM_SIMUL_TRANSFERS; | |
422 | ||
423 | return n; | |
424 | } |