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b9d53092 BV |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
5 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation, either version 3 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
6ec6c43b | 21 | #include <config.h> |
b9d53092 BV |
22 | #include <math.h> |
23 | #include <glib.h> | |
24 | #include <glib/gstdio.h> | |
25 | #include "protocol.h" | |
26 | #include "dslogic.h" | |
27 | ||
3f0ff412 DA |
28 | /* |
29 | * This should be larger than the FPGA bitstream image so that it'll get | |
30 | * uploaded in one big operation. There seem to be issues when uploading | |
31 | * it in chunks. | |
32 | */ | |
33 | #define FW_BUFSIZE (1024 * 1024) | |
1a46cc62 | 34 | |
4df5739a UH |
35 | #define FPGA_UPLOAD_DELAY (10 * 1000) |
36 | ||
37 | #define USB_TIMEOUT (3 * 1000) | |
38 | ||
8e2d6c9d DE |
39 | SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi, |
40 | const char *name) | |
b9d53092 | 41 | { |
8e2d6c9d DE |
42 | uint64_t sum; |
43 | struct sr_resource bitstream; | |
44 | struct drv_context *drvc; | |
b9d53092 | 45 | struct sr_usb_dev_inst *usb; |
b9d53092 | 46 | unsigned char *buf; |
8e2d6c9d DE |
47 | ssize_t chunksize; |
48 | int transferred; | |
49 | int result, ret; | |
d93c1470 | 50 | uint8_t cmd[3]; |
b9d53092 | 51 | |
8e2d6c9d | 52 | drvc = sdi->driver->context; |
b9d53092 | 53 | usb = sdi->conn; |
8e2d6c9d DE |
54 | |
55 | sr_dbg("Uploading FPGA firmware '%s'.", name); | |
56 | ||
57 | result = sr_resource_open(drvc->sr_ctx, &bitstream, | |
58 | SR_RESOURCE_FIRMWARE, name); | |
59 | if (result != SR_OK) | |
60 | return result; | |
b9d53092 BV |
61 | |
62 | /* Tell the device firmware is coming. */ | |
d93c1470 | 63 | memset(cmd, 0, sizeof(cmd)); |
b9d53092 BV |
64 | if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | |
65 | LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000, | |
d93c1470 | 66 | (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) { |
b9d53092 | 67 | sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret)); |
8e2d6c9d | 68 | sr_resource_close(drvc->sr_ctx, &bitstream); |
b9d53092 BV |
69 | return SR_ERR; |
70 | } | |
71 | ||
72 | /* Give the FX2 time to get ready for FPGA firmware upload. */ | |
4df5739a | 73 | g_usleep(FPGA_UPLOAD_DELAY); |
b9d53092 | 74 | |
8e2d6c9d | 75 | buf = g_malloc(FW_BUFSIZE); |
b9d53092 BV |
76 | sum = 0; |
77 | result = SR_OK; | |
78 | while (1) { | |
8e2d6c9d DE |
79 | chunksize = sr_resource_read(drvc->sr_ctx, &bitstream, |
80 | buf, FW_BUFSIZE); | |
81 | if (chunksize < 0) | |
82 | result = SR_ERR; | |
83 | if (chunksize <= 0) | |
b9d53092 BV |
84 | break; |
85 | ||
86 | if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT, | |
4df5739a | 87 | buf, chunksize, &transferred, USB_TIMEOUT)) < 0) { |
b9d53092 BV |
88 | sr_err("Unable to configure FPGA firmware: %s.", |
89 | libusb_error_name(ret)); | |
90 | result = SR_ERR; | |
91 | break; | |
92 | } | |
93 | sum += transferred; | |
8e2d6c9d DE |
94 | sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.", |
95 | sum, bitstream.size); | |
b9d53092 BV |
96 | |
97 | if (transferred != chunksize) { | |
98 | sr_err("Short transfer while uploading FPGA firmware."); | |
99 | result = SR_ERR; | |
100 | break; | |
101 | } | |
102 | } | |
b9d53092 | 103 | g_free(buf); |
8e2d6c9d DE |
104 | sr_resource_close(drvc->sr_ctx, &bitstream); |
105 | ||
b9d53092 BV |
106 | if (result == SR_OK) |
107 | sr_dbg("FPGA firmware upload done."); | |
108 | ||
109 | return result; | |
110 | } | |
111 | ||
8e2d6c9d | 112 | SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi) |
b9d53092 BV |
113 | { |
114 | struct dev_context *devc; | |
115 | struct sr_usb_dev_inst *usb; | |
116 | struct dslogic_mode mode; | |
117 | int ret; | |
118 | ||
119 | devc = sdi->priv; | |
62974b23 | 120 | mode.flags = DS_START_FLAGS_MODE_LA; |
b9d53092 BV |
121 | mode.sample_delay_h = mode.sample_delay_l = 0; |
122 | if (devc->sample_wide) | |
123 | mode.flags |= DS_START_FLAGS_SAMPLE_WIDE; | |
124 | ||
125 | usb = sdi->conn; | |
126 | ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | | |
127 | LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000, | |
4df5739a | 128 | (unsigned char *)&mode, sizeof(mode), USB_TIMEOUT); |
b9d53092 BV |
129 | if (ret < 0) { |
130 | sr_err("Failed to send start command: %s.", libusb_error_name(ret)); | |
131 | return SR_ERR; | |
132 | } | |
133 | ||
134 | return SR_OK; | |
135 | } | |
136 | ||
8e2d6c9d | 137 | SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi) |
b9d53092 BV |
138 | { |
139 | struct sr_usb_dev_inst *usb; | |
140 | struct dslogic_mode mode; | |
141 | int ret; | |
142 | ||
143 | mode.flags = DS_START_FLAGS_STOP; | |
144 | mode.sample_delay_h = mode.sample_delay_l = 0; | |
145 | ||
146 | usb = sdi->conn; | |
147 | ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | | |
148 | LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000, | |
4df5739a | 149 | (unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT); |
b9d53092 BV |
150 | if (ret < 0) { |
151 | sr_err("Failed to send stop command: %s.", libusb_error_name(ret)); | |
152 | return SR_ERR; | |
153 | } | |
154 | ||
155 | return SR_OK; | |
156 | } | |
157 | ||
8e2d6c9d | 158 | SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi) |
b9d53092 BV |
159 | { |
160 | struct dev_context *devc; | |
161 | struct sr_usb_dev_inst *usb; | |
162 | uint8_t c[3]; | |
163 | struct dslogic_fpga_config cfg; | |
164 | uint16_t v16; | |
165 | uint32_t v32; | |
166 | int transferred, len, ret; | |
167 | ||
168 | sr_dbg("Configuring FPGA."); | |
169 | usb = sdi->conn; | |
170 | devc = sdi->priv; | |
171 | ||
172 | WL32(&cfg.sync, DS_CFG_START); | |
173 | WL16(&cfg.mode_header, DS_CFG_MODE); | |
174 | WL32(&cfg.divider_header, DS_CFG_DIVIDER); | |
175 | WL32(&cfg.count_header, DS_CFG_COUNT); | |
176 | WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS); | |
177 | WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB); | |
178 | WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP); | |
179 | WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA); | |
180 | WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0); | |
181 | WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1); | |
182 | WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0); | |
183 | WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1); | |
184 | WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0); | |
185 | WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1); | |
186 | WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0); | |
187 | WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1); | |
188 | WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0); | |
189 | WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1); | |
190 | WL32(&cfg.end_sync, DS_CFG_END); | |
191 | ||
192 | /* Pass in the length of a fixed-size struct. Really. */ | |
193 | len = sizeof(struct dslogic_fpga_config) / 2; | |
194 | c[0] = len & 0xff; | |
195 | c[1] = (len >> 8) & 0xff; | |
196 | c[2] = (len >> 16) & 0xff; | |
197 | ||
198 | ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | | |
199 | LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000, | |
4df5739a | 200 | c, 3, USB_TIMEOUT); |
b9d53092 BV |
201 | if (ret < 0) { |
202 | sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret)); | |
203 | return SR_ERR; | |
204 | } | |
205 | ||
206 | /* | |
207 | * 15 1 = internal test mode | |
208 | * 14 1 = external test mode | |
209 | * 13 1 = loopback test mode | |
210 | * 8-12 unused | |
211 | * 7 1 = analog mode | |
212 | * 6 1 = samplerate 400MHz | |
213 | * 5 1 = samplerate 200MHz or analog mode | |
214 | * 4 0 = logic, 1 = dso or analog | |
215 | * 2-3 unused | |
216 | * 1 0 = internal clock, 1 = external clock | |
217 | * 0 1 = trigger enabled | |
218 | */ | |
219 | v16 = 0x0000; | |
220 | if (devc->dslogic_mode == DS_OP_INTERNAL_TEST) | |
221 | v16 = 1 << 15; | |
222 | else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST) | |
223 | v16 = 1 << 14; | |
224 | else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST) | |
225 | v16 = 1 << 13; | |
226 | if (devc->dslogic_external_clock) | |
227 | v16 |= 1 << 2; | |
228 | WL16(&cfg.mode, v16); | |
229 | ||
230 | v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate); | |
231 | WL32(&cfg.divider, v32); | |
232 | WL32(&cfg.count, devc->limit_samples); | |
233 | ||
234 | len = sizeof(struct dslogic_fpga_config); | |
235 | ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT, | |
4df5739a | 236 | (unsigned char *)&cfg, len, &transferred, USB_TIMEOUT); |
b9d53092 BV |
237 | if (ret < 0 || transferred != len) { |
238 | sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret)); | |
239 | return SR_ERR; | |
240 | } | |
241 | ||
242 | return SR_OK; | |
243 | } |