]>
Commit | Line | Data |
---|---|---|
204b1629 | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
204b1629 | 3 | * |
3ba56876 | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
204b1629 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
3ba56876 | 22 | #ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H |
23 | #define LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H | |
24 | ||
25 | #include <stdint.h> | |
4154a516 | 26 | #include <stdlib.h> |
3ba56876 | 27 | #include <glib.h> |
28 | #include <ftdi.h> | |
29 | #include <string.h> | |
30 | #include <libsigrok/libsigrok.h> | |
31 | #include "libsigrok-internal.h" | |
28a35d8a | 32 | |
f272d7dd UH |
33 | #define LOG_PREFIX "asix-sigma" |
34 | ||
de3f7acb GS |
35 | /* |
36 | * Triggers are not working in this implementation. Stop claiming | |
37 | * support for the feature which effectively is not available, until | |
38 | * the implementation got fixed. Yet keep the code in place and allow | |
39 | * developers to turn on this switch during development. | |
40 | */ | |
41 | #define ASIX_SIGMA_WITH_TRIGGER 0 | |
42 | ||
53a939ab GS |
43 | /* Experimental support for OMEGA (scan only, operation is ENOIMPL). */ |
44 | #define ASIX_WITH_OMEGA 0 | |
45 | ||
46 | #define USB_VENDOR_ASIX 0xa600 | |
47 | #define USB_PRODUCT_SIGMA 0xa000 | |
48 | #define USB_PRODUCT_OMEGA 0xa004 | |
49 | ||
50 | enum asix_device_type { | |
51 | ASIX_TYPE_NONE, | |
52 | ASIX_TYPE_SIGMA, | |
53 | ASIX_TYPE_OMEGA, | |
54 | }; | |
3ba56876 | 55 | |
7c41c420 GS |
56 | /* |
57 | * FPGA commands are 8bits wide. The upper nibble is a command opcode, | |
58 | * the lower nibble can carry operand values. 8bit register addresses | |
59 | * and 8bit data values get communicated in two steps. | |
60 | */ | |
61 | ||
62 | /* Register access. */ | |
63 | #define REG_ADDR_LOW (0x0 << 4) | |
64 | #define REG_ADDR_HIGH (0x1 << 4) | |
65 | #define REG_DATA_LOW (0x2 << 4) | |
66 | #define REG_DATA_HIGH_WRITE (0x3 << 4) | |
67 | #define REG_READ_ADDR (0x4 << 4) | |
68 | #define REG_ADDR_ADJUST (1 << 0) /* Auto adjust register address. */ | |
69 | #define REG_ADDR_DOWN (1 << 1) /* 1 decrement, 0 increment. */ | |
70 | #define REG_ADDR_INC (REG_ADDR_ADJUST) | |
71 | #define REG_ADDR_DEC (REG_ADDR_ADJUST | REG_ADDR_DOWN) | |
72 | ||
73 | /* Sample memory access. */ | |
74 | #define REG_DRAM_WAIT_ACK (0x5 << 4) /* Wait for completion. */ | |
75 | #define REG_DRAM_BLOCK (0x6 << 4) /* DRAM to BRAM, plus bank select. */ | |
76 | #define REG_DRAM_BLOCK_BEGIN (0x8 << 4) /* Read first BRAM bytes. */ | |
77 | #define REG_DRAM_BLOCK_DATA (0xa << 4) /* Read full BRAM block. */ | |
78 | #define REG_DRAM_SEL_N (0x1 << 4) /* Bank select, added to 6/8/a. */ | |
79 | #define REG_DRAM_SEL_BOOL(b) ((b) ? REG_DRAM_SEL_N : 0) | |
80 | ||
81 | /* | |
82 | * Registers at a specific address can have different meanings depending | |
83 | * on whether data is read or written. This is why direction is part of | |
84 | * the programming language identifiers. | |
85 | * | |
86 | * The vendor documentation suggests that in addition to the first 16 | |
87 | * register addresses which implement the logic analyzer's feature set, | |
88 | * there are 240 more registers in the 16 to 255 address range which | |
89 | * are available to applications and plugin features. Can libsigrok's | |
90 | * asix-sigma driver store configuration data there, to avoid expensive | |
91 | * operations (think: firmware re-load). | |
92 | */ | |
93 | ||
fefa1800 | 94 | enum sigma_write_register { |
28a35d8a | 95 | WRITE_CLOCK_SELECT = 0, |
9fb4c632 GS |
96 | WRITE_TRIGGER_SELECT = 1, |
97 | WRITE_TRIGGER_SELECT2 = 2, | |
28a35d8a HE |
98 | WRITE_MODE = 3, |
99 | WRITE_MEMROW = 4, | |
100 | WRITE_POST_TRIGGER = 5, | |
101 | WRITE_TRIGGER_OPTION = 6, | |
102 | WRITE_PIN_VIEW = 7, | |
9fb4c632 | 103 | /* Unassigned register locations. */ |
fefa1800 | 104 | WRITE_TEST = 15, |
28a35d8a HE |
105 | }; |
106 | ||
fefa1800 | 107 | enum sigma_read_register { |
28a35d8a HE |
108 | READ_ID = 0, |
109 | READ_TRIGGER_POS_LOW = 1, | |
110 | READ_TRIGGER_POS_HIGH = 2, | |
111 | READ_TRIGGER_POS_UP = 3, | |
112 | READ_STOP_POS_LOW = 4, | |
113 | READ_STOP_POS_HIGH = 5, | |
114 | READ_STOP_POS_UP = 6, | |
115 | READ_MODE = 7, | |
116 | READ_PIN_CHANGE_LOW = 8, | |
117 | READ_PIN_CHANGE_HIGH = 9, | |
118 | READ_BLOCK_LAST_TS_LOW = 10, | |
119 | READ_BLOCK_LAST_TS_HIGH = 11, | |
9fb4c632 GS |
120 | READ_BLOCK_TS_OVERRUN = 12, |
121 | READ_PIN_VIEW = 13, | |
122 | /* Unassigned register location. */ | |
fefa1800 | 123 | READ_TEST = 15, |
28a35d8a HE |
124 | }; |
125 | ||
57bbf56b HE |
126 | #define LEDSEL0 6 |
127 | #define LEDSEL1 7 | |
128 | ||
22f64ed8 GS |
129 | /* WRITE_MODE register fields. */ |
130 | #define WMR_SDRAMWRITEEN (1 << 0) | |
131 | #define WMR_SDRAMREADEN (1 << 1) | |
132 | #define WMR_TRGRES (1 << 2) | |
133 | #define WMR_TRGEN (1 << 3) | |
134 | #define WMR_FORCESTOP (1 << 4) | |
135 | #define WMR_TRGSW (1 << 5) | |
136 | /* not used: bit position 6 */ | |
137 | #define WMR_SDRAMINIT (1 << 7) | |
138 | ||
139 | /* READ_MODE register fields. */ | |
140 | #define RMR_SDRAMWRITEEN (1 << 0) | |
141 | #define RMR_SDRAMREADEN (1 << 1) | |
142 | /* not used: bit position 2 */ | |
143 | #define RMR_TRGEN (1 << 3) | |
144 | #define RMR_ROUND (1 << 4) | |
145 | #define RMR_TRIGGERED (1 << 5) | |
146 | #define RMR_POSTTRIGGERED (1 << 6) | |
147 | /* not used: bit position 7 */ | |
148 | ||
fd830beb | 149 | /* |
5b1d15ef GS |
150 | * Layout of the sample data DRAM, which will be downloaded to the PC: |
151 | * | |
152 | * Sigma memory is organized in 32K rows. Each row contains 64 clusters. | |
2c33b092 GS |
153 | * Each cluster contains a timestamp (16bit) and 7 events (16bits each). |
154 | * Events contain 16 bits of sample data (potentially taken at multiple | |
155 | * sample points, see below). | |
156 | * | |
157 | * Total memory size is 32K x 64 x 8 x 2 bytes == 32 MiB (256 Mbit). The | |
158 | * size of a memory row is 1024 bytes. Assuming x16 organization of the | |
159 | * memory array, address specs (sample count, trigger position) are kept | |
160 | * in 24bit entities. The upper 15 bit address the "row", the lower 9 bit | |
161 | * refer to the "event" within the row. Because there is one timestamp for | |
162 | * seven events each, one memory row can hold up to 64x7 == 448 events. | |
5b1d15ef GS |
163 | * |
164 | * Sample data is represented in 16bit quantities. The first sample in | |
165 | * the cluster corresponds to the cluster's timestamp. Each next sample | |
166 | * corresponds to the timestamp + 1, timestamp + 2, etc (the distance is | |
167 | * one sample period, according to the samplerate). In the absence of | |
168 | * pin level changes, no data is provided (RLE compression). A cluster | |
169 | * is enforced for each 64K ticks of the timestamp, to reliably handle | |
2c33b092 | 170 | * rollover and determine the next timestamp of the next cluster. |
5b1d15ef | 171 | * |
2c33b092 GS |
172 | * For samplerates up to 50MHz, an event directly translates to one set |
173 | * of sample data at a single sample point, spanning up to 16 channels. | |
5b1d15ef GS |
174 | * For samplerates of 100MHz, there is one 16 bit entity for each 20ns |
175 | * period (50MHz rate). The 16 bit memory contains 2 samples of up to | |
176 | * 8 channels. Bits of multiple samples are interleaved. For samplerates | |
177 | * of 200MHz one 16bit entity contains 4 samples of up to 4 channels, | |
178 | * each 5ns apart. | |
fd830beb MV |
179 | */ |
180 | ||
2c33b092 GS |
181 | #define ROW_COUNT 32768 |
182 | #define ROW_LENGTH_BYTES 1024 | |
183 | #define ROW_LENGTH_U16 (ROW_LENGTH_BYTES / sizeof(uint16_t)) | |
184 | #define ROW_SHIFT 9 /* log2 of u16 count */ | |
185 | #define ROW_MASK ((1UL << ROW_SHIFT) - 1) | |
186 | #define EVENTS_PER_CLUSTER 7 | |
187 | #define CLUSTERS_PER_ROW (ROW_LENGTH_U16 / (1 + EVENTS_PER_CLUSTER)) | |
188 | #define EVENTS_PER_ROW (CLUSTERS_PER_ROW * EVENTS_PER_CLUSTER) | |
fd830beb | 189 | |
fd830beb | 190 | struct sigma_dram_line { |
2c33b092 GS |
191 | struct sigma_dram_cluster { |
192 | uint8_t timestamp_lo; | |
193 | uint8_t timestamp_hi; | |
194 | struct sigma_dram_event { | |
195 | uint8_t sample_hi; | |
196 | uint8_t sample_lo; | |
197 | } samples[EVENTS_PER_CLUSTER]; | |
198 | } cluster[CLUSTERS_PER_ROW]; | |
fd830beb MV |
199 | }; |
200 | ||
edca2c5c HE |
201 | struct clockselect_50 { |
202 | uint8_t async; | |
203 | uint8_t fraction; | |
ba7dd8bb | 204 | uint16_t disabled_channels; |
edca2c5c HE |
205 | }; |
206 | ||
57bbf56b HE |
207 | /* The effect of all these are still a bit unclear. */ |
208 | struct triggerinout { | |
209 | uint8_t trgout_resistor_enable : 1; | |
210 | uint8_t trgout_resistor_pullup : 1; | |
211 | uint8_t reserved1 : 1; | |
212 | uint8_t trgout_bytrigger : 1; | |
213 | uint8_t trgout_byevent : 1; | |
214 | uint8_t trgout_bytriggerin : 1; | |
215 | uint8_t reserved2 : 2; | |
216 | ||
217 | /* Should be set same as the first two */ | |
218 | uint8_t trgout_resistor_enable2 : 1; | |
219 | uint8_t trgout_resistor_pullup2 : 1; | |
220 | ||
221 | uint8_t reserved3 : 1; | |
222 | uint8_t trgout_long : 1; | |
223 | uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */ | |
224 | uint8_t trgin_negate : 1; | |
225 | uint8_t trgout_enable : 1; | |
226 | uint8_t trgin_enable : 1; | |
227 | }; | |
228 | ||
ee492173 HE |
229 | struct triggerlut { |
230 | /* The actual LUTs. */ | |
231 | uint16_t m0d[4], m1d[4], m2d[4]; | |
232 | uint16_t m3, m3s, m4; | |
233 | ||
f3f19d11 | 234 | /* Parameters should be sent as a single register write. */ |
ee492173 HE |
235 | struct { |
236 | uint8_t selc : 2; | |
237 | uint8_t selpresc : 6; | |
238 | ||
239 | uint8_t selinc : 2; | |
240 | uint8_t selres : 2; | |
241 | uint8_t sela : 2; | |
242 | uint8_t selb : 2; | |
243 | ||
244 | uint16_t cmpb; | |
245 | uint16_t cmpa; | |
246 | } params; | |
247 | }; | |
248 | ||
c53d793f HE |
249 | /* Trigger configuration */ |
250 | struct sigma_trigger { | |
ba7dd8bb | 251 | /* Only two channels can be used in mask. */ |
a42aec7f HE |
252 | uint16_t risingmask; |
253 | uint16_t fallingmask; | |
c53d793f HE |
254 | |
255 | /* Simple trigger support (<= 50 MHz). */ | |
256 | uint16_t simplemask; | |
257 | uint16_t simplevalue; | |
258 | ||
c53d793f HE |
259 | /* TODO: Advanced trigger support (boolean expressions). */ |
260 | }; | |
261 | ||
262 | /* Events for trigger operation. */ | |
263 | enum triggerop { | |
264 | OP_LEVEL = 1, | |
265 | OP_NOT, | |
266 | OP_RISE, | |
267 | OP_FALL, | |
268 | OP_RISEFALL, | |
269 | OP_NOTRISE, | |
270 | OP_NOTFALL, | |
271 | OP_NOTRISEFALL, | |
272 | }; | |
273 | ||
274 | /* Logical functions for trigger operation. */ | |
275 | enum triggerfunc { | |
276 | FUNC_AND = 1, | |
277 | FUNC_NAND, | |
278 | FUNC_OR, | |
279 | FUNC_NOR, | |
280 | FUNC_XOR, | |
281 | FUNC_NXOR, | |
282 | }; | |
283 | ||
6aac7737 HE |
284 | struct sigma_state { |
285 | enum { | |
286 | SIGMA_UNINITIALIZED = 0, | |
1bb9dc82 | 287 | SIGMA_CONFIG, |
6aac7737 HE |
288 | SIGMA_IDLE, |
289 | SIGMA_CAPTURE, | |
dde0175d | 290 | SIGMA_STOPPING, |
6aac7737 HE |
291 | SIGMA_DOWNLOAD, |
292 | } state; | |
6aac7737 HE |
293 | uint16_t lastts; |
294 | uint16_t lastsample; | |
6aac7737 HE |
295 | }; |
296 | ||
80e717b3 GS |
297 | enum sigma_firmware_idx { |
298 | SIGMA_FW_NONE, | |
299 | SIGMA_FW_50MHZ, | |
300 | SIGMA_FW_100MHZ, | |
301 | SIGMA_FW_200MHZ, | |
302 | SIGMA_FW_SYNC, | |
303 | SIGMA_FW_FREQ, | |
304 | }; | |
305 | ||
98b43eb3 GS |
306 | struct submit_buffer; |
307 | ||
0e1357e8 | 308 | struct dev_context { |
53a939ab GS |
309 | struct { |
310 | uint16_t vid, pid; | |
311 | uint32_t serno; | |
312 | uint16_t prefix; | |
313 | enum asix_device_type type; | |
314 | } id; | |
99965709 | 315 | struct ftdi_context ftdic; |
5e78a564 GS |
316 | uint64_t samplerate; |
317 | struct sr_sw_limits cfg_limits; /* Configured limits (user specified). */ | |
318 | struct sr_sw_limits acq_limits; /* Acquisition limits (internal use). */ | |
319 | struct sr_sw_limits feed_limits; /* Datafeed limits (internal use). */ | |
80e717b3 | 320 | enum sigma_firmware_idx firmware_idx; |
ba7dd8bb | 321 | int num_channels; |
99965709 | 322 | int samples_per_event; |
efad7ccc | 323 | uint64_t capture_ratio; |
99965709 | 324 | struct sigma_trigger trigger; |
5b5ea7c6 | 325 | int use_triggers; |
99965709 | 326 | struct sigma_state state; |
98b43eb3 | 327 | struct submit_buffer *buffer; |
99965709 HE |
328 | }; |
329 | ||
3ba56876 | 330 | extern SR_PRIV const uint64_t samplerates[]; |
4154a516 | 331 | extern SR_PRIV const size_t samplerates_count; |
3ba56876 | 332 | |
176d785d | 333 | SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
3ba56876 | 334 | struct dev_context *devc); |
335 | SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc); | |
336 | SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc); | |
5e78a564 GS |
337 | SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate); |
338 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi); | |
339 | SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc); | |
3ba56876 | 340 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi); |
341 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data); | |
342 | SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc); | |
343 | ||
204b1629 | 344 | #endif |