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204b1629 | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
204b1629 | 3 | * |
3ba56876 | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
204b1629 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
3ba56876 | 22 | #ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H |
23 | #define LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H | |
24 | ||
25 | #include <stdint.h> | |
4154a516 | 26 | #include <stdlib.h> |
3ba56876 | 27 | #include <glib.h> |
28 | #include <ftdi.h> | |
29 | #include <string.h> | |
30 | #include <libsigrok/libsigrok.h> | |
31 | #include "libsigrok-internal.h" | |
28a35d8a | 32 | |
de3f7acb GS |
33 | /* |
34 | * Triggers are not working in this implementation. Stop claiming | |
35 | * support for the feature which effectively is not available, until | |
36 | * the implementation got fixed. Yet keep the code in place and allow | |
37 | * developers to turn on this switch during development. | |
38 | */ | |
39 | #define ASIX_SIGMA_WITH_TRIGGER 0 | |
40 | ||
3544f848 | 41 | #define LOG_PREFIX "asix-sigma" |
47f4f073 | 42 | |
3ba56876 | 43 | #define USB_VENDOR 0xa600 |
44 | #define USB_PRODUCT 0xa000 | |
45 | #define USB_DESCRIPTION "ASIX SIGMA" | |
46 | #define USB_VENDOR_NAME "ASIX" | |
47 | #define USB_MODEL_NAME "SIGMA" | |
48 | ||
fefa1800 | 49 | enum sigma_write_register { |
28a35d8a HE |
50 | WRITE_CLOCK_SELECT = 0, |
51 | WRITE_TRIGGER_SELECT0 = 1, | |
52 | WRITE_TRIGGER_SELECT1 = 2, | |
53 | WRITE_MODE = 3, | |
54 | WRITE_MEMROW = 4, | |
55 | WRITE_POST_TRIGGER = 5, | |
56 | WRITE_TRIGGER_OPTION = 6, | |
57 | WRITE_PIN_VIEW = 7, | |
58 | ||
fefa1800 | 59 | WRITE_TEST = 15, |
28a35d8a HE |
60 | }; |
61 | ||
fefa1800 | 62 | enum sigma_read_register { |
28a35d8a HE |
63 | READ_ID = 0, |
64 | READ_TRIGGER_POS_LOW = 1, | |
65 | READ_TRIGGER_POS_HIGH = 2, | |
66 | READ_TRIGGER_POS_UP = 3, | |
67 | READ_STOP_POS_LOW = 4, | |
68 | READ_STOP_POS_HIGH = 5, | |
69 | READ_STOP_POS_UP = 6, | |
70 | READ_MODE = 7, | |
71 | READ_PIN_CHANGE_LOW = 8, | |
72 | READ_PIN_CHANGE_HIGH = 9, | |
73 | READ_BLOCK_LAST_TS_LOW = 10, | |
74 | READ_BLOCK_LAST_TS_HIGH = 11, | |
75 | READ_PIN_VIEW = 12, | |
76 | ||
fefa1800 | 77 | READ_TEST = 15, |
28a35d8a HE |
78 | }; |
79 | ||
1c2736f9 MV |
80 | #define REG_ADDR_LOW (0x0 << 4) |
81 | #define REG_ADDR_HIGH (0x1 << 4) | |
82 | #define REG_DATA_LOW (0x2 << 4) | |
83 | #define REG_DATA_HIGH_WRITE (0x3 << 4) | |
84 | #define REG_READ_ADDR (0x4 << 4) | |
85 | #define REG_DRAM_WAIT_ACK (0x5 << 4) | |
28a35d8a HE |
86 | |
87 | /* Bit (1 << 4) can be low or high (double buffer / cache) */ | |
1c2736f9 MV |
88 | #define REG_DRAM_BLOCK (0x6 << 4) |
89 | #define REG_DRAM_BLOCK_BEGIN (0x8 << 4) | |
90 | #define REG_DRAM_BLOCK_DATA (0xa << 4) | |
28a35d8a | 91 | |
57bbf56b HE |
92 | #define LEDSEL0 6 |
93 | #define LEDSEL1 7 | |
94 | ||
28a35d8a HE |
95 | #define NEXT_REG 1 |
96 | ||
97 | #define EVENTS_PER_CLUSTER 7 | |
98 | ||
99 | #define CHUNK_SIZE 1024 | |
100 | ||
22f64ed8 GS |
101 | /* WRITE_MODE register fields. */ |
102 | #define WMR_SDRAMWRITEEN (1 << 0) | |
103 | #define WMR_SDRAMREADEN (1 << 1) | |
104 | #define WMR_TRGRES (1 << 2) | |
105 | #define WMR_TRGEN (1 << 3) | |
106 | #define WMR_FORCESTOP (1 << 4) | |
107 | #define WMR_TRGSW (1 << 5) | |
108 | /* not used: bit position 6 */ | |
109 | #define WMR_SDRAMINIT (1 << 7) | |
110 | ||
111 | /* READ_MODE register fields. */ | |
112 | #define RMR_SDRAMWRITEEN (1 << 0) | |
113 | #define RMR_SDRAMREADEN (1 << 1) | |
114 | /* not used: bit position 2 */ | |
115 | #define RMR_TRGEN (1 << 3) | |
116 | #define RMR_ROUND (1 << 4) | |
117 | #define RMR_TRIGGERED (1 << 5) | |
118 | #define RMR_POSTTRIGGERED (1 << 6) | |
119 | /* not used: bit position 7 */ | |
120 | ||
fd830beb | 121 | /* |
5b1d15ef GS |
122 | * Layout of the sample data DRAM, which will be downloaded to the PC: |
123 | * | |
124 | * Sigma memory is organized in 32K rows. Each row contains 64 clusters. | |
125 | * Each cluster contains a timestamp (16bit) and 7 samples (16bits each). | |
126 | * Total memory size is 32K x 64 x 8 x 2 bytes == 32 MB (256 Mbit). | |
127 | * | |
128 | * Sample data is represented in 16bit quantities. The first sample in | |
129 | * the cluster corresponds to the cluster's timestamp. Each next sample | |
130 | * corresponds to the timestamp + 1, timestamp + 2, etc (the distance is | |
131 | * one sample period, according to the samplerate). In the absence of | |
132 | * pin level changes, no data is provided (RLE compression). A cluster | |
133 | * is enforced for each 64K ticks of the timestamp, to reliably handle | |
134 | * rollover and determination of the next timestamp of the next cluster. | |
135 | * | |
136 | * For samplerates of 100MHz, there is one 16 bit entity for each 20ns | |
137 | * period (50MHz rate). The 16 bit memory contains 2 samples of up to | |
138 | * 8 channels. Bits of multiple samples are interleaved. For samplerates | |
139 | * of 200MHz one 16bit entity contains 4 samples of up to 4 channels, | |
140 | * each 5ns apart. | |
141 | * | |
142 | * Memory addresses (sample count, trigger position) are kept in 24bit | |
143 | * entities. The upper 15 bit refer to the "row", the lower 9 bit refer | |
144 | * to the "event" within the row. Because there is one timestamp for | |
145 | * seven samples each, one memory row can hold up to 64x7 == 448 samples. | |
fd830beb MV |
146 | */ |
147 | ||
148 | /* One "DRAM cluster" contains a timestamp and 7 samples, 16b total. */ | |
149 | struct sigma_dram_cluster { | |
150 | uint8_t timestamp_lo; | |
151 | uint8_t timestamp_hi; | |
152 | struct { | |
153 | uint8_t sample_hi; | |
154 | uint8_t sample_lo; | |
155 | } samples[7]; | |
156 | }; | |
157 | ||
158 | /* One "DRAM line" contains 64 "DRAM clusters", 1024b total. */ | |
159 | struct sigma_dram_line { | |
160 | struct sigma_dram_cluster cluster[64]; | |
161 | }; | |
162 | ||
edca2c5c HE |
163 | struct clockselect_50 { |
164 | uint8_t async; | |
165 | uint8_t fraction; | |
ba7dd8bb | 166 | uint16_t disabled_channels; |
edca2c5c HE |
167 | }; |
168 | ||
57bbf56b HE |
169 | /* The effect of all these are still a bit unclear. */ |
170 | struct triggerinout { | |
171 | uint8_t trgout_resistor_enable : 1; | |
172 | uint8_t trgout_resistor_pullup : 1; | |
173 | uint8_t reserved1 : 1; | |
174 | uint8_t trgout_bytrigger : 1; | |
175 | uint8_t trgout_byevent : 1; | |
176 | uint8_t trgout_bytriggerin : 1; | |
177 | uint8_t reserved2 : 2; | |
178 | ||
179 | /* Should be set same as the first two */ | |
180 | uint8_t trgout_resistor_enable2 : 1; | |
181 | uint8_t trgout_resistor_pullup2 : 1; | |
182 | ||
183 | uint8_t reserved3 : 1; | |
184 | uint8_t trgout_long : 1; | |
185 | uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */ | |
186 | uint8_t trgin_negate : 1; | |
187 | uint8_t trgout_enable : 1; | |
188 | uint8_t trgin_enable : 1; | |
189 | }; | |
190 | ||
ee492173 HE |
191 | struct triggerlut { |
192 | /* The actual LUTs. */ | |
193 | uint16_t m0d[4], m1d[4], m2d[4]; | |
194 | uint16_t m3, m3s, m4; | |
195 | ||
f3f19d11 | 196 | /* Parameters should be sent as a single register write. */ |
ee492173 HE |
197 | struct { |
198 | uint8_t selc : 2; | |
199 | uint8_t selpresc : 6; | |
200 | ||
201 | uint8_t selinc : 2; | |
202 | uint8_t selres : 2; | |
203 | uint8_t sela : 2; | |
204 | uint8_t selb : 2; | |
205 | ||
206 | uint16_t cmpb; | |
207 | uint16_t cmpa; | |
208 | } params; | |
209 | }; | |
210 | ||
c53d793f HE |
211 | /* Trigger configuration */ |
212 | struct sigma_trigger { | |
ba7dd8bb | 213 | /* Only two channels can be used in mask. */ |
a42aec7f HE |
214 | uint16_t risingmask; |
215 | uint16_t fallingmask; | |
c53d793f HE |
216 | |
217 | /* Simple trigger support (<= 50 MHz). */ | |
218 | uint16_t simplemask; | |
219 | uint16_t simplevalue; | |
220 | ||
c53d793f HE |
221 | /* TODO: Advanced trigger support (boolean expressions). */ |
222 | }; | |
223 | ||
224 | /* Events for trigger operation. */ | |
225 | enum triggerop { | |
226 | OP_LEVEL = 1, | |
227 | OP_NOT, | |
228 | OP_RISE, | |
229 | OP_FALL, | |
230 | OP_RISEFALL, | |
231 | OP_NOTRISE, | |
232 | OP_NOTFALL, | |
233 | OP_NOTRISEFALL, | |
234 | }; | |
235 | ||
236 | /* Logical functions for trigger operation. */ | |
237 | enum triggerfunc { | |
238 | FUNC_AND = 1, | |
239 | FUNC_NAND, | |
240 | FUNC_OR, | |
241 | FUNC_NOR, | |
242 | FUNC_XOR, | |
243 | FUNC_NXOR, | |
244 | }; | |
245 | ||
6aac7737 HE |
246 | struct sigma_state { |
247 | enum { | |
248 | SIGMA_UNINITIALIZED = 0, | |
249 | SIGMA_IDLE, | |
250 | SIGMA_CAPTURE, | |
251 | SIGMA_DOWNLOAD, | |
252 | } state; | |
253 | ||
6aac7737 HE |
254 | uint16_t lastts; |
255 | uint16_t lastsample; | |
6aac7737 HE |
256 | }; |
257 | ||
ea9cfed7 | 258 | /* Private, per-device-instance driver context. */ |
0e1357e8 | 259 | struct dev_context { |
99965709 HE |
260 | struct ftdi_context ftdic; |
261 | uint64_t cur_samplerate; | |
94ba4bd6 | 262 | uint64_t limit_msec; |
2f7e529c | 263 | uint64_t limit_samples; |
735ed8a1 | 264 | uint64_t sent_samples; |
2f425a56 | 265 | uint64_t start_time; |
99965709 | 266 | int cur_firmware; |
ba7dd8bb | 267 | int num_channels; |
5fc01191 | 268 | int cur_channels; |
99965709 HE |
269 | int samples_per_event; |
270 | int capture_ratio; | |
271 | struct sigma_trigger trigger; | |
5b5ea7c6 | 272 | int use_triggers; |
99965709 | 273 | struct sigma_state state; |
99965709 HE |
274 | }; |
275 | ||
3ba56876 | 276 | extern SR_PRIV const uint64_t samplerates[]; |
4154a516 | 277 | extern SR_PRIV const size_t samplerates_count; |
3ba56876 | 278 | |
279 | SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, | |
280 | struct dev_context *devc); | |
281 | SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc); | |
282 | SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc); | |
283 | SR_PRIV void sigma_clear_helper(void *priv); | |
9a0a606a GS |
284 | SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc, |
285 | uint64_t limit_samples); | |
3ba56876 | 286 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate); |
287 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi); | |
288 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data); | |
289 | SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc); | |
290 | ||
204b1629 | 291 | #endif |