[sigrok-firmware-fx2lafw.git] / sainsmart_dds120.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	/* Toggle the 1kHz pin, only accurate up to ca 8MHz */
	IOE = IOE^0x04;
	TF2 = 0;
}

/**
 * The gain stage is 2 stage approach. -6dB and -20dB on the first stage (attentuator). The second stage is then doing the gain by 3 different resistor values switched into the feedback loop.
 * #Channel 0:
 * PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
 * PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
 * PC1=1; PC2=1; PC3= 0 -> Gain x0.4 =  -8dB
 * PC1=0; PC2=0; PC3= 0 -> Gain x0.5 =  -6dB
 * PC1=0; PC2=0; PC3= 1 -> Gain x1   =   0dB
 * PC1=0; PC2=1; PC3= 0 -> Gain x2   =  +6dB
 * #Channel 1:
 * PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB 
 * PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
 * PE1=1; PC4=1; PC5= 0 -> Gain x0.4 =  -8dB
 * PE1=0; PC4=0; PC5= 0 -> Gain x0.5 =  -6dB
 * PE1=0; PC4=0; PC5= 1 -> Gain x1   =   0dB
 * PE1=0; PC4=1; PC5= 0 -> Gain x2   =  +6dB
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits_C, bit_E, mask_C, mask_E;

	if (channel == 0) {
		mask_C = 0x0E;
		mask_E = 0x00;
		bit_E = 0;
		switch (val) {
		case 1:
			bits_C = 0x02;
			break;
		case 2:
			bits_C = 0x06;
			break;
		case 5:
			bits_C = 0x00;
			break;
		case 10:
			bits_C = 0x04;
			break;
		case 20:
			bits_C = 0x08;
			break;
		default:
			return FALSE;
		}
	} else if (channel == 1) {
		mask_C = 0x30;
		mask_E = 0x02;
		switch (val) {
		case 1:
			bits_C = 0x00;
			bit_E = 0x02; 
			break;
		case 2:
			bits_C = 0x10;
			bit_E = 0x02; 
			break;
		case 5:
			bits_C = 0x00;
			bit_E = 0x00; 
			break;
		case 10:
			bits_C = 0x10;
			bit_E = 0x00; 
			break;
		case 20:
			bits_C = 0x20;
			bit_E = 0x00; 
			break;
		default:
			return FALSE;
		}
	} else {
		return FALSE;
	}
	IOC = (IOC & ~mask_C) | (bits_C & mask_C);
	IOE = (IOE & ~mask_E) | (bit_E & mask_E);
		
	return TRUE;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, 0x40, 0xea },
	{ 16,    1,   1, 2, 0, 0x40, 0xea },
	{ 12,    2,   1, 2, 0, 0x40, 0xea },
	{  8,    3,   2, 2, 0, 0x40, 0xea },
	{  4,    6,   5, 2, 0, 0x40, 0xea },
	{  2,   12,  11, 2, 0, 0x40, 0xea },
	{  1,   24,  23, 2, 0, 0x40, 0xea },
	{ 50,   48,  47, 2, 0, 0x40, 0xea },
	{ 20,  120, 119, 2, 0, 0x40, 0xea },
	{ 10,  240, 239, 2, 0, 0x40, 0xea },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4;
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTL2=0, FIFO
	 * wait 23, CTL2=1
	 * jump 0, CTL2=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTL2=0, FIFO
	 * jump 0, CTL2=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTL2=Z, FIFO, LOOP
	 */

	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = 0x44;
	EXTAUTODAT2 = 0x44;
	EXTAUTODAT2 = 0x00;
	EXTAUTODAT2 = 0x00;
	EXTAUTODAT2 = 0x00;
	EXTAUTODAT2 = 0x00;
	EXTAUTODAT2 = 0x00;

	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe4) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00;
	GPIFCTLCFG = 0x80;
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -1000 & 0xff;
	RCAP2H = (-1000 >> 8) & 0xff;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTCCFG = 0;
	PORTACFG = 0;
	PORTECFG = 0;
	OEE = 0xFF;
	OEC = 0xff;
	OEA = 0x80;

	PA7 = 1;

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU|bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
ce1d0a86 BL	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
	20	*/
	21
	22	#include <fx2macros.h>
	23	#include <fx2ints.h>
	24	#include <autovector.h>
	25	#include <delay.h>
	26	#include <setupdat.h>
	27
	28	/* Change to support as many interfaces as you need. */
	29	static BYTE altiface = 0;
	30
	31	static volatile __bit dosud = FALSE;
	32	static volatile __bit dosuspend = FALSE;
	33
	34	extern __code BYTE highspd_dscr;
	35	extern __code BYTE fullspd_dscr;
	36
	37	void resume_isr(void) __interrupt RESUME_ISR
	38	{
	39	CLEAR_RESUME();
	40	}
	41
	42	void sudav_isr(void) __interrupt SUDAV_ISR
	43	{
	44	dosud = TRUE;
	45	CLEAR_SUDAV();
	46	}
	47
	48	void usbreset_isr(void) __interrupt USBRESET_ISR
	49	{
	50	handle_hispeed(FALSE);
	51	CLEAR_USBRESET();
	52	}
	53
	54	void hispeed_isr(void) __interrupt HISPEED_ISR
	55	{
	56	handle_hispeed(TRUE);
	57	CLEAR_HISPEED();
	58	}
	59
	60	void suspend_isr(void) __interrupt SUSPEND_ISR
	61	{
	62	dosuspend = TRUE;
	63	CLEAR_SUSPEND();
	64	}
65
66	void timer2_isr(void) __interrupt TF2_ISR
67	{
68	/* Toggle the 1kHz pin, only accurate up to ca 8MHz */
69	IOE = IOE^0x04;
70	TF2 = 0;
71	}
72
73	/**
74	* The gain stage is 2 stage approach. -6dB and -20dB on the first stage (attentuator). The second stage is then doing the gain by 3 different resistor values switched into the feedback loop.
75	* #Channel 0:
76	* PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
77	* PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
78	* PC1=1; PC2=1; PC3= 0 -> Gain x0.4 = -8dB
79	* PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB
80	* PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB
81	* PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB
82	* #Channel 1:
83	* PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB
84	* PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
85	* PE1=1; PC4=1; PC5= 0 -> Gain x0.4 = -8dB
86	* PE1=0; PC4=0; PC5= 0 -> Gain x0.5 = -6dB
87	* PE1=0; PC4=0; PC5= 1 -> Gain x1 = 0dB
88	* PE1=0; PC4=1; PC5= 0 -> Gain x2 = +6dB
89	*/
90	static BOOL set_voltage(BYTE channel, BYTE val)
91	{
92	BYTE bits_C, bit_E, mask_C, mask_E;
93
94	if (channel == 0) {
95	mask_C = 0x0E;
96	mask_E = 0x00;
97	bit_E = 0;
98	switch (val) {
99	case 1:
100	bits_C = 0x02;
101	break;
102	case 2:
103	bits_C = 0x06;
104	break;
105	case 5:
106	bits_C = 0x00;
107	break;
108	case 10:
109	bits_C = 0x04;
110	break;
111	case 20:
112	bits_C = 0x08;
113	break;
114	default:
115	return FALSE;
116	}
117	} else if (channel == 1) {
118	mask_C = 0x30;
119	mask_E = 0x02;
120	switch (val) {
121	case 1:
122	bits_C = 0x00;
123	bit_E = 0x02;
124	break;
125	case 2:
126	bits_C = 0x10;
127	bit_E = 0x02;
128	break;
129	case 5:
130	bits_C = 0x00;
131	bit_E = 0x00;
132	break;
133	case 10:
134	bits_C = 0x10;
135	bit_E = 0x00;
136	break;
137	case 20:
138	bits_C = 0x20;
139	bit_E = 0x00;
140	break;
141	default:
142	return FALSE;
143	}
144	} else {
145	return FALSE;
146	}
147	IOC = (IOC & ~mask_C) \| (bits_C & mask_C);
148	IOE = (IOE & ~mask_E) \| (bit_E & mask_E);
149
150	return TRUE;
151	}
152
153	static BOOL set_numchannels(BYTE numchannels)
154	{
155	if (numchannels == 1 \|\| numchannels == 2) {
156	BYTE fifocfg = 7 + numchannels;
157	EP2FIFOCFG = fifocfg;
158	EP6FIFOCFG = fifocfg;
159	return TRUE;
160	}
161
162	return FALSE;
163	}
164
165	static void clear_fifo(void)
166	{
167	GPIFABORT = 0xff;
168	SYNCDELAY3;
169	FIFORESET = 0x80;
170	SYNCDELAY3;
171	FIFORESET = 0x82;
172	SYNCDELAY3;
173	FIFORESET = 0x86;
174	SYNCDELAY3;
175	FIFORESET = 0;
176	}
177
178	static void stop_sampling(void)
179	{
180	GPIFABORT = 0xff;
181	SYNCDELAY3;
182	INPKTEND = (altiface == 0) ? 6 : 2;
183	}
184
185	static void start_sampling(void)
186	{
187	int i;
188
189	clear_fifo();
190
191	for (i = 0; i < 1000; i++);
192
193	while (!(GPIFTRIG & 0x80))
194	;
195
196	SYNCDELAY3;
197	GPIFTCB1 = 0x28;
198	SYNCDELAY3;
199	GPIFTCB0 = 0;
200	GPIFTRIG = (altiface == 0) ? 6 : 4;
201
202	}
203
204	static void select_interface(BYTE alt)
205	{
206	const BYTE *pPacketSize = \
207	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
208	+ (9 + (16 * alt) + 9 + 4);
209
210	altiface = alt;
211
212	if (alt == 0) {
213	/* Bulk on EP6. */
214	EP2CFG = 0x00;
215	EP6CFG = 0xe0;
216	EP6GPIFFLGSEL = 1;
217	EP6AUTOINLENL = pPacketSize[0];
218	EP6AUTOINLENH = pPacketSize[1];
219	} else {
220	/* Iso on EP2. */
221	EP2CFG = 0xd8;
222	EP6CFG = 0x00;
223	EP2GPIFFLGSEL = 1;
224	EP2AUTOINLENL = pPacketSize[0];
225	EP2AUTOINLENH = pPacketSize[1] & 0x7;
226	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
227	}
228	}
229
230	static const struct samplerate_info {
231	BYTE rate;
232	BYTE wait0;
233	BYTE wait1;
234	BYTE opc0;
235	BYTE opc1;
236	BYTE out0;
237	BYTE ifcfg;
238	} samplerates[] = {
239	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
240	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
241	{ 24, 1, 0, 2, 1, 0x40, 0xea },
242	{ 16, 1, 1, 2, 0, 0x40, 0xea },
243	{ 12, 2, 1, 2, 0, 0x40, 0xea },
244	{ 8, 3, 2, 2, 0, 0x40, 0xea },
245	{ 4, 6, 5, 2, 0, 0x40, 0xea },
246	{ 2, 12, 11, 2, 0, 0x40, 0xea },
247	{ 1, 24, 23, 2, 0, 0x40, 0xea },
248	{ 50, 48, 47, 2, 0, 0x40, 0xea },
249	{ 20, 120, 119, 2, 0, 0x40, 0xea },
250	{ 10, 240, 239, 2, 0, 0x40, 0xea },
251	};
252
253	static BOOL set_samplerate(BYTE rate)
254	{
255	BYTE i = 0;
256
257	while (samplerates[i].rate != rate) {
258	i++;
259	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
260	return FALSE;
261	}
262
263	IFCONFIG = samplerates[i].ifcfg;
264
265	AUTOPTRSETUP = 7;
266	AUTOPTRH2 = 0xE4;
267	AUTOPTRL2 = 0x00;
268
269	/*
270	* The program for low-speed, e.g. 1 MHz, is:
271	* wait 24, CTL2=0, FIFO
272	* wait 23, CTL2=1
273	* jump 0, CTL2=1
274	*
275	* The program for 24 MHz is:
276	* wait 1, CTL2=0, FIFO
277	* jump 0, CTL2=1
278	*
279	* The program for 30/48 MHz is:
280	* jump 0, CTL2=Z, FIFO, LOOP
281	*/
282
283	EXTAUTODAT2 = samplerates[i].wait0;
284	EXTAUTODAT2 = samplerates[i].wait1;
285	EXTAUTODAT2 = 1;
286	EXTAUTODAT2 = 0;
287	EXTAUTODAT2 = 0;
288	EXTAUTODAT2 = 0;
289	EXTAUTODAT2 = 0;
290	EXTAUTODAT2 = 0;
291
292	EXTAUTODAT2 = samplerates[i].opc0;
293	EXTAUTODAT2 = samplerates[i].opc1;
294	EXTAUTODAT2 = 1;
295	EXTAUTODAT2 = 0;
296	EXTAUTODAT2 = 0;
297	EXTAUTODAT2 = 0;
298	EXTAUTODAT2 = 0;
299	EXTAUTODAT2 = 0;
300
301	EXTAUTODAT2 = samplerates[i].out0;
302	EXTAUTODAT2 = 0x44;
303	EXTAUTODAT2 = 0x44;
304	EXTAUTODAT2 = 0x00;
305	EXTAUTODAT2 = 0x00;
306	EXTAUTODAT2 = 0x00;
307	EXTAUTODAT2 = 0x00;
308	EXTAUTODAT2 = 0x00;
309
310	EXTAUTODAT2 = 0;
311	EXTAUTODAT2 = 0;
312	EXTAUTODAT2 = 0;
313	EXTAUTODAT2 = 0;
314	EXTAUTODAT2 = 0;
315	EXTAUTODAT2 = 0;
316	EXTAUTODAT2 = 0;
317	EXTAUTODAT2 = 0;
318
319	for (i = 0; i < 96; i++)
320	EXTAUTODAT2 = 0;
321
322	return TRUE;
323	}
324
325	/* Set alt_ifc to the current alt interface for ifc. /
326	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
327	{
328	(void)ifc;
329
330	*alt_ifc = altiface;
331
332	return TRUE;
333	}
334
335	/*
336	* Return TRUE if you set the interface requested.
337	*
338	* Note: This function should reconfigure and reset the endpoints
339	* according to the interface descriptors you provided.
340	*/
341	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
342	{
343	if (ifc == 0)
344	select_interface(alt_ifc);
345
346	return TRUE;
347	}
348
349	BYTE handle_get_configuration(void)
350	{
351	/* We only support configuration 0. */
352	return 0;
353	}
354
355	BOOL handle_set_configuration(BYTE cfg)
356	{
357	/* We only support configuration 0. */
358	(void)cfg;
359
360	return TRUE;
361	}
362
363	BOOL handle_vendorcommand(BYTE cmd)
364	{
365	stop_sampling();
366
367	/* Clear EP0BCH/L for each valid command. */
368	if (cmd >= 0xe0 && cmd <= 0xe4) {
369	EP0BCH = 0;
370	EP0BCL = 0;
371	while (EP0CS & bmEPBUSY);
372	}
373
374	switch (cmd) {
375	case 0xe0:
376	case 0xe1:
377	set_voltage(cmd - 0xe0, EP0BUF[0]);
378	return TRUE;
379	case 0xe2:
380	set_samplerate(EP0BUF[0]);
381	return TRUE;
382	case 0xe3:
383	if (EP0BUF[0] == 1)
384	start_sampling();
385	return TRUE;
386	case 0xe4:
387	set_numchannels(EP0BUF[0]);
388	return TRUE;
389	}
390
391	return FALSE; /* Not handled by handlers. */
392	}
393
394	static void init(void)
395	{
396	EP4CFG = 0;
397	EP8CFG = 0;
398
399	/* In idle mode tristate all outputs. */
400	GPIFIDLECTL = 0x00;
401	GPIFCTLCFG = 0x80;
402	GPIFWFSELECT = 0x00;
403	GPIFREADYSTAT = 0x00;
404
405	stop_sampling();
406
407	set_voltage(0, 1);
408	set_voltage(1, 1);
409	set_samplerate(1);
410	set_numchannels(2);
411	select_interface(0);
412	}
413
414	static void main(void)
415	{
416	/* Save energy. */
417	SETCPUFREQ(CLK_12M);
418
419	init();
420
421	/* Set up interrupts. */
422	USE_USB_INTS();
423
424	ENABLE_SUDAV();
425	ENABLE_USBRESET();
426	ENABLE_HISPEED();
427	ENABLE_SUSPEND();
428	ENABLE_RESUME();
429
430	/* Global (8051) interrupt enable. */
431	EA = 1;
432
433	/* Init timer2. */
434	RCAP2L = -1000 & 0xff;
435	RCAP2H = (-1000 >> 8) & 0xff;
436	T2CON = 0;
437	ET2 = 1;
438	TR2 = 1;
439
440	RENUMERATE_UNCOND();
441
442	PORTCCFG = 0;
443	PORTACFG = 0;
444	PORTECFG = 0;
445	OEE = 0xFF;
446	OEC = 0xff;
447	OEA = 0x80;
448
449	PA7 = 1;
450
451	while (TRUE) {
452	if (dosud) {
453	dosud = FALSE;
454	handle_setupdata();
455	}
456
457	if (dosuspend) {
458	dosuspend = FALSE;
459	do {
460	/* Make sure ext wakeups are cleared. */
461	WAKEUPCS \|= bmWU\|bmWU2;
462	SUSPEND = 1;
463	PCON \|= 1;
464	__asm
465	nop
466	nop
467	nop
468	nop
469	nop
470	nop
471	nop
472	__endasm;
473	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
474
475	/* Resume (TRM 6.4). */
476	if (REMOTE_WAKEUP()) {
477	delay(5);
478	USBCS \|= bmSIGRESUME;
479	delay(15);
480	USBCS &= ~bmSIGRESUME;
481	}
482	}
483	}
484	}