[sigrok-firmware-fx2lafw.git] / sainsmart_dds120.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	/* Toggle the 1kHz pin, only accurate up to ca 8MHz */
	IOE = IOE^0x04;
	TF2 = 0;
}

/**
 * The gain stage is 2 stage approach. -6dB and -20dB on the first stage (attentuator). The second stage is then doing the gain by 3 different resistor values switched into the feedback loop.
 * #Channel 0:
 * PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
 * PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
 * PC1=1; PC2=1; PC3= 0 -> Gain x0.4 =  -8dB
 * PC1=0; PC2=0; PC3= 0 -> Gain x0.5 =  -6dB
 * PC1=0; PC2=0; PC3= 1 -> Gain x1   =   0dB
 * PC1=0; PC2=1; PC3= 0 -> Gain x2   =  +6dB
 * #Channel 1:
 * PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB 
 * PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
 * PE1=1; PC4=1; PC5= 0 -> Gain x0.4 =  -8dB
 * PE1=0; PC4=0; PC5= 0 -> Gain x0.5 =  -6dB
 * PE1=0; PC4=0; PC5= 1 -> Gain x1   =   0dB
 * PE1=0; PC4=1; PC5= 0 -> Gain x2   =  +6dB
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits_C, bit_E, mask_C, mask_E;

	if (channel == 0) {
		mask_C = 0x0E;
		mask_E = 0x00;
		bit_E = 0;
		switch (val) {
		case 1:
			bits_C = 0x02;
			break;
		case 2:
			bits_C = 0x06;
			break;
		case 5:
			bits_C = 0x00;
			break;
		case 10:
			bits_C = 0x04;
			break;
		case 20:
			bits_C = 0x08;
			break;
		default:
			return FALSE;
		}
	} else if (channel == 1) {
		mask_C = 0x30;
		mask_E = 0x02;
		switch (val) {
		case 1:
			bits_C = 0x00;
			bit_E = 0x02; 
			break;
		case 2:
			bits_C = 0x10;
			bit_E = 0x02; 
			break;
		case 5:
			bits_C = 0x00;
			bit_E = 0x00; 
			break;
		case 10:
			bits_C = 0x10;
			bit_E = 0x00; 
			break;
		case 20:
			bits_C = 0x20;
			bit_E = 0x00; 
			break;
		default:
			return FALSE;
		}
	} else {
		return FALSE;
	}
	IOC = (IOC & ~mask_C) | (bits_C & mask_C);
	IOE = (IOE & ~mask_E) | (bit_E & mask_E);
		
	return TRUE;
}


/**
 * Each LSB in the nibble of the byte controls the coupling per channel.
 *
 * Setting PE3 disables AC coupling capacitor on CH0.
 * Setting PE0 disables AC coupling capacitor on CH1.
 */
static void set_coupling(BYTE coupling_cfg)
{
	if (coupling_cfg & 0x01)
		IOE |= 0x08;
	else
		IOE &= ~0x08;

	if (coupling_cfg & 0x10)
		IOE |= 0x01;
	else
		IOE &= ~0x01;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, 0x40, 0xea },
	{ 16,    1,   1, 2, 0, 0x40, 0xea },
	{ 12,    2,   1, 2, 0, 0x40, 0xea },
	{  8,    3,   2, 2, 0, 0x40, 0xea },
	{  4,    6,   5, 2, 0, 0x40, 0xea },
	{  2,   12,  11, 2, 0, 0x40, 0xea },
	{  1,   24,  23, 2, 0, 0x40, 0xea },
	{ 50,   48,  47, 2, 0, 0x40, 0xea },
	{ 20,  120, 119, 2, 0, 0x40, 0xea },
	{ 10,  240, 239, 2, 0, 0x40, 0xea },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4;
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTL2=0, FIFO
	 * wait 23, CTL2=1
	 * jump 0, CTL2=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTL2=0, FIFO
	 * jump 0, CTL2=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTL2=Z, FIFO, LOOP
	 */

	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = 0x44;
	EXTAUTODAT2 = 0x44;
	EXTAUTODAT2 = 0x00;
	EXTAUTODAT2 = 0x00;
	EXTAUTODAT2 = 0x00;
	EXTAUTODAT2 = 0x00;
	EXTAUTODAT2 = 0x00;

	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe5) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	case 0xe5:
		set_coupling(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00;
	GPIFCTLCFG = 0x80;
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -1000 & 0xff;
	RCAP2H = (-1000 >> 8) & 0xff;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTCCFG = 0;
	PORTACFG = 0;
	PORTECFG = 0;
	OEE = 0xFF;
	OEC = 0xff;
	OEA = 0x80;

	PA7 = 1;

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU|bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
ce1d0a86 BL	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
	20	*/
	21
	22	#include <fx2macros.h>
	23	#include <fx2ints.h>
	24	#include <autovector.h>
	25	#include <delay.h>
	26	#include <setupdat.h>
	27
	28	/* Change to support as many interfaces as you need. */
	29	static BYTE altiface = 0;
	30
	31	static volatile __bit dosud = FALSE;
	32	static volatile __bit dosuspend = FALSE;
	33
	34	extern __code BYTE highspd_dscr;
	35	extern __code BYTE fullspd_dscr;
	36
	37	void resume_isr(void) __interrupt RESUME_ISR
	38	{
	39	CLEAR_RESUME();
	40	}
	41
	42	void sudav_isr(void) __interrupt SUDAV_ISR
	43	{
	44	dosud = TRUE;
	45	CLEAR_SUDAV();
	46	}
	47
	48	void usbreset_isr(void) __interrupt USBRESET_ISR
	49	{
	50	handle_hispeed(FALSE);
	51	CLEAR_USBRESET();
	52	}
	53
	54	void hispeed_isr(void) __interrupt HISPEED_ISR
	55	{
	56	handle_hispeed(TRUE);
	57	CLEAR_HISPEED();
	58	}
	59
	60	void suspend_isr(void) __interrupt SUSPEND_ISR
	61	{
	62	dosuspend = TRUE;
	63	CLEAR_SUSPEND();
	64	}
65
66	void timer2_isr(void) __interrupt TF2_ISR
67	{
68	/* Toggle the 1kHz pin, only accurate up to ca 8MHz */
69	IOE = IOE^0x04;
70	TF2 = 0;
71	}
72
73	/**
74	* The gain stage is 2 stage approach. -6dB and -20dB on the first stage (attentuator). The second stage is then doing the gain by 3 different resistor values switched into the feedback loop.
75	* #Channel 0:
76	* PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
77	* PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
78	* PC1=1; PC2=1; PC3= 0 -> Gain x0.4 = -8dB
79	* PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB
80	* PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB
81	* PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB
82	* #Channel 1:
83	* PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB
84	* PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
85	* PE1=1; PC4=1; PC5= 0 -> Gain x0.4 = -8dB
86	* PE1=0; PC4=0; PC5= 0 -> Gain x0.5 = -6dB
87	* PE1=0; PC4=0; PC5= 1 -> Gain x1 = 0dB
88	* PE1=0; PC4=1; PC5= 0 -> Gain x2 = +6dB
89	*/
90	static BOOL set_voltage(BYTE channel, BYTE val)
91	{
92	BYTE bits_C, bit_E, mask_C, mask_E;
93
94	if (channel == 0) {
95	mask_C = 0x0E;
96	mask_E = 0x00;
97	bit_E = 0;
98	switch (val) {
99	case 1:
100	bits_C = 0x02;
101	break;
102	case 2:
103	bits_C = 0x06;
104	break;
105	case 5:
106	bits_C = 0x00;
107	break;
108	case 10:
109	bits_C = 0x04;
110	break;
111	case 20:
112	bits_C = 0x08;
113	break;
114	default:
115	return FALSE;
116	}
117	} else if (channel == 1) {
118	mask_C = 0x30;
119	mask_E = 0x02;
120	switch (val) {
121	case 1:
122	bits_C = 0x00;
123	bit_E = 0x02;
124	break;
125	case 2:
126	bits_C = 0x10;
127	bit_E = 0x02;
128	break;
129	case 5:
130	bits_C = 0x00;
131	bit_E = 0x00;
132	break;
133	case 10:
134	bits_C = 0x10;
135	bit_E = 0x00;
136	break;
137	case 20:
138	bits_C = 0x20;
139	bit_E = 0x00;
140	break;
141	default:
142	return FALSE;
143	}
144	} else {
145	return FALSE;
146	}
147	IOC = (IOC & ~mask_C) \| (bits_C & mask_C);
148	IOE = (IOE & ~mask_E) \| (bit_E & mask_E);
149
150	return TRUE;
151	}
152
75ad0fa5 BL	153
	154	/**
	155	* Each LSB in the nibble of the byte controls the coupling per channel.
	156	*
	157	* Setting PE3 disables AC coupling capacitor on CH0.
	158	* Setting PE0 disables AC coupling capacitor on CH1.
	159	*/
	160	static void set_coupling(BYTE coupling_cfg)
	161	{
	162	if (coupling_cfg & 0x01)
	163	IOE \|= 0x08;
	164	else
	165	IOE &= ~0x08;
	166
	167	if (coupling_cfg & 0x10)
	168	IOE \|= 0x01;
	169	else
	170	IOE &= ~0x01;
	171	}
	172
ce1d0a86 BL	173	static BOOL set_numchannels(BYTE numchannels)
	174	{
	175	if (numchannels == 1 \|\| numchannels == 2) {
	176	BYTE fifocfg = 7 + numchannels;
	177	EP2FIFOCFG = fifocfg;
	178	EP6FIFOCFG = fifocfg;
	179	return TRUE;
	180	}
	181
	182	return FALSE;
	183	}
	184
	185	static void clear_fifo(void)
	186	{
	187	GPIFABORT = 0xff;
	188	SYNCDELAY3;
	189	FIFORESET = 0x80;
	190	SYNCDELAY3;
	191	FIFORESET = 0x82;
	192	SYNCDELAY3;
	193	FIFORESET = 0x86;
	194	SYNCDELAY3;
	195	FIFORESET = 0;
	196	}
	197
	198	static void stop_sampling(void)
	199	{
	200	GPIFABORT = 0xff;
	201	SYNCDELAY3;
	202	INPKTEND = (altiface == 0) ? 6 : 2;
	203	}
	204
	205	static void start_sampling(void)
	206	{
	207	int i;
	208
	209	clear_fifo();
	210
	211	for (i = 0; i < 1000; i++);
	212
	213	while (!(GPIFTRIG & 0x80))
	214	;
	215
	216	SYNCDELAY3;
	217	GPIFTCB1 = 0x28;
	218	SYNCDELAY3;
	219	GPIFTCB0 = 0;
	220	GPIFTRIG = (altiface == 0) ? 6 : 4;
	221
	222	}
	223
	224	static void select_interface(BYTE alt)
	225	{
	226	const BYTE *pPacketSize = \
	227	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
	228	+ (9 + (16 * alt) + 9 + 4);
	229
	230	altiface = alt;
	231
	232	if (alt == 0) {
	233	/* Bulk on EP6. */
	234	EP2CFG = 0x00;
	235	EP6CFG = 0xe0;
	236	EP6GPIFFLGSEL = 1;
237	EP6AUTOINLENL = pPacketSize[0];
238	EP6AUTOINLENH = pPacketSize[1];
239	} else {
240	/* Iso on EP2. */
241	EP2CFG = 0xd8;
242	EP6CFG = 0x00;
243	EP2GPIFFLGSEL = 1;
244	EP2AUTOINLENL = pPacketSize[0];
245	EP2AUTOINLENH = pPacketSize[1] & 0x7;
246	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
247	}
248	}
249
250	static const struct samplerate_info {
251	BYTE rate;
252	BYTE wait0;
253	BYTE wait1;
254	BYTE opc0;
255	BYTE opc1;
256	BYTE out0;
257	BYTE ifcfg;
258	} samplerates[] = {
259	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
260	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
261	{ 24, 1, 0, 2, 1, 0x40, 0xea },
262	{ 16, 1, 1, 2, 0, 0x40, 0xea },
263	{ 12, 2, 1, 2, 0, 0x40, 0xea },
264	{ 8, 3, 2, 2, 0, 0x40, 0xea },
265	{ 4, 6, 5, 2, 0, 0x40, 0xea },
266	{ 2, 12, 11, 2, 0, 0x40, 0xea },
267	{ 1, 24, 23, 2, 0, 0x40, 0xea },
268	{ 50, 48, 47, 2, 0, 0x40, 0xea },
269	{ 20, 120, 119, 2, 0, 0x40, 0xea },
270	{ 10, 240, 239, 2, 0, 0x40, 0xea },
271	};
272
273	static BOOL set_samplerate(BYTE rate)
274	{
275	BYTE i = 0;
276
277	while (samplerates[i].rate != rate) {
278	i++;
279	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
280	return FALSE;
281	}
282
283	IFCONFIG = samplerates[i].ifcfg;
284
285	AUTOPTRSETUP = 7;
286	AUTOPTRH2 = 0xE4;
287	AUTOPTRL2 = 0x00;
288
289	/*
290	* The program for low-speed, e.g. 1 MHz, is:
291	* wait 24, CTL2=0, FIFO
292	* wait 23, CTL2=1
293	* jump 0, CTL2=1
294	*
295	* The program for 24 MHz is:
296	* wait 1, CTL2=0, FIFO
297	* jump 0, CTL2=1
298	*
299	* The program for 30/48 MHz is:
300	* jump 0, CTL2=Z, FIFO, LOOP
301	*/
302
303	EXTAUTODAT2 = samplerates[i].wait0;
304	EXTAUTODAT2 = samplerates[i].wait1;
305	EXTAUTODAT2 = 1;
306	EXTAUTODAT2 = 0;
307	EXTAUTODAT2 = 0;
308	EXTAUTODAT2 = 0;
309	EXTAUTODAT2 = 0;
310	EXTAUTODAT2 = 0;
311
312	EXTAUTODAT2 = samplerates[i].opc0;
313	EXTAUTODAT2 = samplerates[i].opc1;
314	EXTAUTODAT2 = 1;
315	EXTAUTODAT2 = 0;
316	EXTAUTODAT2 = 0;
317	EXTAUTODAT2 = 0;
318	EXTAUTODAT2 = 0;
319	EXTAUTODAT2 = 0;
320
321	EXTAUTODAT2 = samplerates[i].out0;
322	EXTAUTODAT2 = 0x44;
323	EXTAUTODAT2 = 0x44;
324	EXTAUTODAT2 = 0x00;
325	EXTAUTODAT2 = 0x00;
326	EXTAUTODAT2 = 0x00;
327	EXTAUTODAT2 = 0x00;
328	EXTAUTODAT2 = 0x00;
329
330	EXTAUTODAT2 = 0;
331	EXTAUTODAT2 = 0;
332	EXTAUTODAT2 = 0;
333	EXTAUTODAT2 = 0;
334	EXTAUTODAT2 = 0;
335	EXTAUTODAT2 = 0;
336	EXTAUTODAT2 = 0;
337	EXTAUTODAT2 = 0;
338
339	for (i = 0; i < 96; i++)
340	EXTAUTODAT2 = 0;
341
342	return TRUE;
343	}
344
345	/* Set alt_ifc to the current alt interface for ifc. /
346	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
347	{
348	(void)ifc;
349
350	*alt_ifc = altiface;
351
352	return TRUE;
353	}
354
355	/*
356	* Return TRUE if you set the interface requested.
357	*
358	* Note: This function should reconfigure and reset the endpoints
359	* according to the interface descriptors you provided.
360	*/
361	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
362	{
363	if (ifc == 0)
364	select_interface(alt_ifc);
365
366	return TRUE;
367	}
368
369	BYTE handle_get_configuration(void)
370	{
371	/* We only support configuration 0. */
372	return 0;
373	}
374
375	BOOL handle_set_configuration(BYTE cfg)
376	{
377	/* We only support configuration 0. */
378	(void)cfg;
379
380	return TRUE;
381	}
382
383	BOOL handle_vendorcommand(BYTE cmd)
384	{
385	stop_sampling();
386
387	/* Clear EP0BCH/L for each valid command. */
75ad0fa5	388	if (cmd >= 0xe0 && cmd <= 0xe5) {
ce1d0a86 BL	389	EP0BCH = 0;
	390	EP0BCL = 0;
	391	while (EP0CS & bmEPBUSY);
	392	}
	393
	394	switch (cmd) {
	395	case 0xe0:
	396	case 0xe1:
	397	set_voltage(cmd - 0xe0, EP0BUF[0]);
	398	return TRUE;
	399	case 0xe2:
	400	set_samplerate(EP0BUF[0]);
	401	return TRUE;
	402	case 0xe3:
	403	if (EP0BUF[0] == 1)
	404	start_sampling();
	405	return TRUE;
	406	case 0xe4:
	407	set_numchannels(EP0BUF[0]);
	408	return TRUE;
75ad0fa5 BL	409	case 0xe5:
	410	set_coupling(EP0BUF[0]);
	411	return TRUE;
ce1d0a86 BL	412	}
	413
	414	return FALSE; /* Not handled by handlers. */
	415	}
	416
	417	static void init(void)
	418	{
	419	EP4CFG = 0;
	420	EP8CFG = 0;
	421
	422	/* In idle mode tristate all outputs. */
	423	GPIFIDLECTL = 0x00;
	424	GPIFCTLCFG = 0x80;
	425	GPIFWFSELECT = 0x00;
	426	GPIFREADYSTAT = 0x00;
	427
	428	stop_sampling();
	429
	430	set_voltage(0, 1);
	431	set_voltage(1, 1);
	432	set_samplerate(1);
	433	set_numchannels(2);
	434	select_interface(0);
	435	}
	436
	437	static void main(void)
	438	{
	439	/* Save energy. */
	440	SETCPUFREQ(CLK_12M);
	441
	442	init();
	443
	444	/* Set up interrupts. */
	445	USE_USB_INTS();
	446
	447	ENABLE_SUDAV();
	448	ENABLE_USBRESET();
	449	ENABLE_HISPEED();
	450	ENABLE_SUSPEND();
	451	ENABLE_RESUME();
	452
	453	/* Global (8051) interrupt enable. */
	454	EA = 1;
	455
	456	/* Init timer2. */
	457	RCAP2L = -1000 & 0xff;
	458	RCAP2H = (-1000 >> 8) & 0xff;
	459	T2CON = 0;
	460	ET2 = 1;
	461	TR2 = 1;
	462
	463	RENUMERATE_UNCOND();
	464
	465	PORTCCFG = 0;
	466	PORTACFG = 0;
	467	PORTECFG = 0;
	468	OEE = 0xFF;
	469	OEC = 0xff;
	470	OEA = 0x80;
	471
	472	PA7 = 1;
	473
	474	while (TRUE) {
	475	if (dosud) {
476	dosud = FALSE;
477	handle_setupdata();
478	}
479
480	if (dosuspend) {
481	dosuspend = FALSE;
482	do {
483	/* Make sure ext wakeups are cleared. */
484	WAKEUPCS \|= bmWU\|bmWU2;
485	SUSPEND = 1;
486	PCON \|= 1;
487	__asm
488	nop
489	nop
490	nop
491	nop
492	nop
493	nop
494	nop
495	__endasm;
496	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
497
498	/* Resume (TRM 6.4). */
499	if (REMOTE_WAKEUP()) {
500	delay(5);
501	USBCS \|= bmSIGRESUME;
502	delay(15);
503	USBCS &= ~bmSIGRESUME;
504	}
505	}
506	}
507	}