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sr: make struct drv_context global
[libsigrok.git] / hardware / openbench-logic-sniffer / ols.c
CommitLineData
a1bb33af
UH
1/*
2 * This file is part of the sigrok project.
3 *
c73d2ea4 4 * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
a1bb33af
UH
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <stdio.h>
21#include <stdint.h>
22#include <stdlib.h>
23#include <sys/types.h>
24#include <sys/stat.h>
25#include <fcntl.h>
26#include <unistd.h>
a9f54bcd
UH
27#ifdef _WIN32
28#include <windows.h>
29#else
a1bb33af 30#include <termios.h>
926b866c 31#endif
a1bb33af
UH
32#include <string.h>
33#include <sys/time.h>
34#include <inttypes.h>
926b866c
UH
35#ifdef _WIN32
36/* TODO */
37#else
6937bb75 38#include <arpa/inet.h>
926b866c 39#endif
a1bb33af 40#include <glib.h>
45c59c8b
BV
41#include "libsigrok.h"
42#include "libsigrok-internal.h"
4fe9a6da 43#include "ols.h"
a1bb33af 44
1fdb75e1
UH
45#ifdef _WIN32
46#define O_NONBLOCK FIONBIO
47#endif
48
915f7cc8 49static const int hwcaps[] = {
5a2326a7
UH
50 SR_HWCAP_LOGIC_ANALYZER,
51 SR_HWCAP_SAMPLERATE,
52 SR_HWCAP_CAPTURE_RATIO,
53 SR_HWCAP_LIMIT_SAMPLES,
3a4d09c0 54 SR_HWCAP_RLE,
43fc7885 55 0,
a1bb33af
UH
56};
57
d261dbbf 58/* Probes are numbered 0-31 (on the PCB silkscreen). */
c37d2b1b 59static const char *probe_names[NUM_PROBES + 1] = {
464d12c7
KS
60 "0",
61 "1",
62 "2",
63 "3",
64 "4",
65 "5",
66 "6",
67 "7",
68 "8",
69 "9",
70 "10",
71 "11",
72 "12",
73 "13",
74 "14",
75 "15",
76 "16",
77 "17",
78 "18",
79 "19",
80 "20",
81 "21",
82 "22",
83 "23",
84 "24",
85 "25",
86 "26",
87 "27",
88 "28",
89 "29",
90 "30",
91 "31",
92 NULL,
93};
94
4fe9a6da 95/* default supported samplerates, can be overridden by device metadata */
a533743d 96static const struct sr_samplerates samplerates = {
c9140419 97 SR_HZ(10),
59df0c77 98 SR_MHZ(200),
c9140419
UH
99 SR_HZ(1),
100 NULL,
a1bb33af
UH
101};
102
e5e81856
BV
103SR_PRIV struct sr_dev_driver ols_driver_info;
104static struct sr_dev_driver *odi = &ols_driver_info;
a1bb33af 105
6937bb75 106static int send_shortcommand(int fd, uint8_t command)
a1bb33af
UH
107{
108 char buf[1];
109
b08024a8 110 sr_dbg("ols: sending cmd 0x%.2x", command);
a1bb33af 111 buf[0] = command;
2119ab03 112 if (serial_write(fd, buf, 1) != 1)
e46b8fb1 113 return SR_ERR;
a1bb33af 114
e46b8fb1 115 return SR_OK;
a1bb33af
UH
116}
117
6937bb75 118static int send_longcommand(int fd, uint8_t command, uint32_t data)
a1bb33af
UH
119{
120 char buf[5];
121
b08024a8 122 sr_dbg("ols: sending cmd 0x%.2x data 0x%.8x", command, data);
a1bb33af 123 buf[0] = command;
6937bb75
BV
124 buf[1] = (data & 0xff000000) >> 24;
125 buf[2] = (data & 0xff0000) >> 16;
126 buf[3] = (data & 0xff00) >> 8;
127 buf[4] = data & 0xff;
2119ab03 128 if (serial_write(fd, buf, 5) != 5)
e46b8fb1 129 return SR_ERR;
a1bb33af 130
e46b8fb1 131 return SR_OK;
a1bb33af
UH
132}
133
014359e3 134static int configure_probes(const struct sr_dev_inst *sdi)
a1bb33af 135{
014359e3 136 struct dev_context *devc;
1b79df2f
JH
137 const struct sr_probe *probe;
138 const GSList *l;
6937bb75 139 int probe_bit, stage, i;
a1bb33af
UH
140 char *tc;
141
014359e3
BV
142 devc = sdi->priv;
143
fefc4b85 144 devc->probe_mask = 0;
43fc7885 145 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
fefc4b85
BV
146 devc->trigger_mask[i] = 0;
147 devc->trigger_value[i] = 0;
a1bb33af
UH
148 }
149
fefc4b85 150 devc->num_stages = 0;
014359e3 151 for (l = sdi->probes; l; l = l->next) {
1b79df2f 152 probe = (const struct sr_probe *)l->data;
43fc7885 153 if (!probe->enabled)
6937bb75
BV
154 continue;
155
43fc7885
UH
156 /*
157 * Set up the probe mask for later configuration into the
158 * flag register.
159 */
b35c8293 160 probe_bit = 1 << (probe->index);
fefc4b85 161 devc->probe_mask |= probe_bit;
6937bb75 162
a803c0db 163 if (!probe->trigger)
6937bb75
BV
164 continue;
165
43fc7885 166 /* Configure trigger mask and value. */
6937bb75 167 stage = 0;
43fc7885 168 for (tc = probe->trigger; tc && *tc; tc++) {
fefc4b85 169 devc->trigger_mask[stage] |= probe_bit;
43fc7885 170 if (*tc == '1')
fefc4b85 171 devc->trigger_value[stage] |= probe_bit;
6937bb75 172 stage++;
43fc7885
UH
173 if (stage > 3)
174 /*
175 * TODO: Only supporting parallel mode, with
176 * up to 4 stages.
177 */
e46b8fb1 178 return SR_ERR;
a1bb33af 179 }
fefc4b85
BV
180 if (stage > devc->num_stages)
181 devc->num_stages = stage;
a1bb33af
UH
182 }
183
e46b8fb1 184 return SR_OK;
a1bb33af
UH
185}
186
a803c0db 187static uint32_t reverse16(uint32_t in)
6937bb75
BV
188{
189 uint32_t out;
190
a803c0db
BV
191 out = (in & 0xff) << 8;
192 out |= (in & 0xff00) >> 8;
193 out |= (in & 0xff0000) << 8;
194 out |= (in & 0xff000000) >> 8;
195
196 return out;
197}
198
199static uint32_t reverse32(uint32_t in)
200{
201 uint32_t out;
202
203 out = (in & 0xff) << 24;
204 out |= (in & 0xff00) << 8;
205 out |= (in & 0xff0000) >> 8;
206 out |= (in & 0xff000000) >> 24;
207
208 return out;
6937bb75
BV
209}
210
fefc4b85 211static struct dev_context *ols_dev_new(void)
4fe9a6da 212{
fefc4b85 213 struct dev_context *devc;
4fe9a6da 214
fefc4b85
BV
215 /* TODO: Is 'devc' ever g_free()'d? */
216 if (!(devc = g_try_malloc0(sizeof(struct dev_context)))) {
217 sr_err("ols: %s: devc malloc failed", __func__);
b53738ba
UH
218 return NULL;
219 }
220
fefc4b85
BV
221 devc->trigger_at = -1;
222 devc->probe_mask = 0xffffffff;
223 devc->cur_samplerate = SR_KHZ(200);
224 devc->serial = NULL;
4fe9a6da 225
fefc4b85 226 return devc;
4fe9a6da
BV
227}
228
d68e2d1a 229static struct sr_dev_inst *get_metadata(int fd)
4fe9a6da 230{
d68e2d1a 231 struct sr_dev_inst *sdi;
fefc4b85 232 struct dev_context *devc;
10e5cbed
BV
233 struct sr_probe *probe;
234 uint32_t tmp_int, ui;
4fe9a6da 235 uint8_t key, type, token;
bb7ef793 236 GString *tmp_str, *devname, *version;
10e5cbed 237 guchar tmp_c;
4fe9a6da 238
d3683c42 239 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE, NULL, NULL, NULL);
2efc5948 240 sdi->driver = odi;
fefc4b85
BV
241 devc = ols_dev_new();
242 sdi->priv = devc;
4fe9a6da 243
bb7ef793 244 devname = g_string_new("");
4fe9a6da
BV
245 version = g_string_new("");
246
247 key = 0xff;
248 while (key) {
249 if (serial_read(fd, &key, 1) != 1 || key == 0x00)
250 break;
251 type = key >> 5;
252 token = key & 0x1f;
253 switch (type) {
254 case 0:
255 /* NULL-terminated string */
256 tmp_str = g_string_new("");
257 while (serial_read(fd, &tmp_c, 1) == 1 && tmp_c != '\0')
258 g_string_append_c(tmp_str, tmp_c);
b08024a8
UH
259 sr_dbg("ols: got metadata key 0x%.2x value '%s'",
260 key, tmp_str->str);
4fe9a6da
BV
261 switch (token) {
262 case 0x01:
263 /* Device name */
bb7ef793 264 devname = g_string_append(devname, tmp_str->str);
4fe9a6da
BV
265 break;
266 case 0x02:
267 /* FPGA firmware version */
268 if (version->len)
269 g_string_append(version, ", ");
270 g_string_append(version, "FPGA version ");
271 g_string_append(version, tmp_str->str);
272 break;
273 case 0x03:
274 /* Ancillary version */
275 if (version->len)
276 g_string_append(version, ", ");
277 g_string_append(version, "Ancillary version ");
278 g_string_append(version, tmp_str->str);
279 break;
280 default:
b08024a8
UH
281 sr_info("ols: unknown token 0x%.2x: '%s'",
282 token, tmp_str->str);
4fe9a6da
BV
283 break;
284 }
285 g_string_free(tmp_str, TRUE);
286 break;
287 case 1:
288 /* 32-bit unsigned integer */
289 if (serial_read(fd, &tmp_int, 4) != 4)
290 break;
291 tmp_int = reverse32(tmp_int);
b08024a8
UH
292 sr_dbg("ols: got metadata key 0x%.2x value 0x%.8x",
293 key, tmp_int);
4fe9a6da
BV
294 switch (token) {
295 case 0x00:
296 /* Number of usable probes */
10e5cbed
BV
297 for (ui = 0; ui < tmp_int; ui++) {
298 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
299 probe_names[ui])))
300 return 0;
301 sdi->probes = g_slist_append(sdi->probes, probe);
302 }
4fe9a6da
BV
303 break;
304 case 0x01:
305 /* Amount of sample memory available (bytes) */
fefc4b85 306 devc->max_samples = tmp_int;
4fe9a6da
BV
307 break;
308 case 0x02:
309 /* Amount of dynamic memory available (bytes) */
310 /* what is this for? */
311 break;
312 case 0x03:
313 /* Maximum sample rate (hz) */
fefc4b85 314 devc->max_samplerate = tmp_int;
4fe9a6da
BV
315 break;
316 case 0x04:
317 /* protocol version */
fefc4b85 318 devc->protocol_version = tmp_int;
4fe9a6da
BV
319 break;
320 default:
b08024a8
UH
321 sr_info("ols: unknown token 0x%.2x: 0x%.8x",
322 token, tmp_int);
4fe9a6da
BV
323 break;
324 }
325 break;
326 case 2:
327 /* 8-bit unsigned integer */
328 if (serial_read(fd, &tmp_c, 1) != 1)
329 break;
b08024a8
UH
330 sr_dbg("ols: got metadata key 0x%.2x value 0x%.2x",
331 key, tmp_c);
4fe9a6da
BV
332 switch (token) {
333 case 0x00:
334 /* Number of usable probes */
10e5cbed
BV
335 for (ui = 0; ui < tmp_c; ui++) {
336 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
337 probe_names[ui])))
338 return 0;
339 sdi->probes = g_slist_append(sdi->probes, probe);
340 }
4fe9a6da
BV
341 break;
342 case 0x01:
343 /* protocol version */
fefc4b85 344 devc->protocol_version = tmp_c;
4fe9a6da
BV
345 break;
346 default:
b08024a8
UH
347 sr_info("ols: unknown token 0x%.2x: 0x%.2x",
348 token, tmp_c);
4fe9a6da
BV
349 break;
350 }
351 break;
352 default:
353 /* unknown type */
354 break;
355 }
356 }
357
bb7ef793 358 sdi->model = devname->str;
4fe9a6da 359 sdi->version = version->str;
bb7ef793 360 g_string_free(devname, FALSE);
4fe9a6da
BV
361 g_string_free(version, FALSE);
362
363 return sdi;
364}
365
40dda2c3 366static int hw_init(void)
61136ea6 367{
fefc4b85 368 struct drv_context *drvc;
61136ea6 369
fefc4b85
BV
370 if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
371 sr_err("ols: driver context malloc failed.");
372 return SR_ERR;
373 }
374 odi->priv = drvc;
61136ea6
BV
375
376 return SR_OK;
377}
378
10e5cbed 379static GSList *hw_scan(GSList *options)
a1bb33af 380{
d68e2d1a 381 struct sr_dev_inst *sdi;
fefc4b85
BV
382 struct drv_context *drvc;
383 struct dev_context *devc;
10e5cbed
BV
384 struct sr_probe *probe;
385 GSList *devices, *ports, *l;
4fe9a6da 386 GPollFD *fds, probefd;
10e5cbed 387 int devcnt, final_devcnt, num_ports, fd, ret, i, j;
bb7ef793 388 char buf[8], **dev_names, **serial_params;
a1bb33af 389
10e5cbed 390 (void)options;
fefc4b85 391 drvc = odi->priv;
c0a4b971 392 final_devcnt = 0;
10e5cbed 393 devices = NULL;
c0a4b971 394
40dda2c3
BV
395 /* Scan all serial ports. */
396 ports = list_serial_ports();
a1bb33af 397 num_ports = g_slist_length(ports);
c0a4b971
UH
398
399 if (!(fds = g_try_malloc0(num_ports * sizeof(GPollFD)))) {
400 sr_err("ols: %s: fds malloc failed", __func__);
401 goto hw_init_free_ports; /* TODO: SR_ERR_MALLOC. */
402 }
403
bb7ef793
UH
404 if (!(dev_names = g_try_malloc(num_ports * sizeof(char *)))) {
405 sr_err("ols: %s: dev_names malloc failed", __func__);
c0a4b971
UH
406 goto hw_init_free_fds; /* TODO: SR_ERR_MALLOC. */
407 }
408
409 if (!(serial_params = g_try_malloc(num_ports * sizeof(char *)))) {
410 sr_err("ols: %s: serial_params malloc failed", __func__);
bb7ef793 411 goto hw_init_free_dev_names; /* TODO: SR_ERR_MALLOC. */
c0a4b971
UH
412 }
413
a1bb33af 414 devcnt = 0;
43fc7885
UH
415 for (l = ports; l; l = l->next) {
416 /* The discovery procedure is like this: first send the Reset
417 * command (0x00) 5 times, since the device could be anywhere
418 * in a 5-byte command. Then send the ID command (0x02).
419 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
420 * have a match.
421 *
422 * Since it may take the device a while to respond at 115Kb/s,
423 * we do all the sending first, then wait for all of them to
424 * respond with g_poll().
a1bb33af 425 */
b08024a8 426 sr_info("ols: probing %s...", (char *)l->data);
d02a535e 427 fd = serial_open(l->data, O_RDWR | O_NONBLOCK);
43fc7885 428 if (fd != -1) {
d02a535e 429 serial_params[devcnt] = serial_backup_params(fd);
f8c1fcda 430 serial_set_params(fd, 115200, 8, SERIAL_PARITY_NONE, 1, 2);
e46b8fb1 431 ret = SR_OK;
43fc7885
UH
432 for (i = 0; i < 5; i++) {
433 if ((ret = send_shortcommand(fd,
e46b8fb1 434 CMD_RESET)) != SR_OK) {
43fc7885 435 /* Serial port is not writable. */
6937bb75
BV
436 break;
437 }
a1bb33af 438 }
e46b8fb1 439 if (ret != SR_OK) {
43fc7885
UH
440 serial_restore_params(fd,
441 serial_params[devcnt]);
d02a535e 442 serial_close(fd);
6937bb75 443 continue;
d02a535e 444 }
6937bb75
BV
445 send_shortcommand(fd, CMD_ID);
446 fds[devcnt].fd = fd;
447 fds[devcnt].events = G_IO_IN;
bb7ef793 448 dev_names[devcnt] = g_strdup(l->data);
6937bb75 449 devcnt++;
a1bb33af 450 }
133a37bf 451 g_free(l->data);
a1bb33af
UH
452 }
453
5b15b41e
PS
454 /* 2ms isn't enough for reliable transfer with pl2303, let's try 10 */
455 usleep(10000);
a1bb33af 456
a1bb33af 457 g_poll(fds, devcnt, 1);
4fe9a6da 458
43fc7885 459 for (i = 0; i < devcnt; i++) {
4fe9a6da
BV
460 if (fds[i].revents != G_IO_IN)
461 continue;
462 if (serial_read(fds[i].fd, buf, 4) != 4)
463 continue;
464 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
465 continue;
466
467 /* definitely using the OLS protocol, check if it supports
468 * the metadata command
469 */
470 send_shortcommand(fds[i].fd, CMD_METADATA);
471 probefd.fd = fds[i].fd;
472 probefd.events = G_IO_IN;
473 if (g_poll(&probefd, 1, 10) > 0) {
474 /* got metadata */
475 sdi = get_metadata(fds[i].fd);
476 sdi->index = final_devcnt;
fefc4b85 477 devc = sdi->priv;
4fe9a6da
BV
478 } else {
479 /* not an OLS -- some other board that uses the sump protocol */
d3683c42 480 sdi = sr_dev_inst_new(final_devcnt, SR_ST_INACTIVE,
4fe9a6da 481 "Sump", "Logic Analyzer", "v1.0");
2efc5948 482 sdi->driver = odi;
fefc4b85 483 devc = ols_dev_new();
10e5cbed
BV
484 for (j = 0; j < 32; j++) {
485 if (!(probe = sr_probe_new(j, SR_PROBE_LOGIC, TRUE,
486 probe_names[j])))
487 return 0;
488 sdi->probes = g_slist_append(sdi->probes, probe);
489 }
fefc4b85 490 sdi->priv = devc;
a1bb33af 491 }
fefc4b85
BV
492 devc->serial = sr_serial_dev_inst_new(dev_names[i], -1);
493 drvc->instances = g_slist_append(drvc->instances, sdi);
e5e81856
BV
494 devices = g_slist_append(devices, sdi);
495
4fe9a6da
BV
496 final_devcnt++;
497 serial_close(fds[i].fd);
498 fds[i].fd = 0;
4fe9a6da
BV
499 }
500
501 /* clean up after all the probing */
502 for (i = 0; i < devcnt; i++) {
43fc7885 503 if (fds[i].fd != 0) {
d02a535e
BV
504 serial_restore_params(fds[i].fd, serial_params[i]);
505 serial_close(fds[i].fd);
6937bb75 506 }
133a37bf 507 g_free(serial_params[i]);
bb7ef793 508 g_free(dev_names[i]);
a1bb33af
UH
509 }
510
c0a4b971 511 g_free(serial_params);
bb7ef793
UH
512hw_init_free_dev_names:
513 g_free(dev_names);
c0a4b971
UH
514hw_init_free_fds:
515 g_free(fds);
516hw_init_free_ports:
a1bb33af
UH
517 g_slist_free(ports);
518
10e5cbed 519 return devices;
a1bb33af
UH
520}
521
811deee4
BV
522static GSList *hw_dev_list(void)
523{
524 struct drv_context *drvc;
525
526 drvc = odi->priv;
527
528 return drvc->instances;
529}
530
25a0f108 531static int hw_dev_open(struct sr_dev_inst *sdi)
a1bb33af 532{
fefc4b85 533 struct dev_context *devc;
a1bb33af 534
fefc4b85 535 devc = sdi->priv;
69890f73 536
fefc4b85
BV
537 devc->serial->fd = serial_open(devc->serial->port, O_RDWR);
538 if (devc->serial->fd == -1)
e46b8fb1 539 return SR_ERR;
a1bb33af 540
5a2326a7 541 sdi->status = SR_ST_ACTIVE;
a1bb33af 542
e46b8fb1 543 return SR_OK;
a1bb33af
UH
544}
545
25a0f108 546static int hw_dev_close(struct sr_dev_inst *sdi)
a1bb33af 547{
fefc4b85 548 struct dev_context *devc;
a1bb33af 549
fefc4b85 550 devc = sdi->priv;
69890f73 551
fefc4b85
BV
552 if (devc->serial->fd != -1) {
553 serial_close(devc->serial->fd);
554 devc->serial->fd = -1;
5a2326a7 555 sdi->status = SR_ST_INACTIVE;
a1bb33af 556 }
697785d1
UH
557
558 return SR_OK;
a1bb33af
UH
559}
560
57ab7d9f 561static int hw_cleanup(void)
a1bb33af
UH
562{
563 GSList *l;
d68e2d1a 564 struct sr_dev_inst *sdi;
fefc4b85
BV
565 struct drv_context *drvc;
566 struct dev_context *devc;
57ab7d9f 567 int ret = SR_OK;
a1bb33af 568
fefc4b85
BV
569 if (!(drvc = odi->priv))
570 return SR_OK;
571
8722c31e 572 /* Properly close and free all devices. */
fefc4b85 573 for (l = drvc->instances; l; l = l->next) {
57ab7d9f
UH
574 if (!(sdi = l->data)) {
575 /* Log error, but continue cleaning up the rest. */
576 sr_err("ols: %s: sdi was NULL, continuing", __func__);
577 ret = SR_ERR_BUG;
578 continue;
579 }
fefc4b85 580 if (!(devc = sdi->priv)) {
57ab7d9f
UH
581 /* Log error, but continue cleaning up the rest. */
582 sr_err("ols: %s: sdi->priv was NULL, continuing",
583 __func__);
584 ret = SR_ERR_BUG;
585 continue;
586 }
587 /* TODO: Check for serial != NULL. */
fefc4b85
BV
588 if (devc->serial->fd != -1)
589 serial_close(devc->serial->fd);
590 sr_serial_dev_inst_free(devc->serial);
d3683c42 591 sr_dev_inst_free(sdi);
a1bb33af 592 }
fefc4b85
BV
593 g_slist_free(drvc->instances);
594 drvc->instances = NULL;
57ab7d9f
UH
595
596 return ret;
a1bb33af
UH
597}
598
dddfb3db
BV
599static int hw_info_get(int info_id, const void **data,
600 const struct sr_dev_inst *sdi)
a1bb33af 601{
fefc4b85 602 struct dev_context *devc;
a1bb33af 603
dddfb3db 604 switch (info_id) {
2ca4465b
BV
605 case SR_DI_HWCAPS:
606 *data = hwcaps;
607 break;
5a2326a7 608 case SR_DI_NUM_PROBES:
dddfb3db 609 *data = GINT_TO_POINTER(1);
a1bb33af 610 break;
464d12c7 611 case SR_DI_PROBE_NAMES:
dddfb3db 612 *data = probe_names;
464d12c7 613 break;
5a2326a7 614 case SR_DI_SAMPLERATES:
dddfb3db 615 *data = &samplerates;
a1bb33af 616 break;
5a2326a7 617 case SR_DI_TRIGGER_TYPES:
dddfb3db 618 *data = (char *)TRIGGER_TYPES;
a1bb33af 619 break;
5a2326a7 620 case SR_DI_CUR_SAMPLERATE:
dddfb3db 621 if (sdi) {
fefc4b85
BV
622 devc = sdi->priv;
623 *data = &devc->cur_samplerate;
dddfb3db
BV
624 } else
625 return SR_ERR;
a1bb33af 626 break;
dddfb3db
BV
627 default:
628 return SR_ERR_ARG;
a1bb33af
UH
629 }
630
dddfb3db 631 return SR_OK;
a1bb33af
UH
632}
633
6f4b1868 634static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
a1bb33af 635{
fefc4b85 636 struct dev_context *devc;
a1bb33af 637
fefc4b85
BV
638 devc = sdi->priv;
639 if (devc->max_samplerate) {
640 if (samplerate > devc->max_samplerate)
4fe9a6da
BV
641 return SR_ERR_SAMPLERATE;
642 } else if (samplerate < samplerates.low || samplerate > samplerates.high)
e46b8fb1 643 return SR_ERR_SAMPLERATE;
a1bb33af 644
43fc7885 645 if (samplerate > CLOCK_RATE) {
fefc4b85
BV
646 devc->flag_reg |= FLAG_DEMUX;
647 devc->cur_samplerate_divider = (CLOCK_RATE * 2 / samplerate) - 1;
43fc7885 648 } else {
fefc4b85
BV
649 devc->flag_reg &= ~FLAG_DEMUX;
650 devc->cur_samplerate_divider = (CLOCK_RATE / samplerate) - 1;
a1bb33af 651 }
a1bb33af 652
7583b99d
GM
653 /* Calculate actual samplerate used and complain if it is different
654 * from the requested.
655 */
fefc4b85
BV
656 devc->cur_samplerate = CLOCK_RATE / (devc->cur_samplerate_divider + 1);
657 if (devc->flag_reg & FLAG_DEMUX)
658 devc->cur_samplerate *= 2;
659 if (devc->cur_samplerate != samplerate)
133a37bf 660 sr_err("ols: can't match samplerate %" PRIu64 ", using %"
fefc4b85 661 PRIu64, samplerate, devc->cur_samplerate);
7583b99d 662
e46b8fb1 663 return SR_OK;
a1bb33af
UH
664}
665
6f4b1868
BV
666static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
667 const void *value)
a1bb33af 668{
fefc4b85 669 struct dev_context *devc;
a1bb33af 670 int ret;
1b79df2f 671 const uint64_t *tmp_u64;
a1bb33af 672
fefc4b85 673 devc = sdi->priv;
a1bb33af 674
5a2326a7 675 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 676 return SR_ERR;
a1bb33af 677
ffedd0bf 678 switch (hwcap) {
5a2326a7 679 case SR_HWCAP_SAMPLERATE:
1b79df2f 680 ret = set_samplerate(sdi, *(const uint64_t *)value);
a803c0db 681 break;
5a2326a7 682 case SR_HWCAP_LIMIT_SAMPLES:
2458ea65 683 tmp_u64 = value;
574ce498 684 if (*tmp_u64 < MIN_NUM_SAMPLES)
e46b8fb1 685 return SR_ERR;
fefc4b85 686 if (*tmp_u64 > devc->max_samples)
133a37bf 687 sr_err("ols: sample limit exceeds hw max");
fefc4b85
BV
688 devc->limit_samples = *tmp_u64;
689 sr_info("ols: sample limit %" PRIu64, devc->limit_samples);
e46b8fb1 690 ret = SR_OK;
a803c0db 691 break;
5a2326a7 692 case SR_HWCAP_CAPTURE_RATIO:
fefc4b85
BV
693 devc->capture_ratio = *(const uint64_t *)value;
694 if (devc->capture_ratio < 0 || devc->capture_ratio > 100) {
695 devc->capture_ratio = 0;
e46b8fb1 696 ret = SR_ERR;
43fc7885 697 } else
e46b8fb1 698 ret = SR_OK;
a803c0db 699 break;
3a4d09c0 700 case SR_HWCAP_RLE:
4d436e71 701 if (GPOINTER_TO_INT(value)) {
3a4d09c0 702 sr_info("ols: enabling RLE");
fefc4b85 703 devc->flag_reg |= FLAG_RLE;
3a4d09c0
GM
704 }
705 ret = SR_OK;
706 break;
a803c0db 707 default:
e46b8fb1 708 ret = SR_ERR;
43fc7885 709 }
a1bb33af
UH
710
711 return ret;
712}
713
26bf9d56
BV
714static void abort_acquisition(const struct sr_dev_inst *sdi)
715{
716 struct sr_datafeed_packet packet;
717 struct dev_context *devc;
718
719 devc = sdi->priv;
720 sr_source_remove(devc->serial->fd);
721
722 /* Terminate session */
723 packet.type = SR_DF_END;
724 sr_session_send(sdi, &packet);
725
726}
727
728
729
1f9813eb 730static int receive_data(int fd, int revents, void *cb_data)
a1bb33af 731{
b9c735a2 732 struct sr_datafeed_packet packet;
9c939c51 733 struct sr_datafeed_logic logic;
d68e2d1a 734 struct sr_dev_inst *sdi;
fefc4b85
BV
735 struct drv_context *drvc;
736 struct dev_context *devc;
4fe9a6da 737 GSList *l;
3a4d09c0
GM
738 int num_channels, offset, i, j;
739 unsigned char byte;
a1bb33af 740
fefc4b85
BV
741 drvc = odi->priv;
742
743 /* Find this device's devc struct by its fd. */
744 devc = NULL;
745 for (l = drvc->instances; l; l = l->next) {
4fe9a6da 746 sdi = l->data;
fefc4b85
BV
747 devc = sdi->priv;
748 if (devc->serial->fd == fd) {
4fe9a6da
BV
749 break;
750 }
fefc4b85 751 devc = NULL;
4fe9a6da 752 }
fefc4b85 753 if (!devc)
ea9cfed7 754 /* Shouldn't happen. */
4fe9a6da
BV
755 return TRUE;
756
fefc4b85 757 if (devc->num_transfers++ == 0) {
43fc7885
UH
758 /*
759 * First time round, means the device started sending data,
760 * and will not stop until done. If it stops sending for
761 * longer than it takes to send a byte, that means it's
762 * finished. We'll double that to 30ms to be sure...
a1bb33af 763 */
6f1be0a2 764 sr_source_remove(fd);
1f9813eb 765 sr_source_add(fd, G_IO_IN, 30, receive_data, cb_data);
fefc4b85
BV
766 devc->raw_sample_buf = g_try_malloc(devc->limit_samples * 4);
767 if (!devc->raw_sample_buf) {
768 sr_err("ols: %s: devc->raw_sample_buf malloc failed",
c0a4b971
UH
769 __func__);
770 return FALSE;
771 }
a803c0db 772 /* fill with 1010... for debugging */
fefc4b85 773 memset(devc->raw_sample_buf, 0x82, devc->limit_samples * 4);
a1bb33af
UH
774 }
775
6937bb75 776 num_channels = 0;
43fc7885 777 for (i = 0x20; i > 0x02; i /= 2) {
fefc4b85 778 if ((devc->flag_reg & i) == 0)
6937bb75 779 num_channels++;
43fc7885 780 }
6937bb75 781
3a4d09c0 782 if (revents == G_IO_IN) {
2119ab03 783 if (serial_read(fd, &byte, 1) != 1)
a1bb33af
UH
784 return FALSE;
785
baf1d714 786 /* Ignore it if we've read enough. */
fefc4b85 787 if (devc->num_samples >= devc->limit_samples)
baf1d714 788 return TRUE;
3a4d09c0 789
fefc4b85 790 devc->sample[devc->num_bytes++] = byte;
b08024a8 791 sr_dbg("ols: received byte 0x%.2x", byte);
fefc4b85 792 if (devc->num_bytes == num_channels) {
43fc7885 793 /* Got a full sample. */
b08024a8 794 sr_dbg("ols: received sample 0x%.*x",
fefc4b85
BV
795 devc->num_bytes * 2, *(int *)devc->sample);
796 if (devc->flag_reg & FLAG_RLE) {
43fc7885
UH
797 /*
798 * In RLE mode -1 should never come in as a
799 * sample, because bit 31 is the "count" flag.
43fc7885 800 */
fefc4b85
BV
801 if (devc->sample[devc->num_bytes - 1] & 0x80) {
802 devc->sample[devc->num_bytes - 1] &= 0x7f;
baf1d714
UH
803 /*
804 * FIXME: This will only work on
805 * little-endian systems.
a1bb33af 806 */
fefc4b85
BV
807 devc->rle_count = *(int *)(devc->sample);
808 sr_dbg("ols: RLE count = %d", devc->rle_count);
809 devc->num_bytes = 0;
3a4d09c0 810 return TRUE;
baf1d714 811 }
3a4d09c0 812 }
fefc4b85
BV
813 devc->num_samples += devc->rle_count + 1;
814 if (devc->num_samples > devc->limit_samples) {
baf1d714 815 /* Save us from overrunning the buffer. */
fefc4b85
BV
816 devc->rle_count -= devc->num_samples - devc->limit_samples;
817 devc->num_samples = devc->limit_samples;
a1bb33af
UH
818 }
819
43fc7885
UH
820 if (num_channels < 4) {
821 /*
822 * Some channel groups may have been turned
823 * off, to speed up transfer between the
824 * hardware and the PC. Expand that here before
825 * submitting it over the session bus --
826 * whatever is listening on the bus will be
827 * expecting a full 32-bit sample, based on
828 * the number of probes.
6937bb75
BV
829 */
830 j = 0;
fefc4b85 831 memset(devc->tmp_sample, 0, 4);
43fc7885 832 for (i = 0; i < 4; i++) {
fefc4b85 833 if (((devc->flag_reg >> 2) & (1 << i)) == 0) {
43fc7885
UH
834 /*
835 * This channel group was
836 * enabled, copy from received
837 * sample.
838 */
fefc4b85 839 devc->tmp_sample[i] = devc->sample[j++];
6937bb75
BV
840 }
841 }
fefc4b85
BV
842 memcpy(devc->sample, devc->tmp_sample, 4);
843 sr_dbg("ols: full sample 0x%.8x", *(int *)devc->sample);
6937bb75
BV
844 }
845
a803c0db
BV
846 /* the OLS sends its sample buffer backwards.
847 * store it in reverse order here, so we can dump
848 * this on the session bus later.
849 */
fefc4b85
BV
850 offset = (devc->limit_samples - devc->num_samples) * 4;
851 for (i = 0; i <= devc->rle_count; i++) {
852 memcpy(devc->raw_sample_buf + offset + (i * 4),
853 devc->sample, 4);
baf1d714 854 }
fefc4b85
BV
855 memset(devc->sample, 0, 4);
856 devc->num_bytes = 0;
857 devc->rle_count = 0;
a1bb33af 858 }
43fc7885
UH
859 } else {
860 /*
861 * This is the main loop telling us a timeout was reached, or
862 * we've acquired all the samples we asked for -- we're done.
a803c0db 863 * Send the (properly-ordered) buffer to the frontend.
43fc7885 864 */
fefc4b85 865 if (devc->trigger_at != -1) {
a803c0db
BV
866 /* a trigger was set up, so we need to tell the frontend
867 * about it.
868 */
fefc4b85 869 if (devc->trigger_at > 0) {
a803c0db 870 /* there are pre-trigger samples, send those first */
5a2326a7 871 packet.type = SR_DF_LOGIC;
9c939c51 872 packet.payload = &logic;
fefc4b85 873 logic.length = devc->trigger_at * 4;
9c939c51 874 logic.unitsize = 4;
fefc4b85
BV
875 logic.data = devc->raw_sample_buf +
876 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 877 sr_session_send(cb_data, &packet);
a803c0db
BV
878 }
879
9c939c51 880 /* send the trigger */
5a2326a7 881 packet.type = SR_DF_TRIGGER;
1f9813eb 882 sr_session_send(cb_data, &packet);
a803c0db 883
9c939c51 884 /* send post-trigger samples */
5a2326a7 885 packet.type = SR_DF_LOGIC;
9c939c51 886 packet.payload = &logic;
fefc4b85 887 logic.length = (devc->num_samples * 4) - (devc->trigger_at * 4);
9c939c51 888 logic.unitsize = 4;
fefc4b85
BV
889 logic.data = devc->raw_sample_buf + devc->trigger_at * 4 +
890 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 891 sr_session_send(cb_data, &packet);
a803c0db 892 } else {
9c939c51 893 /* no trigger was used */
5a2326a7 894 packet.type = SR_DF_LOGIC;
9c939c51 895 packet.payload = &logic;
fefc4b85 896 logic.length = devc->num_samples * 4;
9c939c51 897 logic.unitsize = 4;
fefc4b85
BV
898 logic.data = devc->raw_sample_buf +
899 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 900 sr_session_send(cb_data, &packet);
a803c0db 901 }
fefc4b85 902 g_free(devc->raw_sample_buf);
a803c0db 903
06d64eb8 904 serial_flush(fd);
d02a535e 905 serial_close(fd);
26bf9d56
BV
906
907 abort_acquisition(sdi);
a1bb33af
UH
908 }
909
910 return TRUE;
911}
912
5d9ed643
BV
913static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
914 void *cb_data)
a1bb33af 915{
b9c735a2
UH
916 struct sr_datafeed_packet *packet;
917 struct sr_datafeed_header *header;
f366e86c 918 struct sr_datafeed_meta_logic meta;
fefc4b85 919 struct dev_context *devc;
a803c0db 920 uint32_t trigger_config[4];
a1bb33af 921 uint32_t data;
6937bb75
BV
922 uint16_t readcount, delaycount;
923 uint8_t changrp_mask;
22130421 924 int num_channels;
4fe9a6da 925 int i;
a1bb33af 926
fefc4b85 927 devc = sdi->priv;
a1bb33af 928
5a2326a7 929 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 930 return SR_ERR;
a1bb33af 931
014359e3
BV
932 if (configure_probes(sdi) != SR_OK) {
933 sr_err("ols: failed to configured probes");
934 return SR_ERR;
935 }
936
22130421
GM
937 /*
938 * Enable/disable channel groups in the flag register according to the
baf1d714 939 * probe mask. Calculate this here, because num_channels is needed
22130421
GM
940 * to limit readcount.
941 */
942 changrp_mask = 0;
943 num_channels = 0;
944 for (i = 0; i < 4; i++) {
fefc4b85 945 if (devc->probe_mask & (0xff << (i * 8))) {
22130421
GM
946 changrp_mask |= (1 << i);
947 num_channels++;
948 }
949 }
950
baf1d714
UH
951 /*
952 * Limit readcount to prevent reading past the end of the hardware
22130421
GM
953 * buffer.
954 */
fefc4b85 955 readcount = MIN(devc->max_samples / num_channels, devc->limit_samples) / 4;
a803c0db
BV
956
957 memset(trigger_config, 0, 16);
fefc4b85
BV
958 trigger_config[devc->num_stages - 1] |= 0x08;
959 if (devc->trigger_mask[0]) {
960 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
961 devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
a803c0db 962
fefc4b85
BV
963 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_0,
964 reverse32(devc->trigger_mask[0])) != SR_OK)
e46b8fb1 965 return SR_ERR;
fefc4b85
BV
966 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_0,
967 reverse32(devc->trigger_value[0])) != SR_OK)
e46b8fb1 968 return SR_ERR;
fefc4b85 969 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
970 trigger_config[0]) != SR_OK)
971 return SR_ERR;
6937bb75 972
fefc4b85
BV
973 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_1,
974 reverse32(devc->trigger_mask[1])) != SR_OK)
e46b8fb1 975 return SR_ERR;
fefc4b85
BV
976 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_1,
977 reverse32(devc->trigger_value[1])) != SR_OK)
e46b8fb1 978 return SR_ERR;
fefc4b85 979 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_1,
e46b8fb1
UH
980 trigger_config[1]) != SR_OK)
981 return SR_ERR;
6937bb75 982
fefc4b85
BV
983 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_2,
984 reverse32(devc->trigger_mask[2])) != SR_OK)
e46b8fb1 985 return SR_ERR;
fefc4b85
BV
986 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_2,
987 reverse32(devc->trigger_value[2])) != SR_OK)
e46b8fb1 988 return SR_ERR;
fefc4b85 989 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_2,
e46b8fb1
UH
990 trigger_config[2]) != SR_OK)
991 return SR_ERR;
a803c0db 992
fefc4b85
BV
993 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_3,
994 reverse32(devc->trigger_mask[3])) != SR_OK)
e46b8fb1 995 return SR_ERR;
fefc4b85
BV
996 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_3,
997 reverse32(devc->trigger_value[3])) != SR_OK)
e46b8fb1 998 return SR_ERR;
fefc4b85 999 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_3,
e46b8fb1
UH
1000 trigger_config[3]) != SR_OK)
1001 return SR_ERR;
6937bb75 1002 } else {
fefc4b85
BV
1003 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_0,
1004 devc->trigger_mask[0]) != SR_OK)
e46b8fb1 1005 return SR_ERR;
fefc4b85
BV
1006 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_0,
1007 devc->trigger_value[0]) != SR_OK)
e46b8fb1 1008 return SR_ERR;
fefc4b85 1009 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
1010 0x00000008) != SR_OK)
1011 return SR_ERR;
a803c0db 1012 delaycount = readcount;
6937bb75 1013 }
a1bb33af 1014
b08024a8 1015 sr_info("ols: setting samplerate to %" PRIu64 " Hz (divider %u, "
fefc4b85
BV
1016 "demux %s)", devc->cur_samplerate, devc->cur_samplerate_divider,
1017 devc->flag_reg & FLAG_DEMUX ? "on" : "off");
1018 if (send_longcommand(devc->serial->fd, CMD_SET_DIVIDER,
1019 reverse32(devc->cur_samplerate_divider)) != SR_OK)
4fe9a6da 1020 return SR_ERR;
a1bb33af 1021
43fc7885 1022 /* Send sample limit and pre/post-trigger capture ratio. */
a803c0db
BV
1023 data = ((readcount - 1) & 0xffff) << 16;
1024 data |= (delaycount - 1) & 0xffff;
fefc4b85 1025 if (send_longcommand(devc->serial->fd, CMD_CAPTURE_SIZE, reverse16(data)) != SR_OK)
e46b8fb1 1026 return SR_ERR;
a1bb33af 1027
43fc7885 1028 /* The flag register wants them here, and 1 means "disable channel". */
fefc4b85
BV
1029 devc->flag_reg |= ~(changrp_mask << 2) & 0x3c;
1030 devc->flag_reg |= FLAG_FILTER;
1031 devc->rle_count = 0;
1032 data = (devc->flag_reg << 24) | ((devc->flag_reg << 8) & 0xff0000);
1033 if (send_longcommand(devc->serial->fd, CMD_SET_FLAGS, data) != SR_OK)
e46b8fb1 1034 return SR_ERR;
a1bb33af 1035
43fc7885 1036 /* Start acquisition on the device. */
fefc4b85 1037 if (send_shortcommand(devc->serial->fd, CMD_RUN) != SR_OK)
e46b8fb1 1038 return SR_ERR;
a1bb33af 1039
fefc4b85 1040 sr_source_add(devc->serial->fd, G_IO_IN, -1, receive_data,
3cd3a20b 1041 cb_data);
a1bb33af 1042
b53738ba
UH
1043 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1044 sr_err("ols: %s: packet malloc failed", __func__);
1045 return SR_ERR_MALLOC;
1046 }
1047
1048 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1049 sr_err("ols: %s: header malloc failed", __func__);
c0a4b971 1050 g_free(packet);
b53738ba
UH
1051 return SR_ERR_MALLOC;
1052 }
1053
43fc7885 1054 /* Send header packet to the session bus. */
5a2326a7 1055 packet->type = SR_DF_HEADER;
43fc7885 1056 packet->payload = (unsigned char *)header;
a1bb33af
UH
1057 header->feed_version = 1;
1058 gettimeofday(&header->starttime, NULL);
f366e86c
BV
1059 sr_session_send(cb_data, packet);
1060
1061 /* Send metadata about the SR_DF_LOGIC packets to come. */
1062 packet->type = SR_DF_META_LOGIC;
1063 packet->payload = &meta;
fefc4b85 1064 meta.samplerate = devc->cur_samplerate;
f366e86c 1065 meta.num_probes = NUM_PROBES;
3cd3a20b 1066 sr_session_send(cb_data, packet);
c0a4b971 1067
a1bb33af
UH
1068 g_free(header);
1069 g_free(packet);
1070
e46b8fb1 1071 return SR_OK;
a1bb33af
UH
1072}
1073
3cd3a20b 1074/* TODO: This stops acquisition on ALL devices, ignoring dev_index. */
5d9ed643
BV
1075static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
1076 void *cb_data)
a1bb33af 1077{
a1bb33af 1078
17e1afcb 1079 /* Avoid compiler warnings. */
26bf9d56 1080 (void)cb_data;
afc8e4de 1081
26bf9d56 1082 abort_acquisition(sdi);
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1083
1084 return SR_OK;
a1bb33af
UH
1085}
1086
c09f0b57 1087SR_PRIV struct sr_dev_driver ols_driver_info = {
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1088 .name = "ols",
1089 .longname = "Openbench Logic Sniffer",
1090 .api_version = 1,
1091 .init = hw_init,
1092 .cleanup = hw_cleanup,
61136ea6 1093 .scan = hw_scan,
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BV
1094 .dev_list = hw_dev_list,
1095 .dev_clear = hw_cleanup,
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1096 .dev_open = hw_dev_open,
1097 .dev_close = hw_dev_close,
dddfb3db 1098 .info_get = hw_info_get,
a9a245b4 1099 .dev_config_set = hw_dev_config_set,
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1100 .dev_acquisition_start = hw_dev_acquisition_start,
1101 .dev_acquisition_stop = hw_dev_acquisition_stop,
fefc4b85 1102 .priv = NULL,
a1bb33af 1103};