[sigrok-firmware-fx2lafw.git] / gpif-acquisition.c

/*
 * This file is part of the fx2lafw project.
 *
 * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

#include <eputils.h>
#include <fx2regs.h>
#include <fx2macros.h>
#include <delay.h>
#include <gpif.h>

#include <fx2lafw.h>
#include <gpif-acquisition.h>

bit gpif_acquiring;

static void gpif_reset_waveforms(void)
{
	int i;

	/* Reset WAVEDATA. */
	AUTOPTRSETUP = 0x03;
	AUTOPTRH1 = 0xe4;
	AUTOPTRL1 = 0x00;
	for (i = 0; i < 128; i++)
		EXTAUTODAT1 = 0;
}

static void gpif_setup_registers(void)
{
	/* TODO. Value probably irrelevant, as we don't use RDY* signals? */
	GPIFREADYCFG = 0;

	/*
	 * Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs.
	 * TODO: Probably irrelevant, as we don't use CTL0-CTL5?
	 */
	GPIFCTLCFG = 0;

	/* When GPIF is idle, tri-state the data bus. */
	/* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
	GPIFIDLECS = (1 << 0);

	/* When GPIF is idle, set CTL0-CTL5 to 0. */
	GPIFIDLECTL = 0;

	/*
	 * Map index 0 in WAVEDATA to FIFORD. The rest is assigned too,
	 * but not used by us.
	 *
	 * GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index,
	 *               [3:2] = FIFOWR index, [1:0] = FIFORD index
	 */
	GPIFWFSELECT = (0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0);

	/* Contains RDY* pin values. Read-only according to TRM. */
	GPIFREADYSTAT = 0;

	/* Make GPIF stop on transcation count not flag */
	EP2GPIFPFSTOP = (0 << 0);
}

static void gpif_init_addr_pins(void)
{
	/*
	 * Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of
	 * PORTC[7:0] and PORTE[7]), and output an initial address (zero).
	 * TODO: Probably irrelevant, the 56pin FX2 has no ports C and E.
	 */
	PORTCCFG = 0xff;    /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */
	OEC = 0xff;         /* Configure PORTC[7:0] as outputs. */
	PORTECFG |= 0x80;   /* Set PORTE[7] as alt. func. (GPIFADR[8]). */
	OEE |= 0x80;        /* Configure PORTE[7] as output. */
	SYNCDELAY();
	GPIFADRL = 0x00;    /* Clear GPIFADR[7:0]. */
	SYNCDELAY();
	GPIFADRH = 0x00;    /* Clear GPIFADR[8]. */
}

static void gpif_init_flowstates(void)
{
	/* Clear all flowstate registers, we don't use this functionality. */
	FLOWSTATE = 0;
	FLOWLOGIC = 0;
	FLOWEQ0CTL = 0;
	FLOWEQ1CTL = 0;
	FLOWHOLDOFF = 0;
	FLOWSTB = 0;
	FLOWSTBEDGE = 0;
	FLOWSTBHPERIOD = 0;
}

void gpif_init_la(void)
{
	/*
	 * Setup the FX2 in GPIF master mode, using the internal clock
	 * (non-inverted) at 48MHz, and using async sampling.
	 */
	IFCONFIG = 0xee;

	/* Abort currently executing GPIF waveform (if any). */
	GPIFABORT = 0xff;

	/* Setup the GPIF registers. */
	gpif_setup_registers();

	/* Reset WAVEDATA. */
	gpif_reset_waveforms();

	/* Initialize GPIF address pins, output initial values. */
	gpif_init_addr_pins();

	/* Initialize flowstate registers (not used by us). */
	gpif_init_flowstates();

	/* Reset the status */
	gpif_acquiring = FALSE;
}

void gpif_acquisition_start(const struct cmd_start_acquisition *cmd)
{
	xdata volatile BYTE *pSTATE;

	/* Ensure GPIF is idle before reconfiguration */
	while(!(GPIFTRIG & 0x80));

	/* Set IFCONFIG to the correct clock source */
	if(cmd->flags & CMD_START_FLAGS_CLK_48MHZ) {
		IFCONFIG = bmIFCLKSRC |
			bm3048MHZ |
			bmIFCLKOE |
			bmASYNC |
			bmGSTATE |
			bmIFGPIF;
	} else {
		IFCONFIG = bmIFCLKSRC |
			bmIFCLKOE |
			bmASYNC |
			bmGSTATE |
			bmIFGPIF;
	}

	/* GPIF terminology: DP = decision point, NDP = non-decision-point */

	/* Populate WAVEDATA
	 *
	 * This is the basic algorithm implemented in our GPIF state machine:
	 *
	 * State 0: NDP: Sample the FIFO data bus.
	 * State 1: DP: If EP2 is full, go to state 7 (the IDLE state), i.e.,
	 *          end the current waveform. Otherwise, go to state 0 again,
	 *          i.e., sample data until EP2 is full.
	 * State 2: Unused.
	 * State 3: Unused.
	 * State 4: Unused.
	 * State 5: Unused.
	 * State 6: Unused.
	 */

	/* Populate S0 */
	pSTATE = &GPIF_WAVE_DATA;

	/* DELAY
	 * Delay cmd->sample_delay clocks.
	 */
	pSTATE[0] = cmd->sample_delay;

	/* OPCODE
	 * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=1, DP=0
	 * Collect data in this state.
	 */
	pSTATE[8] = 0x02;

	/* OUTPUT
	 * OE[0:3]=0, CTL[0:3]=0
	 */
	pSTATE[16] = 0x00;

	/* LOGIC FUNCTION
	 * Not used
	 */
	pSTATE[24] = 0x00;

	/* Populate S1 - the decision point */
	pSTATE = &GPIF_WAVE_DATA + 1;

	/* BRANCH
	 * Branch to IDLE if condition is true, back to S0 otherwise
	 */
	pSTATE[0] = (7 << 3) | (0 << 0);

	/* OPCODE
	 * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=0, DP=1
	 */
	pSTATE[8] = (1 << 0);

	/* OUTPUT
	 * OE[0:3]=0, CTL[0:3]=0
	 */
	pSTATE[16] = 0x00;

	/* LOGIC FUNCTION
	 * Evaluate if the FIFO full flag is set.
	 * LFUNC=0 (AND), TERMA=6 (FIFO Flag), TERMB=6 (FIFO Flag)
	 */
	pSTATE[24] = (6 << 3) | (6 << 0);

	/* Execute the whole GPIF waveform once */
	gpif_set_tc16(1);

	/* Perform the initial GPIF read. */
	gpif_fifo_read(GPIF_EP2);

	/* Update the status */
	gpif_acquiring = TRUE;
}

void gpif_poll(void)
{
	/* Detect if acquisition has completed */
	if(gpif_acquiring && (GPIFTRIG & 0x80))
	{
		/* Activate NAK-ALL to avoid race conditions */
		FIFORESET = 0x80;
		SYNCDELAY();

		/* Switch to manual mode */
		EP2FIFOCFG = 0;
		SYNCDELAY();

		/* Reset EP2 */
		FIFORESET = 0x02;
		SYNCDELAY();

		/* Return to auto mode */
		EP2FIFOCFG = bmAUTOIN;
		SYNCDELAY();

		/* Release NAK-ALL */
		FIFORESET = 0x00;
		SYNCDELAY();

		gpif_acquiring = FALSE;
	}
}
Commit	Line	Data
e41576ec JH	1	/*
	2	* This file is part of the fx2lafw project.
	3	*
	4	* Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	*/
	21
293d7e9e	22	#include <eputils.h>
e41576ec JH	23	#include <fx2regs.h>
	24	#include <fx2macros.h>
	25	#include <delay.h>
	26	#include <gpif.h>
	27
	28	#include <fx2lafw.h>
	29	#include <gpif-acquisition.h>
	30
293d7e9e JH	31	bit gpif_acquiring;
293d7e9e JH	32
421e7d6d JH	33	static void gpif_reset_waveforms(void)
	34	{
	35	int i;
e41576ec	36
421e7d6d JH	37	/* Reset WAVEDATA. */
	38	AUTOPTRSETUP = 0x03;
	39	AUTOPTRH1 = 0xe4;
	40	AUTOPTRL1 = 0x00;
	41	for (i = 0; i < 128; i++)
	42	EXTAUTODAT1 = 0;
	43	}
e41576ec JH	44
	45	static void gpif_setup_registers(void)
	46	{
	47	/* TODO. Value probably irrelevant, as we don't use RDY* signals? */
	48	GPIFREADYCFG = 0;
	49
	50	/*
	51	* Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs.
	52	* TODO: Probably irrelevant, as we don't use CTL0-CTL5?
	53	*/
	54	GPIFCTLCFG = 0;
	55
	56	/* When GPIF is idle, tri-state the data bus. */
	57	/* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
	58	GPIFIDLECS = (1 << 0);
	59
	60	/* When GPIF is idle, set CTL0-CTL5 to 0. */
	61	GPIFIDLECTL = 0;
	62
	63	/*
421e7d6d	64	* Map index 0 in WAVEDATA to FIFORD. The rest is assigned too,
e41576ec JH	65	* but not used by us.
	66	*
	67	* GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index,
	68	* [3:2] = FIFOWR index, [1:0] = FIFORD index
	69	*/
	70	GPIFWFSELECT = (0x3 << 6) \| (0x2 << 4) \| (0x1 << 2) \| (0x0 << 0);
	71
	72	/* Contains RDY* pin values. Read-only according to TRM. */
	73	GPIFREADYSTAT = 0;
1e588d06 JH	74
	75	/* Make GPIF stop on transcation count not flag */
	76	EP2GPIFPFSTOP = (0 << 0);
e41576ec JH	77	}
e41576ec JH	78
e41576ec JH	79	static void gpif_init_addr_pins(void)
	80	{
	81	/*
	82	* Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of
	83	* PORTC[7:0] and PORTE[7]), and output an initial address (zero).
	84	* TODO: Probably irrelevant, the 56pin FX2 has no ports C and E.
	85	*/
	86	PORTCCFG = 0xff; /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */
	87	OEC = 0xff; /* Configure PORTC[7:0] as outputs. */
	88	PORTECFG \|= 0x80; /* Set PORTE[7] as alt. func. (GPIFADR[8]). */
	89	OEE \|= 0x80; /* Configure PORTE[7] as output. */
	90	SYNCDELAY();
	91	GPIFADRL = 0x00; /* Clear GPIFADR[7:0]. */
	92	SYNCDELAY();
	93	GPIFADRH = 0x00; /* Clear GPIFADR[8]. */
	94	}
	95
	96	static void gpif_init_flowstates(void)
	97	{
	98	/* Clear all flowstate registers, we don't use this functionality. */
	99	FLOWSTATE = 0;
	100	FLOWLOGIC = 0;
	101	FLOWEQ0CTL = 0;
	102	FLOWEQ1CTL = 0;
	103	FLOWHOLDOFF = 0;
	104	FLOWSTB = 0;
	105	FLOWSTBEDGE = 0;
	106	FLOWSTBHPERIOD = 0;
	107	}
	108
	109	void gpif_init_la(void)
	110	{
	111	/*
	112	* Setup the FX2 in GPIF master mode, using the internal clock
	113	* (non-inverted) at 48MHz, and using async sampling.
	114	*/
	115	IFCONFIG = 0xee;
	116
	117	/* Abort currently executing GPIF waveform (if any). */
	118	GPIFABORT = 0xff;
	119
	120	/* Setup the GPIF registers. */
	121	gpif_setup_registers();
	122
421e7d6d JH	123	/* Reset WAVEDATA. */
421e7d6d JH	124	gpif_reset_waveforms();
e41576ec JH	125
	126	/* Initialize GPIF address pins, output initial values. */
	127	gpif_init_addr_pins();
	128
	129	/* Initialize flowstate registers (not used by us). */
	130	gpif_init_flowstates();
293d7e9e JH	131
	132	/* Reset the status */
	133	gpif_acquiring = FALSE;
e41576ec JH	134	}
e41576ec JH	135
2846a114	136	void gpif_acquisition_start(const struct cmd_start_acquisition *cmd)
e41576ec	137	{
421e7d6d JH	138	xdata volatile BYTE *pSTATE;
421e7d6d JH	139
3b969d92 JH	140	/* Ensure GPIF is idle before reconfiguration */
	141	while(!(GPIFTRIG & 0x80));
	142
809dc779 JH	143	/* Set IFCONFIG to the correct clock source */
	144	if(cmd->flags & CMD_START_FLAGS_CLK_48MHZ) {
	145	IFCONFIG = bmIFCLKSRC \|
	146	bm3048MHZ \|
	147	bmIFCLKOE \|
	148	bmASYNC \|
	149	bmGSTATE \|
	150	bmIFGPIF;
	151	} else {
	152	IFCONFIG = bmIFCLKSRC \|
	153	bmIFCLKOE \|
	154	bmASYNC \|
	155	bmGSTATE \|
	156	bmIFGPIF;
	157	}
2846a114	158
421e7d6d JH	159	/* GPIF terminology: DP = decision point, NDP = non-decision-point */
	160
	161	/* Populate WAVEDATA
	162	*
	163	* This is the basic algorithm implemented in our GPIF state machine:
	164	*
	165	* State 0: NDP: Sample the FIFO data bus.
	166	* State 1: DP: If EP2 is full, go to state 7 (the IDLE state), i.e.,
	167	* end the current waveform. Otherwise, go to state 0 again,
	168	* i.e., sample data until EP2 is full.
	169	* State 2: Unused.
	170	* State 3: Unused.
	171	* State 4: Unused.
	172	* State 5: Unused.
	173	* State 6: Unused.
	174	*/
	175
	176	/* Populate S0 */
	177	pSTATE = &GPIF_WAVE_DATA;
baecf744 JH	178
	179	/* DELAY
	180	* Delay cmd->sample_delay clocks.
	181	*/
2846a114	182	pSTATE[0] = cmd->sample_delay;
baecf744 JH	183
	184	/* OPCODE
	185	* SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=1, DP=0
	186	* Collect data in this state.
	187	*/
421e7d6d	188	pSTATE[8] = 0x02;
baecf744 JH	189
	190	/* OUTPUT
	191	* OE[0:3]=0, CTL[0:3]=0
	192	*/
421e7d6d	193	pSTATE[16] = 0x00;
baecf744 JH	194
	195	/* LOGIC FUNCTION
	196	* Not used
	197	*/
421e7d6d JH	198	pSTATE[24] = 0x00;
421e7d6d JH	199
baecf744	200	/* Populate S1 - the decision point */
421e7d6d	201	pSTATE = &GPIF_WAVE_DATA + 1;
baecf744 JH	202
	203	/* BRANCH
	204	* Branch to IDLE if condition is true, back to S0 otherwise
	205	*/
	206	pSTATE[0] = (7 << 3) \| (0 << 0);
	207
	208	/* OPCODE
	209	* SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=0, DP=1
	210	*/
	211	pSTATE[8] = (1 << 0);
	212
	213	/* OUTPUT
	214	* OE[0:3]=0, CTL[0:3]=0
	215	*/
421e7d6d	216	pSTATE[16] = 0x00;
baecf744 JH	217
	218	/* LOGIC FUNCTION
	219	* Evaluate if the FIFO full flag is set.
	220	* LFUNC=0 (AND), TERMA=6 (FIFO Flag), TERMB=6 (FIFO Flag)
	221	*/
	222	pSTATE[24] = (6 << 3) \| (6 << 0);
421e7d6d	223
1e588d06 JH	224	/* Execute the whole GPIF waveform once */
	225	gpif_set_tc16(1);
	226
e41576ec JH	227	/* Perform the initial GPIF read. */
e41576ec JH	228	gpif_fifo_read(GPIF_EP2);
293d7e9e JH	229
	230	/* Update the status */
	231	gpif_acquiring = TRUE;
	232	}
	233
	234	void gpif_poll(void)
	235	{
	236	/* Detect if acquisition has completed */
	237	if(gpif_acquiring && (GPIFTRIG & 0x80))
	238	{
	239	/* Activate NAK-ALL to avoid race conditions */
	240	FIFORESET = 0x80;
	241	SYNCDELAY();
	242
	243	/* Switch to manual mode */
	244	EP2FIFOCFG = 0;
	245	SYNCDELAY();
	246
	247	/* Reset EP2 */
	248	FIFORESET = 0x02;
	249	SYNCDELAY();
	250
	251	/* Return to auto mode */
	252	EP2FIFOCFG = bmAUTOIN;
	253	SYNCDELAY();
	254
	255	/* Release NAK-ALL */
	256	FIFORESET = 0x00;
	257	SYNCDELAY();
	258
	259	gpif_acquiring = FALSE;
	260	}
e41576ec	261	}