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e41576ec | 1 | /* |
a986cfff | 2 | * This file is part of the sigrok-firmware-fx2lafw project. |
e41576ec JH |
3 | * |
4 | * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | */ | |
21 | ||
293d7e9e | 22 | #include <eputils.h> |
e41576ec JH |
23 | #include <fx2regs.h> |
24 | #include <fx2macros.h> | |
25 | #include <delay.h> | |
26 | #include <gpif.h> | |
e41576ec JH |
27 | #include <fx2lafw.h> |
28 | #include <gpif-acquisition.h> | |
29 | ||
8819f75c | 30 | __bit gpif_acquiring; |
293d7e9e | 31 | |
421e7d6d JH |
32 | static void gpif_reset_waveforms(void) |
33 | { | |
34 | int i; | |
e41576ec | 35 | |
421e7d6d JH |
36 | /* Reset WAVEDATA. */ |
37 | AUTOPTRSETUP = 0x03; | |
38 | AUTOPTRH1 = 0xe4; | |
39 | AUTOPTRL1 = 0x00; | |
40 | for (i = 0; i < 128; i++) | |
41 | EXTAUTODAT1 = 0; | |
42 | } | |
e41576ec JH |
43 | |
44 | static void gpif_setup_registers(void) | |
45 | { | |
46 | /* TODO. Value probably irrelevant, as we don't use RDY* signals? */ | |
47 | GPIFREADYCFG = 0; | |
48 | ||
49 | /* | |
50 | * Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs. | |
51 | * TODO: Probably irrelevant, as we don't use CTL0-CTL5? | |
52 | */ | |
53 | GPIFCTLCFG = 0; | |
54 | ||
55 | /* When GPIF is idle, tri-state the data bus. */ | |
56 | /* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */ | |
6398a519 | 57 | GPIFIDLECS = (0 << 0); |
e41576ec JH |
58 | |
59 | /* When GPIF is idle, set CTL0-CTL5 to 0. */ | |
60 | GPIFIDLECTL = 0; | |
61 | ||
62 | /* | |
421e7d6d | 63 | * Map index 0 in WAVEDATA to FIFORD. The rest is assigned too, |
e41576ec JH |
64 | * but not used by us. |
65 | * | |
66 | * GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index, | |
67 | * [3:2] = FIFOWR index, [1:0] = FIFORD index | |
68 | */ | |
69 | GPIFWFSELECT = (0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0); | |
70 | ||
71 | /* Contains RDY* pin values. Read-only according to TRM. */ | |
72 | GPIFREADYSTAT = 0; | |
1e588d06 | 73 | |
c7e02d8c | 74 | /* Make GPIF stop on transaction count not flag. */ |
1e588d06 | 75 | EP2GPIFPFSTOP = (0 << 0); |
e41576ec JH |
76 | } |
77 | ||
e41576ec JH |
78 | static void gpif_init_addr_pins(void) |
79 | { | |
80 | /* | |
81 | * Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of | |
82 | * PORTC[7:0] and PORTE[7]), and output an initial address (zero). | |
83 | * TODO: Probably irrelevant, the 56pin FX2 has no ports C and E. | |
84 | */ | |
85 | PORTCCFG = 0xff; /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */ | |
86 | OEC = 0xff; /* Configure PORTC[7:0] as outputs. */ | |
87 | PORTECFG |= 0x80; /* Set PORTE[7] as alt. func. (GPIFADR[8]). */ | |
88 | OEE |= 0x80; /* Configure PORTE[7] as output. */ | |
89 | SYNCDELAY(); | |
90 | GPIFADRL = 0x00; /* Clear GPIFADR[7:0]. */ | |
91 | SYNCDELAY(); | |
92 | GPIFADRH = 0x00; /* Clear GPIFADR[8]. */ | |
93 | } | |
94 | ||
95 | static void gpif_init_flowstates(void) | |
96 | { | |
97 | /* Clear all flowstate registers, we don't use this functionality. */ | |
98 | FLOWSTATE = 0; | |
99 | FLOWLOGIC = 0; | |
100 | FLOWEQ0CTL = 0; | |
101 | FLOWEQ1CTL = 0; | |
102 | FLOWHOLDOFF = 0; | |
103 | FLOWSTB = 0; | |
104 | FLOWSTBEDGE = 0; | |
105 | FLOWSTBHPERIOD = 0; | |
106 | } | |
107 | ||
108 | void gpif_init_la(void) | |
109 | { | |
110 | /* | |
111 | * Setup the FX2 in GPIF master mode, using the internal clock | |
112 | * (non-inverted) at 48MHz, and using async sampling. | |
113 | */ | |
114 | IFCONFIG = 0xee; | |
115 | ||
116 | /* Abort currently executing GPIF waveform (if any). */ | |
117 | GPIFABORT = 0xff; | |
118 | ||
119 | /* Setup the GPIF registers. */ | |
120 | gpif_setup_registers(); | |
121 | ||
421e7d6d JH |
122 | /* Reset WAVEDATA. */ |
123 | gpif_reset_waveforms(); | |
e41576ec JH |
124 | |
125 | /* Initialize GPIF address pins, output initial values. */ | |
126 | gpif_init_addr_pins(); | |
127 | ||
128 | /* Initialize flowstate registers (not used by us). */ | |
129 | gpif_init_flowstates(); | |
293d7e9e | 130 | |
c7e02d8c | 131 | /* Reset the status. */ |
293d7e9e | 132 | gpif_acquiring = FALSE; |
e41576ec JH |
133 | } |
134 | ||
a371bdee | 135 | static void gpif_make_delay_state(volatile BYTE *pSTATE, uint8_t delay) |
e41576ec | 136 | { |
cd29817d UH |
137 | /* |
138 | * DELAY | |
baecf744 JH |
139 | * Delay cmd->sample_delay clocks. |
140 | */ | |
7dfad4cb | 141 | pSTATE[0] = delay; |
baecf744 | 142 | |
cd29817d UH |
143 | /* |
144 | * OPCODE | |
a371bdee | 145 | * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=0, DP=0 |
baecf744 JH |
146 | * Collect data in this state. |
147 | */ | |
a371bdee | 148 | pSTATE[8] = 0x00; |
baecf744 | 149 | |
cd29817d UH |
150 | /* |
151 | * OUTPUT | |
baecf744 JH |
152 | * OE[0:3]=0, CTL[0:3]=0 |
153 | */ | |
421e7d6d | 154 | pSTATE[16] = 0x00; |
baecf744 | 155 | |
cd29817d UH |
156 | /* |
157 | * LOGIC FUNCTION | |
158 | * Not used. | |
baecf744 | 159 | */ |
421e7d6d | 160 | pSTATE[24] = 0x00; |
7dfad4cb | 161 | } |
421e7d6d | 162 | |
a371bdee | 163 | static void gpid_make_data_dp_state(volatile BYTE *pSTATE) |
7dfad4cb | 164 | { |
cd29817d UH |
165 | /* |
166 | * BRANCH | |
167 | * Branch to IDLE if condition is true, back to S0 otherwise. | |
baecf744 JH |
168 | */ |
169 | pSTATE[0] = (7 << 3) | (0 << 0); | |
170 | ||
cd29817d UH |
171 | /* |
172 | * OPCODE | |
a371bdee | 173 | * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=1, DP=1 |
baecf744 | 174 | */ |
a371bdee | 175 | pSTATE[8] = (1 << 1) | (1 << 0); |
baecf744 | 176 | |
cd29817d UH |
177 | /* |
178 | * OUTPUT | |
baecf744 JH |
179 | * OE[0:3]=0, CTL[0:3]=0 |
180 | */ | |
421e7d6d | 181 | pSTATE[16] = 0x00; |
baecf744 | 182 | |
cd29817d UH |
183 | /* |
184 | * LOGIC FUNCTION | |
baecf744 JH |
185 | * Evaluate if the FIFO full flag is set. |
186 | * LFUNC=0 (AND), TERMA=6 (FIFO Flag), TERMB=6 (FIFO Flag) | |
187 | */ | |
188 | pSTATE[24] = (6 << 3) | (6 << 0); | |
7dfad4cb JH |
189 | } |
190 | ||
fb08a72d | 191 | bool gpif_acquisition_start(const struct cmd_start_acquisition *cmd) |
7dfad4cb | 192 | { |
fb08a72d JH |
193 | int i; |
194 | volatile BYTE *pSTATE = &GPIF_WAVE_DATA; | |
7dfad4cb JH |
195 | |
196 | /* Ensure GPIF is idle before reconfiguration. */ | |
197 | while (!(GPIFTRIG & 0x80)); | |
198 | ||
5d492e18 UH |
199 | /* Configure the EP2 FIFO. */ |
200 | if (cmd->flags & CMD_START_FLAGS_SAMPLE_16BIT) { | |
daf6d940 JH |
201 | EP2FIFOCFG = bmAUTOIN | bmWORDWIDE; |
202 | } else { | |
203 | EP2FIFOCFG = bmAUTOIN; | |
204 | } | |
205 | SYNCDELAY(); | |
206 | ||
7dfad4cb JH |
207 | /* Set IFCONFIG to the correct clock source. */ |
208 | if (cmd->flags & CMD_START_FLAGS_CLK_48MHZ) { | |
209 | IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmASYNC | | |
210 | bmGSTATE | bmIFGPIF; | |
211 | } else { | |
212 | IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmASYNC | | |
213 | bmGSTATE | bmIFGPIF; | |
214 | } | |
215 | ||
5d492e18 UH |
216 | /* Populate delay states. */ |
217 | if ((cmd->sample_delay_h == 0 && cmd->sample_delay_l == 0) || | |
218 | cmd->sample_delay_h >= 6) | |
fb08a72d | 219 | return false; |
7dfad4cb | 220 | |
5d492e18 | 221 | for (i = 0; i < cmd->sample_delay_h; i++) |
fb08a72d | 222 | gpif_make_delay_state(pSTATE++, 0); |
7dfad4cb | 223 | |
5d492e18 | 224 | if (cmd->sample_delay_l != 0) |
fb08a72d | 225 | gpif_make_delay_state(pSTATE++, cmd->sample_delay_l); |
7dfad4cb JH |
226 | |
227 | /* Populate S1 - the decision point. */ | |
fb08a72d | 228 | gpid_make_data_dp_state(pSTATE++); |
421e7d6d | 229 | |
cd29817d | 230 | /* Execute the whole GPIF waveform once. */ |
1e588d06 JH |
231 | gpif_set_tc16(1); |
232 | ||
e41576ec JH |
233 | /* Perform the initial GPIF read. */ |
234 | gpif_fifo_read(GPIF_EP2); | |
293d7e9e | 235 | |
cd29817d | 236 | /* Update the status. */ |
293d7e9e | 237 | gpif_acquiring = TRUE; |
fb08a72d JH |
238 | |
239 | return true; | |
293d7e9e JH |
240 | } |
241 | ||
242 | void gpif_poll(void) | |
243 | { | |
cd29817d UH |
244 | /* Detect if acquisition has completed. */ |
245 | if (gpif_acquiring && (GPIFTRIG & 0x80)) { | |
246 | /* Activate NAK-ALL to avoid race conditions. */ | |
293d7e9e JH |
247 | FIFORESET = 0x80; |
248 | SYNCDELAY(); | |
249 | ||
cd29817d | 250 | /* Switch to manual mode. */ |
293d7e9e JH |
251 | EP2FIFOCFG = 0; |
252 | SYNCDELAY(); | |
253 | ||
cd29817d | 254 | /* Reset EP2. */ |
293d7e9e JH |
255 | FIFORESET = 0x02; |
256 | SYNCDELAY(); | |
257 | ||
cd29817d | 258 | /* Return to auto mode. */ |
293d7e9e JH |
259 | EP2FIFOCFG = bmAUTOIN; |
260 | SYNCDELAY(); | |
261 | ||
cd29817d | 262 | /* Release NAK-ALL. */ |
293d7e9e JH |
263 | FIFORESET = 0x00; |
264 | SYNCDELAY(); | |
265 | ||
266 | gpif_acquiring = FALSE; | |
267 | } | |
e41576ec | 268 | } |