]>
Commit | Line | Data |
---|---|---|
3608c106 UH |
1 | // Copyright (C) 2010 Ubixum, Inc. |
2 | // | |
3 | // This library is free software; you can redistribute it and/or | |
4 | // modify it under the terms of the GNU Lesser General Public | |
5 | // License as published by the Free Software Foundation; either | |
6 | // version 2.1 of the License, or (at your option) any later version. | |
7 | // | |
8 | // This library is distributed in the hope that it will be useful, | |
9 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | // Lesser General Public License for more details. | |
12 | // | |
13 | // You should have received a copy of the GNU Lesser General Public | |
040a6eae | 14 | // License along with this library; if not, see <http://www.gnu.org/licenses/>. |
3608c106 UH |
15 | |
16 | /*! \file | |
17 | * Define the standard fx2 interrupts. For int2 and int4 autovector | |
18 | * interrupts see \ref autovector.h | |
19 | * | |
20 | * To enable an interrupt, simply define an interrupt handler function | |
21 | * and use the appropriate ENABLE_* macro. Interrupt enable macros | |
22 | * do not enable interrupts globally. Use EA=1 to enable interrupts. | |
23 | * | |
24 | * \code | |
25 | * void main() { | |
26 | * ENABLE_RESUME(); | |
27 | * EA=1; | |
28 | * ... | |
29 | * } | |
30 | * | |
31 | * void handle_resume() interrupt RESUME_ISR { | |
32 | * CLEAR_RESUME(); | |
33 | * } | |
34 | * \endcode | |
35 | * | |
36 | * */ | |
37 | ||
38 | ||
39 | /** | |
40 | * \brief interrupt numbers for standard fx2 interrupts | |
41 | ||
42 | **/ | |
43 | typedef enum { | |
44 | IE0_ISR=0, ///< External interrupt 0 | |
45 | TF0_ISR, ///< Timer 0 interrupt | |
46 | IE1_ISR, ///< External interrupt 1 | |
47 | TF1_ISR, ///< Timer 1 interrupt | |
48 | TI_0_ISR, ///< Serial port 0 transmit or receive interrupt | |
49 | TF2_ISR, ///< Timer 2 interrupt | |
50 | RESUME_ISR, ///< Resume interrupt | |
51 | TI_1_ISR, ///< Serial port 1 transmit or receive interrupt | |
52 | USBINT_ISR, ///< Usb Interrupt. An interrupt handler for this should only be used if not using auto vectored interrupts with int2 | |
53 | I2CINT_ISR, ///< I2C Bus interrupt | |
54 | IE4_ISR, ///< External interrupt 4. An interrupt handler for this should only be used if not using auto vectored interrupts with int4 | |
55 | IE5_ISR, ///< External interrupt 5 | |
56 | IE6_ISR, ///< External interrupt 6 | |
57 | } FX2_ISR; | |
58 | ||
59 | ||
60 | /** | |
61 | * \brief Enable the timer 0 interrupt. | |
62 | * | |
63 | * There is not CLEAR_TIMER0 because the timer interrupt flag | |
64 | * is automatically cleared when the isr is called. | |
65 | **/ | |
66 | #define ENABLE_TIMER0() ET0=1 | |
67 | ||
68 | /** | |
69 | * \brief Enable timer 1 interrupt | |
70 | * There is no CLEAR_TIMER1 because the timer interrupt flag | |
71 | * is automatically cleared when the isr is called. | |
72 | **/ | |
73 | #define ENABLE_TIMER1() ET1=1 | |
74 | ||
75 | ||
76 | /** | |
77 | * \brief Enable timer 2 interrupt | |
78 | * | |
79 | * This is the same interrupt whether timer 2 overflowed or | |
80 | * for the external EXF2 flag. | |
81 | **/ | |
82 | #define ENABLE_TIMER2() ET2=1 | |
83 | /** | |
84 | * \brief Clear timer 2 interrupt | |
85 | * | |
86 | * Clears both the TF2 AND EXF2 flag | |
87 | **/ | |
88 | #define CLEAR_TIMER2() TF2=0;EXF2=0; | |
89 | ||
90 | /** | |
91 | * \brief Enable the Resume Interrupt. Requires EA=1 separately. | |
92 | **/ | |
93 | #define ENABLE_RESUME() ERESI = 1 | |
94 | ||
95 | /** | |
96 | * \brief Clear the resume interrupt. Use within the resume | |
97 | * interrupt handler. | |
98 | **/ | |
99 | #define CLEAR_RESUME() RESI=0 | |
100 | ||
101 | ||
102 | #define ENABLE_INT4() | |
103 | ||
104 | /** | |
105 | * \brief | |
106 | * Enable external interupt for int5# | |
107 | **/ | |
108 | #define ENABLE_INT5() EIEX5=1 | |
109 | ||
110 | /** | |
111 | * \brief | |
112 | * Clear int5# interrupt | |
113 | **/ | |
114 | #define CLEAR_INT5() EXIF &= ~0x80 | |
115 |