Bug 218 - Rational vdiv and timebase arguments are rejected unless an exact match.
Summary: Rational vdiv and timebase arguments are rejected unless an exact match.
Status: CONFIRMED
Alias: None
Product: libsigrok
Classification: Unclassified
Component: Driver: rigol-ds (show other bugs)
Version: unreleased development snapshot
Hardware: All All
: Normal normal
Target Milestone: ---
Assignee: Nobody
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2013-12-18 03:33 CET by Martin Ling
Modified: 2018-05-27 17:48 CEST (History)
2 users (show)


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Description Martin Ling 2013-12-18 03:33:38 CET 
Rational input values for vdiv and timebase are checked against the supported values exactly. If the caller uses normalised fractions this will usually fail, e.g. for vdiv = 100mV, (1, 10) will be given but only (100, 1000) would match.

A reusable function implementing rational equality checks would be useful here.
Comment 1 Stefan Brüns 2016-05-17 17:53:04 CEST 
libsigrok now has sr_rational_eq

http://sigrok.org/gitweb/?p=libsigrok.git;a=commit;h=bdba362695bd5ee97fca685839a9e90e1e788ecb
Comment 2 Valentin Ochs 2018-05-27 17:48:34 CEST 
All supported devices accept a real value for vdiv settings. Maybe we should just check that the value is in range, and then pass it on?