|Channels||16 + 2|
Digital 0 — 5.4V|
|Threshold voltage||Fixed: VIH=1.4V, VIL=0.8V|
The XZL_Studio DX is a USB-based, 16-channel logic analyzer with up to 24MHz sampling rate, and with 2 additional analog channels.
It is a clone of the CWAV USBee DX.
See XZL_Studio DX/Info for some more details (such as lsusb -vvv output) on the device.
Note:You need to chose one of "CWAV USBee DX" devices found in system ( sigrok-ok --scan ). One of them is digital (supported, 16 channels). Other show 16 digital channels too, but it is for 2x analog input and not working yet.
Note: Due to the fact that this device has two FX2 chips behind a USB hub inside, this will need extra code to enumerate correctly in sigrok. Do you have this device? Let us know!
Note: Idea how sync 2 chips works. Second FX2 is responsible for reading ADC data only, but it can't initialise processing. It can only get info from first chip that he need to read data -> pin SLWR. So it means that if second chip do conversions only when triggered, then there are exactly that same number of samples read from both chips, from that same time... Look at 48 page of Cypress CY7C68013A-56LTXC (FX2LP) "Slave FIFO Asynchronous Write"
- Main chip: 2x Cypress CY7C68013A-56LTXC (FX2LP)
- Analog-to-Digital converter: 2x Texas Instruments TLC5510I (SO 24pin package)
- I2C EEPROM: ATMLH136 24C02C M Y, place for second EEPROM chip reference.
- USB 2.0 Hub: SMSC USB2512A (QFN 36-pin package)
- Low-dropout voltage regulator: Advanced Monolithic Systems AMS1117-3.3
- CMOS Voltage Converter: 2x 7660 AIBAZ V01828A
- Crystal: 24MHz
- P1 jumper - WRITE PROTECT, Connects WP EEPROM pin  to Vcc. If pin is closed, Write Protection is enabled.
- P3 jumper - EEPROM CONNECTION, connects SDA EEPROM pin  to SDA pins on both CY7C68013A (if open there is no connection)
It looks that place for second eeprom is designed as backup memory. If P4 is closed, and P3 is open, then only spare memory is connected.
Needed for use (I don't know how to remap pins yet)
Current PIN meaning - instead of that what is printed on device (for sigrok 0.8)
First FX2LP pin mappings
Responsible for all digital inputs (0-15) and TRIG. Now it works with latest software version, but channels numbers are scrambled:
|37||CTL1/*FLAGB||ADC [1,2] CLK + RDY1/SLWR on second FX2LP||signal for both ADC and secondary FX2|
Second FX2LP pin mappings
Connected to both ADCs
FX2LP pin mappings
|9||RDY1/SLWR||CL1 on first FXLP and ADC [1,2] CLK||input: ADC_clock, signal to start read data|
|25-32||FD0-FD7||ADC CH1, D1-D8||ADC_data for channel 1|
|42-56,1-3||FD8-FD15||ADC CH2, D1-D8||ADC_data for channel 2|
|45||PA5/FIFOADR1||GND||gnd ? to check|
|47||PA7/*FLAGD/SLCS#||GND||gnd ? to check? probably can be used do distinguish chips|
TODO - check rest of the pins
EEPROM - connected to both (!) CY7C68013A processors
Since we use the open-source fx2lafw firmware for this device, we don't need to know the protocol.