Difference between revisions of "XZL Studio DX"

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== Pin mapping ==
== Pin mapping ==
Current PIN meaning (latest software)
{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
|-
| 4 || 15
|-
| 5 || 14
|-
| 6 || 13
|-
| 7 || 8
|-
| 3 || 9
|-
| 2 || 10
|-
| 1 || 11
|-
| 0 || 12
|-
| TRIG || GND
|-
| 5V || GND
|-
|}


=== First FX2LP pin mappings ===
=== First FX2LP pin mappings ===


Responsible for all digital inputs (0-15) and TRIG. Now it works with latest software version, but channels numbers are scrambled:
Responsible for all digital inputs (0-15) and TRIG. Now it works with latest software version, but channels numbers are scrambled:

Revision as of 10:31, 9 March 2018

XZL_Studio DX
Status planned
Source code fx2lafw
Channels 16 + 2
Samplerate 24MHz
Samplerate (state)
Triggers none (SW-only)
Min/max voltage Digital 0 — 5.4V
Analog ±10V
Threshold voltage Fixed: VIH=1.4V, VIL=0.8V
Memory none
Compression none
Website hotmcu.com

The XZL_Studio DX is a USB-based, 16-channel logic analyzer with up to 24MHz sampling rate, and with 2 additional analog channels.

It is a clone of the CWAV USBee DX.

See XZL_Studio DX/Info for some more details (such as lsusb -vvv output) on the device.

Note: Due to the fact that this device has two FX2 chips behind a USB hub inside, this will need extra code to enumerate correctly in sigrok. Do you have this device? Let us know!

Hardware

Two jumpers:

  • P1 jumper - WRITE PROTECT, Connects WP EEPROM pin [7] to Vcc. If pin is closed, Write Protection is enabled.
  • P3 jumper - EEPROM CONNECTION, connects SDA EEPROM pin [5] to SDA pins on both CY7C68013A (if open there is no connection)

Extra info,
It looks that place for second eeprom is designed as backup memory. If P4 is closed, and P3 is open, then only spare memory is connected.

Pin mapping

Current PIN meaning (latest software)

4 15
5 14
6 13
7 8
3 9
2 10
1 11
0 12
TRIG GND
5V GND


First FX2LP pin mappings

Responsible for all digital inputs (0-15) and TRIG. Now it works with latest software version, but channels numbers are scrambled:

# Pin Destination Remark
FD4 0 digital input
FD5 1 digital input
FD6 2 digital input
FD7 3 digital input
FD3 4 digital input
FD2 5 digital input
FD1 6 digital input
FD0 7 digital input
FD15 8 digital input
FD14 9 digital input
FD13 a digital input
FD8 b digital input
FD9 c digital input
FD10 d digital input
FD11 e digital input
FD12 f digital input
36 CTL0/FLAGA TRIG socket pin
21 Reserved GND


Second FX2LP pin mappings

Connected to both ADCs
FX2LP pin mappings

# Pin Destination Remark
9 RDY1/SLWR ADC [1,2] CLK ADC_clock, both ADC connected to single pin
25-32 FD0-FD7 ADC CH1, D1-D8 ADC_data for channel 1
42-56,1-3 FD8-FD15 ADC CH2, D1-D8 ADC_data for channel 2
45 PA5/FIFOADR1 GND gnd ? to check
47 PA7/*FLAGD/SLCS# GND gnd ? to check? probably can be used do distinguish chips

TODO - check rest of the pins

EEPROM - connected to both (!) CY7C68013A processors

# EEPROM Processor
SDA SDA via jumper
SCL SCL

Photos

Protocol

Since we use the open-source fx2lafw firmware for this device, we don't need to know the protocol.

Resources

TODO.