Difference between revisions of "XMOS XTAG-2"
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== Hardware == | == Hardware == | ||
The main chip is an XMOS XS1-L1 [https://www.xmos.com/en/download/public/XS1-L01A-LQ64-Datasheet%28X1135E%29.pdf XS1-L01A-LQ64 Datasheet]. | |||
In the above picture, the 7-pin header markings are barely unreadable, but that's the jtag port for the xmos chip. From right to left: TDO, TDI, TCK, TMS, TRST#, RST# and GND. | |||
The secondary chip is an [http://ww1.microchip.com/downloads/en/DeviceDoc/3310.pdf SMSC HS Usb 2.0 transceiver]. | |||
== Photos == | == Photos == | ||
<gallery> | <gallery> | ||
File:Xtag-2 front. | File:Xtag-2 front.png|<small>PCB, front</small> | ||
File:Xtag-2 back.jpeg|<small>PCB, back</small> | File:Xtag-2 back.jpeg|<small>PCB, back</small> | ||
</gallery> | </gallery> |
Latest revision as of 12:57, 4 January 2014
Status | planned |
---|---|
Channels | ???? |
Samplerate | 50MHz @ 2ch, 16MHz @ 7ch |
Samplerate (state) | ? |
Triggers | ? |
Min/max voltage | ? |
Threshold voltage | ? |
Memory | ? |
Compression | ? |
Website | xmos.com |
The XMOS XTAG-2 is a USB based, ????-channel logic analyzer with up to 50MHz sampling rate.
The XTAG-2 is actually a debug/eval board for XMOS ICs, but it can be used as a logic analyzer with a firmware written by Henk Muller.
See XMOS XTAG-2/Info for more details (such as lsusb -vvv output) about the device.
Hardware
The main chip is an XMOS XS1-L1 XS1-L01A-LQ64 Datasheet. In the above picture, the 7-pin header markings are barely unreadable, but that's the jtag port for the xmos chip. From right to left: TDO, TDI, TCK, TMS, TRST#, RST# and GND.
The secondary chip is an SMSC HS Usb 2.0 transceiver.
Photos
Protocol
TODO.