Difference between revisions of "Saanlima Pipistrello OLS"

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(Adding comments about FIFO/UART mode and links to required gateware.)
 
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| memory          = 64MiB
| memory          = 64MiB
| compression      = yes
| compression      = yes
| website          = [http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello pipistrello.saanlima.com]
| website          = [http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello saanlima.com]
}}
}}


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All design source for the Pipistrello, including schematics and Eagle board files, are available under the [https://creativecommons.org/licenses/by-sa/4.0/ CC-BY-SA 4.0] license.
All design source for the Pipistrello, including schematics and Eagle board files, are available under the [https://creativecommons.org/licenses/by-sa/4.0/ CC-BY-SA 4.0] license.


See [[Saanlima Pipistrello OLS/Info]] for more details (such as '''lsusb -vvv''' output) about the device.
See [[Saanlima Pipistrello OLS/Info]] for more details (such as '''lsusb -v''' output) about the device.


== Hardware ==
== Hardware ==
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== Protocol ==
== Protocol ==
The protocol used is the same as the [[Openbench Logic Sniffer#Protocol|OLS protocol]], with the addition of commands for edge triggers. See the source code for details.
The protocol used is the same as the [[Openbench Logic Sniffer#Protocol|OLS protocol]], with the addition of commands for edge triggers. See the source code for details.


The Pipistrello needs to be manually flashed with a FPGA bitstream to work with Sigrok. These bitstreams can be downloaded from [http://pipistrello.saanlima.com/index.php?title=Pipistrello_as_Logic_Analyzer the Pipistrello wiki] and the source code is avaliable ([https://sigrok.org/bugzilla/show_bug.cgi?id=1021 See bug #1021 about possible automation for for this]).
The Pipistrello needs to be manually flashed with a FPGA bitstream to work with sigrok. These bitstreams can be downloaded from [http://pipistrello.saanlima.com/index.php?title=Pipistrello_as_Logic_Analyzer the Pipistrello wiki] and the source code is available (see [https://sigrok.org/bugzilla/show_bug.cgi?id=1021 bug #1021] about possible automation for for this).


'''Important''': [http://forum.gadgetfactory.net/index.php?/topic/1864-fpga-as-usb-pia/&do=findComment&comment=18847 The Pipistrello OLS driver only supports using the FIFO mode bitstream and the FTDI chip has been switch to FIFO mode]. If using the UART mode bitstream, use the [[Openbench Logic Sniffer]] driver '''instead''' ([https://sigrok.org/bugzilla/show_bug.cgi?id=1020 See bug #1020 about automated detection for this]).
'''Important''': The Pipistrello OLS driver [http://forum.gadgetfactory.net/index.php?/topic/1864-fpga-as-usb-pia/&do=findComment&comment=18847 only supports using the FIFO mode bitstream] and the FTDI chip has been switched to FIFO mode. If using the UART mode bitstream, use the [[Openbench Logic Sniffer]] driver '''instead''' (see [https://sigrok.org/bugzilla/show_bug.cgi?id=1020 bug #1020] about automated detection for this).


== Photos ==


== Photos ==
<gallery>
<gallery>
File:Saanlima Pipistrello.jpg|<small>Pipistrello board</small>
File:Saanlima Pipistrello.jpg|<small>Pipistrello board</small>
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== Resources ==
== Resources ==
* [http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello Saanlima Pipistrello]
* [http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello Saanlima Pipistrello]
* [http://saanlima.com/forum/viewforum.php?f=3&sid=d8f2eaf446327493dd36a7132da1cc52 Pipistrello support forum]
* [http://saanlima.com/forum/viewforum.php?f=3&sid=d8f2eaf446327493dd36a7132da1cc52 Pipistrello support forum]


[[Category:Device]]
[[Category:Device]]

Latest revision as of 15:36, 2 October 2018

Saanlima Pipistrello OLS
Saanlima Pipistrello-OLS.png
Status supported
Source code pipistrello-ols
Channels 32
Samplerate 0-100MHz
Samplerate (state)
Triggers value, rising/falling edge
Min/max voltage 0V — 5V
Memory 64MiB
Compression yes
Website saanlima.com

The Saanlima Pipistrello is an FPGA development board with many on-board peripherals and pin headers compatible with the Papilio series of boards. It has USB connectivity to a host PC, and, by adding the Saanlima buffer wing, can be used as a replacement for the Openbench Logic Sniffer (OLS).

The FPGA firmware for the OLS has been ported for the Pipistrello, and can thus use the full 64MiB memory to store samples. It also has triggers on rising/falling edges as an extra feature.

All design source for the Pipistrello, including schematics and Eagle board files, are available under the CC-BY-SA 4.0 license.

See Saanlima Pipistrello OLS/Info for more details (such as lsusb -v output) about the device.

Hardware

Pipistrello 2.0 board

Buffer wing

Protocol

The protocol used is the same as the OLS protocol, with the addition of commands for edge triggers. See the source code for details.

The Pipistrello needs to be manually flashed with a FPGA bitstream to work with sigrok. These bitstreams can be downloaded from the Pipistrello wiki and the source code is available (see bug #1021 about possible automation for for this).

Important: The Pipistrello OLS driver only supports using the FIFO mode bitstream and the FTDI chip has been switched to FIFO mode. If using the UART mode bitstream, use the Openbench Logic Sniffer driver instead (see bug #1020 about automated detection for this).

Photos

Resources