Difference between revisions of "Noname XL-LOGIC16-100M"

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(Seems to work now, at least for some versions of the device.)
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| name            = Noname XL-LOGIC16-100M
| name            = Noname XL-LOGIC16-100M
| status          = planned
| status          = planned
| source_code_dir  =  
| source_code_dir  = saleae-logic16
| channels        = 3/6/9/16
| channels        = 3/6/9/16
| samplerate      = 100/50/32/16MHz
| samplerate      = 100/50/32/16MHz
| samplerate_state = —
| samplerate_state = —
| triggers        = ?
| triggers        = none (SW-only)
| voltages        = ?
| voltages        = -0.9V — 6V
| threshold        = ?
| threshold        = configurable:<br />for 1.8V to 3.6V systems: V<sub>IH</sub>=1.4V, V<sub>IL</sub>=0.7V<br />for 5V systems: V<sub>IH</sub>=3.6V, V<sub>IL</sub>=1.4V
| memory          = ?
| memory          = none
| compression      = ?
| compression      = yes
| website          = [http://www.aliexpress.com/item/Free-Shipping-Saleae-24MHz-8Channels-Logic-Analyzer-Fully-Checked-Best-quality-Input-buffered/1731200392.html aliexpress.com]
| website          = [http://www.aliexpress.com/item/Free-Shipping-Saleae-24MHz-8Channels-Logic-Analyzer-Fully-Checked-Best-quality-Input-buffered/1731200392.html aliexpress.com]
}}
}}
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== Hardware ==
== Hardware ==


A single Phillips head screw holds the case together. The parts selection seem to be almost identical to the [[WayEngineer Saleae16]] but that page doesn't have any internal photos for full comparison.
A single Phillips head screw holds the case together. Most notable are the complete lack of test points or programming headers! There are some unpopulated resistor/capacitor pairs on the backside.
 
Most notable are the complete lack of test points or programming headers! There are some unpopulated resistor/capacitor pairs on the backside.


* '''FPGA''': [http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/spartan-3a.html Xilinx Spartan-3A XC3S200A], 200K gates ([http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf datasheeet])
* '''FPGA''': [http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/spartan-3a.html Xilinx Spartan-3A XC3S200A], 200K gates ([http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf datasheeet])
* '''USB interface chip''': [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A-56PVXC (FX2LP)] ([http://www.cypress.com/?docID=34060 datasheet])
* '''USB interface chip''': [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A-56PVXC (FX2LP)] ([http://www.cypress.com/?docID=34060 datasheet])
* '''I2C EEPROM''': 2Kbit [http://www.atmel.com/devices/AT24C02B.aspx Atmel 24C02B] (markings: "ATMEL317 24C02BN SU27 D") ([http://www.atmel.com/Images/doc5126.pdf datasheet])
* '''I2C EEPROM''': 2Kbit [http://www.atmel.com/devices/AT24C02B.aspx Atmel 24C02B] (markings: "ATMEL317 24C02BN SU27 D") ([http://www.atmel.com/Images/doc5126.pdf datasheet])
* '''16-Bit 2.5V to 3.3V/3.3V to 5V level shifting transceiver with 3-state outputs''': [http://www.ti.com/product/SN74ALVC164245 TI SN74ALVC164245] ([http://www.ti.com/lit/gpn/sn74alvc164245 datasheet])
* '''3.3V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-3.3] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''3.3V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-3.3] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''1.2V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-1.2] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''1.2V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-1.2] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
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== Protocol ==
== Protocol ==


Presumably the same as for the [[Saleae Logic16]].
See [[Saleae Logic16#Protocol]].


== Resources ==
== Resources ==

Revision as of 23:42, 27 November 2014

Noname XL-LOGIC16-100M
Noname xl logic16 100m mugshot.png
Status planned
Source code saleae-logic16
Channels 3/6/9/16
Samplerate 100/50/32/16MHz
Samplerate (state)
Triggers none (SW-only)
Min/max voltage -0.9V — 6V
Threshold voltage configurable:
for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V
for 5V systems: VIH=3.6V, VIL=1.4V
Memory none
Compression yes
Website aliexpress.com

The Noname XL-LOGIC16-100M is a USB-based, 16-channel logic analyzer with up to 100MHz sampling rate.

It is labelled and sold as a Saleae Logic16 clone, and comes with "modified" Saleae Logic software on a CD-ROM.

See Noname XL-LOGIC16-100M/Info for more details (such as lsusb -v output) about the device.

Hardware

A single Phillips head screw holds the case together. Most notable are the complete lack of test points or programming headers! There are some unpopulated resistor/capacitor pairs on the backside.

Three LEDs (USB/green, COM/blue, and RUN/red) are on the board.

Photos

Photos from another unit:

Photos from yet another unit with JTAG and other resistor values:

Firmware

You can use the sigrok-fwextract-saleae-logic16 tool to extract (from the "Logic" Linux binary) the FX2 firmware and the FPGA bitstreams, exactly as for a real Saleae Logic16. Note, the md5sum of the FX2 firmware is identical to the original Saleae firmware, but the FPGA bitstreams are different. Attempting to connect to this device with the "modified" FPGA bitstream, which _works_ with the vendor supplied "modified" Logic software fails to load in sigrok, with a FPGA version mismatch. The FX2 firmware loads successfully, at least in as much as the LED blinks a heartbeat pattern as expected.

Protocol

See Saleae Logic16#Protocol.

Resources