Difference between revisions of "Main Page"
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<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#cfdfff; align:right; border:1px solid #aabbcc;"> | <div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#cfdfff; align:right; border:1px solid #aabbcc;"> | ||
The '''sigrok''' project aims at creating a portable, cross-platform, Free/Libre/Open-Source logic analyzer software that supports various (usually USB-based) logic analyzer hardware products. The code is licensed under the terms of the '''GNU GPL'''. | The '''sigrok''' project aims at creating a portable, cross-platform, Free/Libre/Open-Source logic analyzer software that supports various (usually USB-based) logic analyzer hardware products. The code is licensed under the terms of the '''GNU GPL'''. Some of the design goals and features include: | ||
* '''Broad hardware support'''. Supports a wide variety of logic analyzers from various vendors with different capabilities. | * '''Broad hardware support'''. Supports a wide variety of logic analyzers from various vendors with different capabilities. | ||
* '''Cross-platform'''. Works on [[Linux]], [[Mac OS X]], [[Windows]], and [[FreeBSD]], and on many architectures including x86, ARM, Sparc and PowerPC. | * '''Cross-platform'''. Works on [[Linux]], [[Mac OS X]], [[Windows]], and [[FreeBSD]], and on many architectures including x86, ARM, Sparc and PowerPC. | ||
* '''Scriptable protocol decoding'''. Extendable with [[protocol decoders]] and analyzers written in Python. | * '''Scriptable protocol decoding'''. Extendable with [[protocol decoders]] and analyzers written in Python. | ||
* '''Format support'''. Supports various [[Input output formats|input and output formats]] (raw, ASCII, hex, CSV, gnuplot, [http://en.wikipedia.org/wiki/Value_change_dump VCD], others). | * '''Format support'''. Supports various [[Input output formats|input and output formats]] (raw, ASCII, hex, CSV, gnuplot, [http://en.wikipedia.org/wiki/Value_change_dump VCD], others). | ||
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== <span style="font-variant:small-caps">Supported hardware</span> == | == <span style="font-variant:small-caps">Supported hardware</span> == | ||
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[[File:Logic analyzer collection.png|center|thumb|Small logic analyzer collection]] | [[File:Logic analyzer collection.png|center|thumb|<small>Small logic analyzer collection</small>]] | ||
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'''IMPORTANT: Please note that (unless explicitly specified otherwise) all contents in this wiki (including text and images) are released under the <span style="color:red">CC-BY-SA 3.0</span> license. If you don't want that, please explicitly specify another free-ish license when adding pages or images to the wiki!''' | '''IMPORTANT: Please note that (unless explicitly specified otherwise) all contents in this wiki (including text and images) are released under the <span style="color:red">CC-BY-SA 3.0</span> license. If you don't want that, please explicitly specify another free-ish license when adding pages or images to the wiki!''' | ||
</small> | |||
__NOTOC__ | __NOTOC__ | ||
__NOEDITSECTION__ | __NOEDITSECTION__ | ||
Revision as of 17:57, 25 April 2011
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The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source logic analyzer software that supports various (usually USB-based) logic analyzer hardware products. The code is licensed under the terms of the GNU GPL. Some of the design goals and features include:
Supported hardware
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 News
|
IMPORTANT: Please note that (unless explicitly specified otherwise) all contents in this wiki (including text and images) are released under the CC-BY-SA 3.0 license. If you don't want that, please explicitly specify another free-ish license when adding pages or images to the wiki!