JTAGulator
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 | |
| Status | supported |
|---|---|
| Source code | openbench-logic-sniffer |
| Channels | 24 |
| Samplerate | 1.2MHz |
| Samplerate (state) | — |
| Triggers | 4 |
| Min/max voltage | 1.4 - 3.3V |
| Memory | 1024 samples |
| Compression | none |
| Website | jtagulator.com |
The Grand Idea Studio JTAGulator is a tool to identify interfaces. It also supports a logic analyzer mode, and can thus be used to capture signals. See the vendor's logic analyzer mode wiki page for details.
See JTAGulator/Info for lsusb details and SUMP metadata.
Hardware
- Parallax Propeller P8X32A
- FTDI FT232RL
- TI TXS0108EPWR
Photos
JTAGulator Rev B, front
JTAGulator, annotated front
Protocol
JTAGulator (in logic analyzer mode) implements the "extended SUMP" protocol.