Difference between revisions of "DreamSourceLab DSLogic Plus"
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| voltages = -0.6V — 6V, +-30V with provided probe-wires | | voltages = -0.6V — 6V, +-30V with provided probe-wires | ||
| threshold = configurable: 0-5V (0.1V increments) | | threshold = configurable: 0-5V (0.1V increments) | ||
| memory = | | memory = 256MBit | ||
| compression = yes | | compression = yes | ||
| website = [http://www.dreamsourcelab.com/dslogic.html dreamsourcelab.com] | | website = [http://www.dreamsourcelab.com/dslogic.html dreamsourcelab.com] | ||
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* [http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/ Xilinx XC6SLX9] U3: Spartan-6 FPGA (TQG144BIV13337) | * [http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/ Xilinx XC6SLX9] U3: Spartan-6 FPGA (TQG144BIV13337) | ||
* [https://www.alliancememory.com/wp-content/uploads/pdf/dram/256Mb-AS4C16M16SA-C&I_V3.0_March%202015.pdf Alliance AS4C16M16SA-7TCN] U1: 256Mbit SDRAM | * Sample memory: | ||
** Original version: [https://www.alliancememory.com/wp-content/uploads/pdf/dram/256Mb-AS4C16M16SA-C&I_V3.0_March%202015.pdf Alliance AS4C16M16SA-7TCN] U1: 256Mbit SDRAM | |||
** V211: [https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/256Mb_sdr.pdf Micron MT48LC16M16A2 256Mbit SDRAM] | |||
* [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A] U2: FX2LP USB interface chip | * [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A] U2: FX2LP USB interface chip | ||
* [http://www.st.com/content/ccc/resource/technical/document/datasheet/59/05/c9/5b/7b/41/48/b6/CD00259167.pdf/files/CD00259167.pdf/jcr:content/translations/en.CD00259167.pdf 128Kbit I²C EEPROM] U4: ST M24128-BR | * [http://www.st.com/content/ccc/resource/technical/document/datasheet/59/05/c9/5b/7b/41/48/b6/CD00259167.pdf/files/CD00259167.pdf/jcr:content/translations/en.CD00259167.pdf 128Kbit I²C EEPROM] U4: ST M24128-BR | ||
Revision as of 13:26, 11 October 2018
 | |
| Status | supported |
|---|---|
| Source code | dreamsourcelab-dslogic |
| Channels | 1-16 |
| Samplerate | 400MHz(4ch), 200MHz(8ch), 100MHz(16ch) |
| Samplerate (state) | 30MHz (?) or 50MHz (?) |
| Triggers | high, low, rising, falling, edge, multi-stage triggers |
| Min/max voltage | -0.6V — 6V, +-30V with provided probe-wires |
| Threshold voltage | configurable: 0-5V (0.1V increments) |
| Memory | 256MBit |
| Compression | yes |
| Website | dreamsourcelab.com |
The DreamSourceLab DSLogic Plus is a 16-channel USB-based logic analyzer, with sampling rates up to 400MHz (when using only 4 channels). This differs slightly from the original DSLogic product in its configurable threshold voltage and different PCB layout. DreamSourceLab doesn't make the distinction between these two products very clear on their website.
See DreamSourceLab DSLogic Plus/Info for more details (such as lsusb -v output) about the device.
Hardware
- Xilinx XC6SLX9 U3: Spartan-6 FPGA (TQG144BIV13337)
- Sample memory:
- Original version: Alliance AS4C16M16SA-7TCN U1: 256Mbit SDRAM
- V211: Micron MT48LC16M16A2 256Mbit SDRAM
- Cypress CY7C68013A U2: FX2LP USB interface chip
- 128Kbit I²C EEPROM U4: ST M24128-BR
- TI TPS62400 U10: Dual, Adjustable, 400mA and 600mA, 2.25MHz Step-Down Converter (3.3V and 1.2V output)
- 24.0Mhz Crystal Y1: YSX321SL series 20ppm (markings: YXC 24.0SBJI)
Photos
Device:
PCB, front
PCB, back (mirrored)
PCB V211, front
PCB V211, back
Cables:
Probe cable circuit
Firmware
See DreamSourceLab DSLogic#Firmware.