ChronoVu LA16

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Revision as of 16:56, 13 April 2014 by Uwe Hermann (talk | contribs) (The ChronoVu LA16 is now supported.)
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ChronoVu LA16
Chronovu la16.png
Status supported
Source code chronovu-la
Channels 16
Samplerate 200MHz
Samplerate (state)
Triggers high/low/any state, rising/falling/any edge
Min/max voltage -0.5 — 6V
Threshold voltage Fixed: VIH=2V—5.5V, VIL=0V—0.8V
Memory 8Mbyte (SDRAM)
Compression none
Website chronovu.com

The ChronoVu LA16 is a USB-based 16-channel logic analyzer with up to 200MHz sampling rate.

It features a Xilinx FPGA for sampling, 8MByte of built-in SDRAM to store the samples, and can trigger on low/high/any state or rising/falling/any edge of any combination of probes. After the 8MByte sample buffer is full, the data is transferred to the host via an FTDI FT245RL chip.

See ChronoVu LA16/Info for more details (such as lsusb -v output) about the device.

Many thanks to the vendor (ChronoVu) for freely providing information on the protocol used to communicate with the device. This helped us implement the libsigrok hardware driver more quickly. We're happy to see more open-source friendly vendors support sigrok!

Hardware

  • Xilinx XC3S50AN
  • Micron MT48LC2M32B2 SDRAM (8 MByte)
  • FTDI FT245RL
  • ...

Photos

TODO.

Protocol

Similar to the ChonoVu LA8 protocol, more info will follow.

Resources