Difference between revisions of "ASIX OMEGA"
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The ASIX OMEGA is new version of [[ASIX SIGMA]] logic analyzer. It is a 16 channel logic analyzer with sample rate support up to 400 MHz and with 512 Mbit on-board memory. It uses Huffman compression and achieves much better compression ratio than SIGMA. Two or more OMEGA analyzers can be connected in with synchronization cable and use more inputs. | The ASIX OMEGA is new version of [[ASIX SIGMA]] logic analyzer. It is a 16 channel logic analyzer with sample rate support up to 400 MHz and with 512 Mbit on-board memory. It uses Huffman compression and achieves much better compression ratio than SIGMA. Two or more OMEGA analyzers can be connected in with synchronization cable and use more inputs. | ||
ASIX OMEGA will be | [[Category:Device]] | ||
[[Category:Logic analyzer]] | |||
{{Infobox logic analyzer | |||
| image = [[File:ASIX Omega.png|180px]] | |||
| name = ASIX Omega | |||
| status = in progress | |||
| source_code_dir = asix-sigma | |||
| channels = 16 | |||
| samplerate = 400MHz @ 8ch, 200MHz @ 16 | |||
| samplerate_state = ? | |||
| triggers = value, edge, duration, sequence, counter, logical ops | |||
| voltages = -0.3V — 5.5V | |||
| threshold = Fixed: VIH=2.0V, VIL=0.8V (suitable for TTL, LVTTL, 2.7-5.5V CMOS) | |||
| memory = 512 megabit | |||
| compression = "real-time hardware data compression" | |||
| website = [http://www.asix.net/dbg_omega.htm asix.net] | |||
}} | |||
The '''ASIX OMEGA''' is a USB-based, 16-channel logic analyzer with up to 400MHz sampling rate. | |||
See [[ASIX OMEGA/Info]] for more details (such as '''lsusb -vvv''' output) about the device. | |||
== Hardware == | |||
* Xilinx Spartan [http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf XC3S200A] (FPGA) | |||
* FTDI [http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf FT232HL] (USB connectivity) | |||
* SOT23-5 EEPROM for FTDI FT232H | |||
* 2 x NXP [http://www.nxp.com/documents/data_sheet/74LVC_LVCH245A.pdf LVC245A] (buffer / level shifter) | |||
* [http://www.ti.com/lit/ds/scas290q/scas290q.pdf LC125A] (buffer / level shifter) | |||
* 2 x [https://www.micron.com/~/media/documents/products/data-sheet/dram/256mb_sdr.pdf MT48LC16M16A2B4-7E] (DRAM for sample data) | |||
* [https://www.idt.com/document/dst/570-datasheet ICS570BL] (IDT, "multiplier and zero delay buffer", trigger clock sync?) | |||
* [http://www.ti.com/lit/ds/symlink/sn65mlvd204a.pdf MF204A] (LVDS line driver) | |||
* multiple regulators, and stuff ... | |||
== Photos == | |||
<gallery> | |||
File:ASIX_Omega.png | |||
File:Omega-Top.jpg | |||
File:Omega-Bottom.jpg | |||
</gallery> | |||
== Documentation == | |||
TODO | |||
== Example usage == | |||
TODO | |||
(will be using the Asix Sigma/Sigma2 driver -- models can be told from serial numbers) | |||
== Firmware == | |||
TODO | |||
== Resources == | |||
TODO | |||
[[Category:Device]] | |||
[[Category:Logic analyzer]] | |||
[[Category:In progress]] |
Revision as of 00:16, 27 December 2016
The ASIX OMEGA is new version of ASIX SIGMA logic analyzer. It is a 16 channel logic analyzer with sample rate support up to 400 MHz and with 512 Mbit on-board memory. It uses Huffman compression and achieves much better compression ratio than SIGMA. Two or more OMEGA analyzers can be connected in with synchronization cable and use more inputs.
Status | in progress |
---|---|
Source code | asix-sigma |
Channels | 16 |
Samplerate | 400MHz @ 8ch, 200MHz @ 16 |
Samplerate (state) | ? |
Triggers | value, edge, duration, sequence, counter, logical ops |
Min/max voltage | -0.3V — 5.5V |
Threshold voltage | Fixed: VIH=2.0V, VIL=0.8V (suitable for TTL, LVTTL, 2.7-5.5V CMOS) |
Memory | 512 megabit |
Compression | "real-time hardware data compression" |
Website | asix.net |
The ASIX OMEGA is a USB-based, 16-channel logic analyzer with up to 400MHz sampling rate.
See ASIX OMEGA/Info for more details (such as lsusb -vvv output) about the device.
Hardware
- Xilinx Spartan XC3S200A (FPGA)
- FTDI FT232HL (USB connectivity)
- SOT23-5 EEPROM for FTDI FT232H
- 2 x NXP LVC245A (buffer / level shifter)
- LC125A (buffer / level shifter)
- 2 x MT48LC16M16A2B4-7E (DRAM for sample data)
- ICS570BL (IDT, "multiplier and zero delay buffer", trigger clock sync?)
- MF204A (LVDS line driver)
- multiple regulators, and stuff ...
Photos
Documentation
TODO
Example usage
TODO
(will be using the Asix Sigma/Sigma2 driver -- models can be told from serial numbers)
Firmware
TODO
Resources
TODO