sigrok - User contributions [en]

LeCroy LogicStudio

2016-05-17T17:29:20Z

Tilman: Formatting

{{Infobox logic analyzer
| image = [[File:Lecroy logicstudio16 mugshot.png|180px]]
| name = LeCroy LogicStudio
| status = supported
| source_code_dir = lecroy-logicstudio
| channels = 16
| samplerate = 1GHz (@ 8ch), 500MHz (@ 16ch)
| samplerate_state = —
| triggers = high/low state, rising/falling/any edge, more
| voltages = ?
| threshold = configurable: 0.0V — 7.0V
| memory = 40 KB
| compression = none
| website = [http://teledynelecroy.com/logicstudio/ teledynelecroy.com]
}}

The '''LeCroy LogicStudio''' is a USB-based, 16-channel logic analyzer with 1GHz samplerate.

When all 16 channels are enabled, the maximum samplerate is limited to at most 500MHz. Either the lower eight or the upper eight channels may be disabled for an increased samplerate of up to 1GHz. The device offers a continuous acquisition mode where all inputs are sampled at a frequency of 1kHz. Its internal protocol decoder supports UART, I2C and SPI.

See [[LeCroy LogicStudio/Info]] for more details (such as '''lsusb -v''' output) about the device.

== Hardware ==

* '''FPGA''': Xilinx Spartan-6 XC6SLX16
* '''USB interface''': [http://www.cypress.com/?docID=45142 Cypress CY7C68013A]
* '''Crystal (FX2LP):''' 24.000MHz
* '''Crystal (FPGA):''' Unknown, xpress0?

== Photos ==

<gallery>
File:Lecroy-logicstudio.jpg|Device, top
File:Lecroy-logicstudio-pcb.jpg|PCB, front
File:Lecroy-logicstudio-fpga.jpg|FPGA
File:Lecroy-logicstudio-usb.jpg|FX2
</gallery>

== Protocol ==

=== Trigger capabilities ===

The device has both standard logic triggers as well as triggers that operate on data produced by its internal protocol decoder.
There are two logic trigger blocks A and B which can optionally be combined in the following ways:
* A AND B
* A OR B
* A THEN B

Each logic trigger block offers the following match criteria:
* Rising edge
* Falling edge
* Any edge
* Level 0 (including pulse width)
* Level 1 (ditto)
* Qualified edge triggers (trigger on rising/falling/any edge while another signal is high/low).

Multiple edge triggers in the same block are OR'd, while multiple level triggers in the same block are AND'ed.
Each trigger block can further be configured with a number of times that the trigger criteria need to match before the trigger fires.

=== Internals ===

The device initially shows up as VID:PID 0x5ff:0xa001 on the USB bus. It then requires a firmware upload to its FX2LP chip, after which the original USB device disappears and a new one shows up, with VID:PID 0x5ff:0xa002.

The bitstreams for the FPGA come in two versions: one which enables all 16 channels, and one which only enables either the bottom 8 or the top 8 channels. If the first bitstream is uploaded, the maximum allowed sample rate is 500MHz. If the second bitstream is uploaded, the device can sample at up to 1GHz. In the latter case, a separate command controls whether the lower or the upper channels are enabled.

Samples are stored in the device's 40 KB memory. That memory block is used as a ringbuffer; samples are continuously written to it (thus overwriting old data if necessary) until the user-programmed trigger fires ''and'' the requested number of post-trigger samples have been acquired.
At that point, you may retrieve the ringbuffer's contents from the device.

=== USB endpoints ===

# Endpoint 1 is used by the device to send acquisition status messages to the host.
# Endpoint 6 is used to upload the FPGA bitstream.
# Endpoint 2 is used to retrieve the device's samplebuffer.

Vendor requests are used to read or write control registers.

See [[LeCroy LogicStudio/Info]] for an '''lsusb -v'''.

== Firmware ==

=== Revisions ===

As of October 2015, the latest released LeCroy LogicStudio software ships with FPGA bitstreams that are 464196 bytes and have the following hashes:
* md5(lecroy-logicstudio16-16.bitstream) = 1ab904704def72f18543d9d7aa929002
* md5(lecroy-logicstudio16-8.bitstream) = 5763c67cb762c85c8b1d09dc1f239acb

The FX2LP firmware is 4250 bytes:
* md5(lecroy-logicstudio16-fx2lp.fw) = 1638e2a5ef211c10f48405c1c16a057f

=== Extracting lecroy-logicstudio16-fx2lp.fw from the Windows driver ===

# Get https://ftp.dlitz.net/pub/dlitz/cyusb-fw-extract/0.1/cyusb-fw-extract.py
# Run that script on the SPT file that is included in the Windows installation:
<code>
python cyusb-fw-extract.py -o converted LogicStudio16Load.spt
</code>
# Remove the comments (first two lines) from the top of converted_2.ihx.
# Use objcopy (or any other hex/bin converter) to convert from ihex to binary:
<code>
objcopy -I ihex -O binary converted_2.ihx lecroy-logicstudio16-fx2lp.fw
</code>

== Resources ==

* [http://teledynelecroy.com/doc/docview.aspx?id=6378 Datasheet]
* [http://teledynelecroy.com/doc/docview.aspx?id=7699 Manual]
* [http://teledynelecroy.com/support/softwaredownload/logicstudio.aspx Vendor software]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Supported]]

LeCroy LogicStudio

2016-05-17T17:28:24Z

Tilman: Document how to exxtract lecroy-logicstudio16-fx2lp.fw from the Windows driver

{{Infobox logic analyzer
| image = [[File:Lecroy logicstudio16 mugshot.png|180px]]
| name = LeCroy LogicStudio
| status = supported
| source_code_dir = lecroy-logicstudio
| channels = 16
| samplerate = 1GHz (@ 8ch), 500MHz (@ 16ch)
| samplerate_state = —
| triggers = high/low state, rising/falling/any edge, more
| voltages = ?
| threshold = configurable: 0.0V — 7.0V
| memory = 40 KB
| compression = none
| website = [http://teledynelecroy.com/logicstudio/ teledynelecroy.com]
}}

The '''LeCroy LogicStudio''' is a USB-based, 16-channel logic analyzer with 1GHz samplerate.

When all 16 channels are enabled, the maximum samplerate is limited to at most 500MHz. Either the lower eight or the upper eight channels may be disabled for an increased samplerate of up to 1GHz. The device offers a continuous acquisition mode where all inputs are sampled at a frequency of 1kHz. Its internal protocol decoder supports UART, I2C and SPI.

See [[LeCroy LogicStudio/Info]] for more details (such as '''lsusb -v''' output) about the device.

== Hardware ==

* '''FPGA''': Xilinx Spartan-6 XC6SLX16
* '''USB interface''': [http://www.cypress.com/?docID=45142 Cypress CY7C68013A]
* '''Crystal (FX2LP):''' 24.000MHz
* '''Crystal (FPGA):''' Unknown, xpress0?

== Photos ==

<gallery>
File:Lecroy-logicstudio.jpg|Device, top
File:Lecroy-logicstudio-pcb.jpg|PCB, front
File:Lecroy-logicstudio-fpga.jpg|FPGA
File:Lecroy-logicstudio-usb.jpg|FX2
</gallery>

== Protocol ==

=== Trigger capabilities ===

The device has both standard logic triggers as well as triggers that operate on data produced by its internal protocol decoder.
There are two logic trigger blocks A and B which can optionally be combined in the following ways:
* A AND B
* A OR B
* A THEN B

Each logic trigger block offers the following match criteria:
* Rising edge
* Falling edge
* Any edge
* Level 0 (including pulse width)
* Level 1 (ditto)
* Qualified edge triggers (trigger on rising/falling/any edge while another signal is high/low).

Multiple edge triggers in the same block are OR'd, while multiple level triggers in the same block are AND'ed.
Each trigger block can further be configured with a number of times that the trigger criteria need to match before the trigger fires.

=== Internals ===

The device initially shows up as VID:PID 0x5ff:0xa001 on the USB bus. It then requires a firmware upload to its FX2LP chip, after which the original USB device disappears and a new one shows up, with VID:PID 0x5ff:0xa002.

The bitstreams for the FPGA come in two versions: one which enables all 16 channels, and one which only enables either the bottom 8 or the top 8 channels. If the first bitstream is uploaded, the maximum allowed sample rate is 500MHz. If the second bitstream is uploaded, the device can sample at up to 1GHz. In the latter case, a separate command controls whether the lower or the upper channels are enabled.

Samples are stored in the device's 40 KB memory. That memory block is used as a ringbuffer; samples are continuously written to it (thus overwriting old data if necessary) until the user-programmed trigger fires ''and'' the requested number of post-trigger samples have been acquired.
At that point, you may retrieve the ringbuffer's contents from the device.

=== USB endpoints ===

# Endpoint 1 is used by the device to send acquisition status messages to the host.
# Endpoint 6 is used to upload the FPGA bitstream.
# Endpoint 2 is used to retrieve the device's samplebuffer.

Vendor requests are used to read or write control registers.

See [[LeCroy LogicStudio/Info]] for an '''lsusb -v'''.

=== Firmware revisions ===

As of October 2015, the latest released LeCroy LogicStudio software ships with FPGA bitstreams that are 464196 bytes and have the following hashes:
* md5(lecroy-logicstudio16-16.bitstream) = 1ab904704def72f18543d9d7aa929002
* md5(lecroy-logicstudio16-8.bitstream) = 5763c67cb762c85c8b1d09dc1f239acb

The FX2LP firmware is 4250 bytes:
* md5(lecroy-logicstudio16-fx2lp.fw) = 1638e2a5ef211c10f48405c1c16a057f

=== Extracting lecroy-logicstudio16-fx2lp.fw from the Windows driver ===

# Get https://ftp.dlitz.net/pub/dlitz/cyusb-fw-extract/0.1/cyusb-fw-extract.py
# Run that script on the SPT file that is included in the Windows installation:
<code>
python cyusb-fw-extract.py -o converted LogicStudio16Load.spt
</code>
# Remove the comments (first two lines) from the top of converted_2.ihx.
# Use objcopy (or any other hex/bin converter) to convert from ihex to binary:
<code>
objcopy -I ihex -O binary converted_2.ihx lecroy-logicstudio16-fx2lp.fw
</code>

== Resources ==

* [http://teledynelecroy.com/doc/docview.aspx?id=6378 Datasheet]
* [http://teledynelecroy.com/doc/docview.aspx?id=7699 Manual]
* [http://teledynelecroy.com/support/softwaredownload/logicstudio.aspx Vendor software]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Supported]]

LeCroy LogicStudio/Info

2016-01-30T08:05:16Z

Tilman: Add lsusb output before FX2 firmware upload

== lsusb (before FX2 firmware upload) ==

$ '''lsusb -v'''
Bus 001 Device 005: ID '''05ff:a001 LeCroy Corp.'''
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 255 Vendor Specific Class
bDeviceSubClass 255 Vendor Specific Subclass
bDeviceProtocol 255 Vendor Specific Protocol
bMaxPacketSize0 64
idVendor 0x05ff '''LeCroy Corp.'''
idProduct 0xa001
bcdDevice 0.00
iManufacturer 0
iProduct 0
iSerial 0
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 171
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0x80
(Bus Powered)
MaxPower 100mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 0
bInterfaceClass 255 Vendor Specific Class
bInterfaceSubClass 255 Vendor Specific Subclass
bInterfaceProtocol 255 Vendor Specific Protocol
iInterface 0
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 1
bNumEndpoints 6
bInterfaceClass 255 Vendor Specific Class
bInterfaceSubClass 255 Vendor Specific Subclass
bInterfaceProtocol 255 Vendor Specific Protocol
iInterface 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x01 '''EP 1 OUT'''
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 '''EP 1 IN'''
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 '''EP 2 OUT'''
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x04 '''EP 4 OUT'''
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x86 '''EP 6 IN'''
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x88 '''EP 8 IN'''
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 2
bNumEndpoints 6
bInterfaceClass 255 Vendor Specific Class
bInterfaceSubClass 255 Vendor Specific Subclass
bInterfaceProtocol 255 Vendor Specific Protocol
iInterface 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x01 '''EP 1 OUT'''
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0040 1x 64 bytes
bInterval 1
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 '''EP 1 IN'''
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0040 1x 64 bytes
bInterval 1
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 '''EP 2 OUT'''
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 1
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x04 '''EP 4 OUT'''
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x86 '''EP 6 IN'''
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 1
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x88 '''EP 8 IN'''
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 3
bNumEndpoints 6
bInterfaceClass 255 Vendor Specific Class
bInterfaceSubClass 255 Vendor Specific Subclass
bInterfaceProtocol 255 Vendor Specific Protocol
iInterface 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x01 '''EP 1 OUT'''
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0040 1x 64 bytes
bInterval 1
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 '''EP 1 IN'''
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0040 1x 64 bytes
bInterval 1
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 '''EP 2 OUT'''
bmAttributes 1
Transfer Type Isochronous
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 1
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x04 '''EP 4 OUT'''
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x86 '''EP 6 IN'''
bmAttributes 1
Transfer Type Isochronous
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 1
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x88 '''EP 8 IN'''
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Device Qualifier (for other device speed):
bLength 10
bDescriptorType 6
bcdUSB 2.00
bDeviceClass 255 Vendor Specific Class
bDeviceSubClass 255 Vendor Specific Subclass
bDeviceProtocol 255 Vendor Specific Protocol
bMaxPacketSize0 64
bNumConfigurations 1
Device Status: 0x0000
(Bus Powered)

'''


== lsusb (after FX2 firmware upload) ==


$ '''lsusb -v'''
Bus 001 Device 005: ID '''05ff:a002 LeCroy Corp.'''
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 0
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
idVendor 0x05ff '''LeCroy Corp.'''
idProduct 0xa002
bcdDevice 0.01
iManufacturer 1 '''LeCroy'''
iProduct 2 '''LogicStudio 16'''
iSerial 0
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 46
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0x80
(Bus Powered)
MaxPower 300mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 4
bInterfaceClass 255 '''Vendor Specific Class'''
bInterfaceSubClass 0
bInterfaceProtocol 0
iInterface 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 '''EP 1 IN'''
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0040 1x 64 bytes
bInterval 4
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x01 '''EP 1 OUT'''
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0040 1x 64 bytes
bInterval 6
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x82 '''EP 2 IN'''
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x06 '''EP 6 OUT'''
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Device Qualifier (for other device speed):
bLength 10
bDescriptorType 6
bcdUSB 2.00
bDeviceClass 0
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
bNumConfigurations 1
Device Status: 0x0000
(Bus Powered)

LeCroy LogicStudio

2015-12-03T20:39:44Z

Tilman: Voltage thresholds can be configured from 0.0V to 7.0V

{{Infobox logic analyzer
| image = [[File:Lecroy-logicstudio.jpg|180px]]
| name = LeCroy LogicStudio
| status =
| source_code_dir =
| channels = 16
| samplerate = up to 1GHz (when sampling 8 channels) ; up to 500MHz (when sampling 16 channels)
| samplerate_state = —
| triggers = high/low state, rising/falling/any edge, more
| voltages = ?
| threshold = 0.0V - 7.0V
| memory = 40 KB
| compression = none
| website = [http://teledynelecroy.com/logicstudio/ teledynelecroy.com]
}}

The '''LeCroy LogicStudio''' is an USB logic analyzer with 16 channels that offers up to 1GHz samplerate. When all 16 channels are enabled, the maximum samplerate is limited to at most 500MHz. Either the lower eight or the upper eight channels may be disabled for an increased samplerate of up to 1GHz. The device offers a continuous acquisition mode where all inputs are sampled at a frequency of 1kHz. Its internal protocol decoder supports UART, I2C and SPI.

== Hardware ==
* '''FPGA''': Xilinx Spartan-6 XC6SLX16
* '''USB interface''': [http://www.cypress.com/?docID=45142 Cypress CY7C68013A]
* '''Crystal (FX2LP):''' 24.000MHz
* '''Crystal (FPGA):''' Unknown, xpress0?

== Photos ==
<gallery>
File:Lecroy-logicstudio.jpg|LogicStudio
File:Lecroy-logicstudio-pcb.jpg|PCB, front
File:Lecroy-logicstudio-fpga.jpg|FPGA
File:Lecroy-logicstudio-usb.jpg|FX2
</gallery>

== Trigger Capabilities ==

The device has both standard logic triggers as well as triggers that operate on data produced by its internal protocol decoder.
There are two logic trigger blocks A and B which can optionally be combined in the following ways:
* A AND B
* A OR B
* A THEN B

Each logic trigger block offers the following match criteria:
* Rising edge
* Falling edge
* Any edge
* Level 0 (including pulse width)
* Level 1 (ditto)
* Qualified edge triggers (trigger on rising/falling/any edge while another signal is high/low).

Multiple edge triggers in the same block are OR'd, while multiple level triggers in the same block are AND'ed.
Each trigger block can further be configured with a number of times that the trigger criteria need to match before the trigger fires.

== Internals ==

The device initially shows up as VID:PID 0x5ff:0xa001 on the USB bus. It then requires a firmware upload to its FX2LP chip, after which the original USB device disappears and a new one shows up, with VID:PID 0x5ff:0xa002.

The bitstreams for the FPGA come in two versions: one which enables all 16 channels, and one which only enables either the bottom 8 or the top 8 channels. If the first bitstream is uploaded, the maximum allowed sample rate is 500MHz. If the second bitstream is uploaded, the device can sample at up to 1GHz. In the latter case, a separate command controls whether the lower or the upper channels are enabled.

Samples are stored in the device's 40 KB memory. That memory block is used as a ringbuffer; samples are continously written to it (thus overwriting old data if necessary) until the user-programmed trigger fires _and_ the requested number of post-trigger samples have been acquired.
At that point, you may retrieve the ringbuffer's contents from the device.

== Firmware revisions ==

As of October 2015, the latest released LeCroy LogicStudio software ships with FPGA bitstreams that are 464196 bytes and have the following hashes:
* md5(lecroy-logicstudio16-16.bitstream) = 1ab904704def72f18543d9d7aa929002
* md5(lecroy-logicstudio16-8.bitstream) = 5763c67cb762c85c8b1d09dc1f239acb

The FX2LP firmware is 4250 bytes:
* md5(lecroy-logicstudio16-fx2lp.fw) = 1638e2a5ef211c10f48405c1c16a057f

LeCroy LogicStudio

2015-12-03T20:38:08Z

Tilman: Short description of how the device works

{{Infobox logic analyzer
| image = [[File:Lecroy-logicstudio.jpg|180px]]
| name = LeCroy LogicStudio
| status =
| source_code_dir =
| channels = 16
| samplerate = up to 1GHz (when sampling 8 channels) ; up to 500MHz (when sampling 16 channels)
| samplerate_state = —
| triggers = high/low state, rising/falling/any edge, more
| voltages = ?
| threshold = ?
| memory = 40 KB
| compression = none
| website = [http://teledynelecroy.com/logicstudio/ teledynelecroy.com]
}}

The '''LeCroy LogicStudio''' is an USB logic analyzer with 16 channels that offers up to 1GHz samplerate. When all 16 channels are enabled, the maximum samplerate is limited to at most 500MHz. Either the lower eight or the upper eight channels may be disabled for an increased samplerate of up to 1GHz. The device offers a continuous acquisition mode where all inputs are sampled at a frequency of 1kHz. Its internal protocol decoder supports UART, I2C and SPI.

== Hardware ==
* '''FPGA''': Xilinx Spartan-6 XC6SLX16
* '''USB interface''': [http://www.cypress.com/?docID=45142 Cypress CY7C68013A]
* '''Crystal (FX2LP):''' 24.000MHz
* '''Crystal (FPGA):''' Unknown, xpress0?

== Photos ==
<gallery>
File:Lecroy-logicstudio.jpg|LogicStudio
File:Lecroy-logicstudio-pcb.jpg|PCB, front
File:Lecroy-logicstudio-fpga.jpg|FPGA
File:Lecroy-logicstudio-usb.jpg|FX2
</gallery>

== Trigger Capabilities ==

The device has both standard logic triggers as well as triggers that operate on data produced by its internal protocol decoder.
There are two logic trigger blocks A and B which can optionally be combined in the following ways:
* A AND B
* A OR B
* A THEN B

Each logic trigger block offers the following match criteria:
* Rising edge
* Falling edge
* Any edge
* Level 0 (including pulse width)
* Level 1 (ditto)
* Qualified edge triggers (trigger on rising/falling/any edge while another signal is high/low).

Multiple edge triggers in the same block are OR'd, while multiple level triggers in the same block are AND'ed.
Each trigger block can further be configured with a number of times that the trigger criteria need to match before the trigger fires.

== Internals ==

The device initially shows up as VID:PID 0x5ff:0xa001 on the USB bus. It then requires a firmware upload to its FX2LP chip, after which the original USB device disappears and a new one shows up, with VID:PID 0x5ff:0xa002.

The bitstreams for the FPGA come in two versions: one which enables all 16 channels, and one which only enables either the bottom 8 or the top 8 channels. If the first bitstream is uploaded, the maximum allowed sample rate is 500MHz. If the second bitstream is uploaded, the device can sample at up to 1GHz. In the latter case, a separate command controls whether the lower or the upper channels are enabled.

Samples are stored in the device's 40 KB memory. That memory block is used as a ringbuffer; samples are continously written to it (thus overwriting old data if necessary) until the user-programmed trigger fires _and_ the requested number of post-trigger samples have been acquired.
At that point, you may retrieve the ringbuffer's contents from the device.

== Firmware revisions ==

As of October 2015, the latest released LeCroy LogicStudio software ships with FPGA bitstreams that are 464196 bytes and have the following hashes:
* md5(lecroy-logicstudio16-16.bitstream) = 1ab904704def72f18543d9d7aa929002
* md5(lecroy-logicstudio16-8.bitstream) = 5763c67cb762c85c8b1d09dc1f239acb

The FX2LP firmware is 4250 bytes:
* md5(lecroy-logicstudio16-fx2lp.fw) = 1638e2a5ef211c10f48405c1c16a057f

LeCroy LogicStudio

2015-10-28T06:01:20Z

Tilman: /* Trigger Capabilities */ Typo

{{Infobox logic analyzer
| image = [[File:Lecroy-logicstudio.jpg|180px]]
| name = LeCroy LogicStudio
| status =
| source_code_dir =
| channels = 16
| samplerate = up to 1GHz (when sampling 8 channels) ; up to 500MHz (when sampling 16 channels)
| samplerate_state = —
| triggers = high/low state, rising/falling/any edge, more
| voltages = ?
| threshold = ?
| memory = ?
| compression = none
| website = [http://teledynelecroy.com/logicstudio/ teledynelecroy.com]
}}

The '''LeCroy LogicStudio''' is an USB logic analyzer with 16 channels that offers up to 1GHz samplerate. When all 16 channels are enabled, the maximum samplerate is limited to at most 500MHz. Either the lower eight or the upper eight channels may be disabled for an increased samplerate of up to 1GHz. The device offers a continuous acquisition mode where all inputs are sampled at a frequency of 1kHz. Its internal protocol decoder supports UART, I2C and SPI.

== Hardware ==
* '''FPGA''': Xilinx Spartan-6 XC6SLX16
* '''USB interface''': [http://www.cypress.com/?docID=45142 Cypress CY7C68013A]
* '''Crystal (FX2LP):''' 24.000MHz
* '''Crystal (FPGA):''' Unknown, xpress0?

== Photos ==
<gallery>
File:Lecroy-logicstudio.jpg|LogicStudio
File:Lecroy-logicstudio-pcb.jpg|PCB, front
File:Lecroy-logicstudio-fpga.jpg|FPGA
File:Lecroy-logicstudio-usb.jpg|FX2
</gallery>

== Trigger Capabilities ==

The device has both standard logic triggers as well as triggers that operate on data produced by its internal protocol decoder.
There are two logic trigger blocks A and B which can optionally be combined in the following ways:
* A AND B
* A OR B
* A THEN B

Each logic trigger block offers the following match criteria:
* Rising edge
* Falling edge
* Any edge
* Level 0 (including pulse width)
* Level 1 (ditto)
* Qualified edge triggers (trigger on rising/falling/any edge while another signal is high/low).

Multiple edge triggers in the same block are OR'd, while multiple level triggers in the same block are AND'ed.
Each trigger block can further be configured with a number of times that the trigger criteria need to match before the trigger fires.

== Internals ==

The device initially shows up as VID:PID 0x5ff:0xa001 on the USB bus. It then requires a firmware upload to its FX2LP chip, after which the original USB device disappears and a new one shows up, with VID:PID 0x5ff:0xa002.

The bitstreams for the FPGA come in two versions: one which enables all 16 channels, and one which only enables either the bottom 8 or the top 8 channels. If the first bitstream is uploaded, the maximum allowed sample rate is 500MHz. If the second bitstream is uploaded, the device can sample at up to 1GHz. In the latter case, a separate command seems to control whether the lower or the upper channels are enabled.

== Firmware revisions ==

As of October 2015, the latest released LeCroy LogicStudio software ships with FPGA bitstreams that are 464196 bytes and have the following hashes:
* md5(lecroy-logicstudio16-16.bitstream) = 1ab904704def72f18543d9d7aa929002
* md5(lecroy-logicstudio16-8.bitstream) = 5763c67cb762c85c8b1d09dc1f239acb

The FX2LP firmware is 4250 bytes:
* md5(lecroy-logicstudio16-fx2lp.fw) = 1638e2a5ef211c10f48405c1c16a057f

LeCroy LogicStudio

2015-10-28T06:00:38Z

Tilman: Document the hashes of the official firmware

{{Infobox logic analyzer
| image = [[File:Lecroy-logicstudio.jpg|180px]]
| name = LeCroy LogicStudio
| status =
| source_code_dir =
| channels = 16
| samplerate = up to 1GHz (when sampling 8 channels) ; up to 500MHz (when sampling 16 channels)
| samplerate_state = —
| triggers = high/low state, rising/falling/any edge, more
| voltages = ?
| threshold = ?
| memory = ?
| compression = none
| website = [http://teledynelecroy.com/logicstudio/ teledynelecroy.com]
}}

The '''LeCroy LogicStudio''' is an USB logic analyzer with 16 channels that offers up to 1GHz samplerate. When all 16 channels are enabled, the maximum samplerate is limited to at most 500MHz. Either the lower eight or the upper eight channels may be disabled for an increased samplerate of up to 1GHz. The device offers a continuous acquisition mode where all inputs are sampled at a frequency of 1kHz. Its internal protocol decoder supports UART, I2C and SPI.

== Hardware ==
* '''FPGA''': Xilinx Spartan-6 XC6SLX16
* '''USB interface''': [http://www.cypress.com/?docID=45142 Cypress CY7C68013A]
* '''Crystal (FX2LP):''' 24.000MHz
* '''Crystal (FPGA):''' Unknown, xpress0?

== Photos ==
<gallery>
File:Lecroy-logicstudio.jpg|LogicStudio
File:Lecroy-logicstudio-pcb.jpg|PCB, front
File:Lecroy-logicstudio-fpga.jpg|FPGA
File:Lecroy-logicstudio-usb.jpg|FX2
</gallery>

== Trigger Capabilities ==

The device has both standard logic triggers as well as triggers that operate on data produced by its internal protocol decoder.
There are two logic trigger blocks A and B which can optionally be combined in the following ways:
* A AND B
* A OR B
* A THEN B

Each logic trigger block offers the following match criteria:
* Rising edge
* Falling edge
* Any edge
* Level 0 (including pulse width)
* Level 1 (ditto)
* Qualified edge triggers (trigger on rising/falling/any edge while another signal is high/low).

Multiple edge triggers in the same block are OR'd, while multiple level triggers in the same block are AND'ed.
Each trigger block can further be configured with a number of times that the trigger criteria need to match before the trigger fired.

== Internals ==

The device initially shows up as VID:PID 0x5ff:0xa001 on the USB bus. It then requires a firmware upload to its FX2LP chip, after which the original USB device disappears and a new one shows up, with VID:PID 0x5ff:0xa002.

The bitstreams for the FPGA come in two versions: one which enables all 16 channels, and one which only enables either the bottom 8 or the top 8 channels. If the first bitstream is uploaded, the maximum allowed sample rate is 500MHz. If the second bitstream is uploaded, the device can sample at up to 1GHz. In the latter case, a separate command seems to control whether the lower or the upper channels are enabled.

== Firmware revisions ==

As of October 2015, the latest released LeCroy LogicStudio software ships with FPGA bitstreams that are 464196 bytes and have the following hashes:
* md5(lecroy-logicstudio16-16.bitstream) = 1ab904704def72f18543d9d7aa929002
* md5(lecroy-logicstudio16-8.bitstream) = 5763c67cb762c85c8b1d09dc1f239acb

The FX2LP firmware is 4250 bytes:
* md5(lecroy-logicstudio16-fx2lp.fw) = 1638e2a5ef211c10f48405c1c16a057f

LeCroy LogicStudio

2015-10-14T18:47:38Z

Tilman:

{{Infobox logic analyzer
| image = [[File:Lecroy-logicstudio.jpg|180px]]
| name = LeCroy LogicStudio
| status =
| source_code_dir =
| channels = 16
| samplerate = up to 1GHz (when sampling 8 channels) ; up to 500MHz (when sampling 16 channels)
| samplerate_state = —
| triggers = high/low state, rising/falling/any edge, more
| voltages = ?
| threshold = ?
| memory = ?
| compression = none
| website = [http://teledynelecroy.com/logicstudio/ teledynelecroy.com]
}}

The '''LeCroy LogicStudio''' is an USB logic analyzer with 16 channels that offers up to 1GHz samplerate. When all 16 channels are enabled, the maximum samplerate is limited to at most 500MHz. Either the lower eight or the upper eight channels may be disabled for an increased samplerate of up to 1GHz. The device offers a continuous acquisition mode where all inputs are sampled at a frequency of 1kHz. Its internal protocol decoder supports UART, I2C and SPI.

== Hardware ==
* '''FPGA''': Xilinx Spartan-6 XC6SLX16
* '''USB interface''': [http://www.cypress.com/?docID=45142 Cypress CY7C68013A]
* '''Crystal (FX2LP):''' 24.000MHz
* '''Crystal (FPGA):''' Unknown, xpress0?

== Photos ==
<gallery>
File:Lecroy-logicstudio.jpg|LogicStudio
File:Lecroy-logicstudio-pcb.jpg|PCB, front
File:Lecroy-logicstudio-fpga.jpg|FPGA
File:Lecroy-logicstudio-usb.jpg|FX2
</gallery>

== Trigger Capabilities ==

The device has both standard logic triggers as well as triggers that operate on data produced by its internal protocol decoder.
There are two logic trigger blocks A and B which can optionally be combined in the following ways:
* A AND B
* A OR B
* A THEN B

Each logic trigger block offers the following match criteria:
* Rising edge
* Falling edge
* Any edge
* Level 0 (including pulse width)
* Level 1 (ditto)
* Qualified edge triggers (trigger on rising/falling/any edge while another signal is high/low).

Multiple edge triggers in the same block are OR'd, while multiple level triggers in the same block are AND'ed.
Each trigger block can further be configured with a number of times that the trigger criteria need to match before the trigger fired.

== Internals ==

The device initially shows up as VID:PID 0x5ff:0xa001 on the USB bus. It then requires a firmware upload to its FX2LP chip, after which the original USB device disappears and a new one shows up, with VID:PID 0x5ff:0xa002.

The bitstreams for the FPGA come in two versions: one which enables all 16 channels, and one which only enables either the bottom 8 or the top 8 channels. If the first bitstream is uploaded, the maximum allowed sample rate is 500MHz. If the second bitstream is uploaded, the device can sample at up to 1GHz. In the latter case, a separate command seems to control whether the lower or the upper channels are enabled.

LeCroy LogicStudio

2015-10-12T16:44:07Z

Tilman: Add photos of the FPGA and FX2

File:Lecroy-logicstudio-usb.jpg

2015-10-12T16:42:40Z

Tilman: LeCroy LogicStudio USB interface chip

== Summary ==
LeCroy LogicStudio USB interface chip
== Licensing ==
{{PD}}

File:Lecroy-logicstudio-fpga.jpg

2015-10-12T16:42:06Z

Tilman: LeCroy LogicStudio FPGA

== Summary ==
LeCroy LogicStudio FPGA
== Licensing ==
{{PD}}

LeCroy LogicStudio

2015-10-12T16:36:58Z

Tilman: Add photos

File:Lecroy-logicstudio.jpg

2015-10-12T16:33:28Z

Tilman: LeCroy LogicStudio

== Summary ==
LeCroy LogicStudio
== Licensing ==
{{PD}}

File:Lecroy-logicstudio-pcb.jpg

2015-10-12T16:26:17Z

Tilman: Photo of LeCroy LogicStudio PCB.

== Summary ==
Photo of LeCroy LogicStudio PCB.
== Licensing ==
{{PD}}

LeCroy LogicStudio

2015-10-12T16:19:42Z

Tilman: New article on LeCroy LogicStudio

{{Infobox logic analyzer
| image =
| name = LeCroy LogicStudio
| status =
| source_code_dir =
| channels = 16
| samplerate = up to 1GHz (when sampling 8 channels) ; up to 500MHz (when sampling 16 channels)
| samplerate_state = —
| triggers = high/low state, rising/falling/any edge, more
| voltages = ?
| threshold = ?
| memory = ?
| compression = none
| website = [http://teledynelecroy.com/logicstudio/ teledynelecroy.com]
}}

The '''LeCroy LogicStudio''' is an USB logic analyzer with 16 channels that offers up to 1GHz samplerate. When all 16 channels are enabled, the maximum samplerate is limited to at most 500MHz. Either the lower eight or the upper eight channels may be disabled for an increased samplerate of up to 1GHz. The device offers a continuous acquisition mode where all inputs are sampled at a frequency of 1kHz.

== Hardware ==
* '''FPGA''': Xilinx Spartan-6 XC6SLX16
* '''USB interface''': [http://www.cypress.com/?docID=45142 Cypress CY7C68013A]
* '''Crystal (FX2):''' 24.000MHz
* '''Crystal (FPGA):''' Unknown, xpress0?