sigrok - User contributions [en]

DreamSourceLab DSLogic Plus

2023-03-30T05:25:39Z

Reversebias: Including hardware information about a new V421 variant.

{{Infobox logic analyzer
| image = [[File:DSLogic.png|180px]]
| name = DreamSourceLab DSLogic Plus
| status = supported
| source_code_dir = dreamsourcelab-dslogic
| channels = 1-16
| samplerate = 400MHz(4ch), 200MHz(8ch), 100MHz(16ch)
| samplerate_state = 30MHz (?) or 50MHz (?)
| triggers = high, low, rising, falling, edge, multi-stage triggers
| voltages = -0.6V — 6V, +-30V with provided probe-wires
| threshold = configurable: 0-5V (0.1V increments)
| memory = 256MBit
| compression = yes
| website = [http://www.dreamsourcelab.com/dslogic.html dreamsourcelab.com]
}}

The '''DreamSourceLab DSLogic Plus''' is a 16-channel USB-based logic analyzer, with sampling rates up to 400MHz (when using only 4 channels). This differs slightly from the original DSLogic product in its configurable threshold voltage and different PCB layout. DreamSourceLab doesn't make the distinction between these two products very clear on their website.

See [[DreamSourceLab DSLogic Plus/Info]] for more details (such as '''lsusb -v''' output) about the device.

== Hardware ==

* [http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/ Xilinx XC6SLX9] U3: Spartan-6 FPGA (TQG144BIV13337)
* Sample memory:
** Original version: [https://www.alliancememory.com/wp-content/uploads/pdf/dram/256Mb-AS4C16M16SA-C&I_V3.0_March%202015.pdf Alliance AS4C16M16SA-7TCN] U1: 256Mbit SDRAM
** V211: [https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/256Mb_sdr.pdf Micron MT48LC16M16A2 256Mbit SDRAM]
* [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A] U2: FX2LP USB interface chip
* [http://www.st.com/content/ccc/resource/technical/document/datasheet/59/05/c9/5b/7b/41/48/b6/CD00259167.pdf/files/CD00259167.pdf/jcr:content/translations/en.CD00259167.pdf 128Kbit I²C EEPROM] U4: ST M24128-BR
* [http://www.ti.com/product/TPS62400 TI TPS62400] U10: Dual, Adjustable, 400mA and 600mA, 2.25MHz Step-Down Converter (3.3V and 1.2V output)
* [http://file1.jzsc8.com/mallpropdf/16/04/28/151237988.pdf 24.0Mhz Crystal] Y1: [http://www.yxc.hk/u_file/product/17_08_22/YSX321SL.pdf YSX321SL series] 20ppm (markings: YXC 24.0SBJI)

== Hardware (V421/Pango Variant) ==

New hardware variant received early 2023, enumerates as 2a0e:0030, and uses a different vendor's FPGA. Currently incompatible with sigrok.

* [https://www-pangomicro-com.translate.goog/procenter/detail4.html?_x_tr_sl=auto&_x_tr_tl=en&_x_tr_hl=en&_x_tr_pto=wapp PangoMicro Logos PGL12G] U13: PGL12G, 12k LUT, LPG144 package
* [https://www.winbond.com/resource-files/w9825g6kh_a04.pdf Winbond W9825G6KH-6] U6: 256Mbit SDRAM
* [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A] U2: FX2LP USB interface chip
* [http://www.st.com/content/ccc/resource/technical/document/datasheet/59/05/c9/5b/7b/41/48/b6/CD00259167.pdf/files/CD00259167.pdf/jcr:content/translations/en.CD00259167.pdf 128Kbit I²C EEPROM] U4: ST M24128-BR
* Unmarked 3.3V and 1.2V regulators
* [http://file1.jzsc8.com/mallpropdf/16/04/28/151237988.pdf 24.0Mhz Crystal] Y1: [http://www.yxc.hk/u_file/product/17_08_22/YSX321SL.pdf YSX321SL series] 20ppm (markings: YXC 24.0SBJI)

== Photos ==

'''Device''':
<gallery>
File:Dslogic_plus_pcb_front.jpg|PCB, front
File:Dslogic_plus_pcb_back.jpg|PCB, back (mirrored)
File:Dslogic_plus_V211_pcb_front.jpeg|PCB V211, front
File:Dslogic_plus_V211_pcb_back.jpeg|PCB V211, back
File:Dslogic plus V421 pcb front.jpg|PCB V421, front
File:Dslogic plus V421 pcb rear.jpg|PCB V421, back

</gallery>

'''Cables''':
<gallery>
File:Dreamsourcelab dslogic plus cable 1.jpg
File:Dreamsourcelab dslogic plus cable 2.jpg
File:Dreamsourcelab dslogic plus cable 3.jpg
File:Dreamsourcelab dslogic plus cable 4.jpg
File:Dreamsourcelab dslogic plus cable 5.jpg
File:Dreamsourcelab dslogic plus probe circuit.png|Probe cable circuit
File:Dreamsourcelab dslogic plus cable B xray 1.jpg|Revised Probe cable
File:Dreamsourcelab dslogic plus cable B xray 2.jpg|Revised Probe cable
</gallery>

== Firmware ==

See [[DreamSourceLab DSLogic#Firmware]].

== Resources ==

* [http://www.dreamsourcelab.com Vendor website]
* [https://www.dreamsourcelab.com/doc/DSLogic_Plus_Datasheet.pdf Vendor datasheet]
* [https://www.kickstarter.com/projects/dreamsourcelab/dslogic-multifunction-instruments-for-everyone Kickstarter page]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Supported]]

DreamSourceLab DSLogic Plus/Info

2023-03-30T05:22:20Z

Reversebias: Update to include lsusb dump of new variant

== lsusb ==


$ '''lsusb -v'''
Bus 001 Device 011: ID '''2a0e:0020'''
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 255 Vendor Specific Class
bDeviceSubClass 255 Vendor Specific Subclass
bDeviceProtocol 255 Vendor Specific Protocol
bMaxPacketSize0 64
idVendor 0x2a0e
idProduct 0x0020
bcdDevice 0.01
iManufacturer 1 '''DreamSourceLab'''
iProduct 2 '''USB-based DSL Instrument v2'''
iSerial 0
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 32
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0x80
(Bus Powered)
MaxPower 100mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 255 Vendor Specific Class
bInterfaceSubClass 255 Vendor Specific Subclass
bInterfaceProtocol 255 Vendor Specific Protocol
iInterface 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 EP 2 OUT
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x86 EP 6 IN
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Device Qualifier (for other device speed):
bLength 10
bDescriptorType 6
bcdUSB 2.00
bDeviceClass 255 Vendor Specific Class
bDeviceSubClass 255 Vendor Specific Subclass
bDeviceProtocol 255 Vendor Specific Protocol
bMaxPacketSize0 64
bNumConfigurations 1
Device Status: 0x0000
(Bus Powered)


== lsusb (V421 variant) ==


$ '''lsusb -v'''
Bus 001 Device 010: ID 2a0e:0030 Shenzhen DreamSource Technology Co., Ltd. USB-based DSL
Instrument v2
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 255 Vendor Specific Class
bDeviceSubClass 255 Vendor Specific Subclass
bDeviceProtocol 255 Vendor Specific Protocol
bMaxPacketSize0 64
idVendor 0x2a0e Shenzhen DreamSource Technology Co., Ltd.
idProduct 0x0030
bcdDevice 0.01
iManufacturer 1 DreamSourceLab
iProduct 2 USB-based DSL Instrument v2
iSerial 0
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 0x0020
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0x80
(Bus Powered)
MaxPower 100mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 255 Vendor Specific Class
bInterfaceSubClass 255 Vendor Specific Subclass
bInterfaceProtocol 255 Vendor Specific Protocol
iInterface 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 EP 2 OUT
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x86 EP 6 IN
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Device Qualifier (for other device speed):
bLength 10
bDescriptorType 6
bcdUSB 2.00
bDeviceClass 255 Vendor Specific Class
bDeviceSubClass 255 Vendor Specific Subclass
bDeviceProtocol 255 Vendor Specific Protocol
bMaxPacketSize0 64
bNumConfigurations 1
Device Status: 0x0000
(Bus Powered)

DreamSourceLab DSLogic Plus

2023-03-30T05:02:58Z

Reversebias: /* Photos */

{{Infobox logic analyzer
| image = [[File:DSLogic.png|180px]]
| name = DreamSourceLab DSLogic Plus
| status = supported
| source_code_dir = dreamsourcelab-dslogic
| channels = 1-16
| samplerate = 400MHz(4ch), 200MHz(8ch), 100MHz(16ch)
| samplerate_state = 30MHz (?) or 50MHz (?)
| triggers = high, low, rising, falling, edge, multi-stage triggers
| voltages = -0.6V — 6V, +-30V with provided probe-wires
| threshold = configurable: 0-5V (0.1V increments)
| memory = 256MBit
| compression = yes
| website = [http://www.dreamsourcelab.com/dslogic.html dreamsourcelab.com]
}}

The '''DreamSourceLab DSLogic Plus''' is a 16-channel USB-based logic analyzer, with sampling rates up to 400MHz (when using only 4 channels). This differs slightly from the original DSLogic product in its configurable threshold voltage and different PCB layout. DreamSourceLab doesn't make the distinction between these two products very clear on their website.

See [[DreamSourceLab DSLogic Plus/Info]] for more details (such as '''lsusb -v''' output) about the device.

== Hardware ==

* [http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/ Xilinx XC6SLX9] U3: Spartan-6 FPGA (TQG144BIV13337)
* Sample memory:
** Original version: [https://www.alliancememory.com/wp-content/uploads/pdf/dram/256Mb-AS4C16M16SA-C&I_V3.0_March%202015.pdf Alliance AS4C16M16SA-7TCN] U1: 256Mbit SDRAM
** V211: [https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/256Mb_sdr.pdf Micron MT48LC16M16A2 256Mbit SDRAM]
* [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A] U2: FX2LP USB interface chip
* [http://www.st.com/content/ccc/resource/technical/document/datasheet/59/05/c9/5b/7b/41/48/b6/CD00259167.pdf/files/CD00259167.pdf/jcr:content/translations/en.CD00259167.pdf 128Kbit I²C EEPROM] U4: ST M24128-BR
* [http://www.ti.com/product/TPS62400 TI TPS62400] U10: Dual, Adjustable, 400mA and 600mA, 2.25MHz Step-Down Converter (3.3V and 1.2V output)
* [http://file1.jzsc8.com/mallpropdf/16/04/28/151237988.pdf 24.0Mhz Crystal] Y1: [http://www.yxc.hk/u_file/product/17_08_22/YSX321SL.pdf YSX321SL series] 20ppm (markings: YXC 24.0SBJI)

== Photos ==

'''Device''':
<gallery>
File:Dslogic_plus_pcb_front.jpg|PCB, front
File:Dslogic_plus_pcb_back.jpg|PCB, back (mirrored)
File:Dslogic_plus_V211_pcb_front.jpeg|PCB V211, front
File:Dslogic_plus_V211_pcb_back.jpeg|PCB V211, back
File:Dslogic plus V421 pcb front.jpg|PCB V421, front
File:Dslogic plus V421 pcb rear.jpg|PCB V421, back

</gallery>

'''Cables''':
<gallery>
File:Dreamsourcelab dslogic plus cable 1.jpg
File:Dreamsourcelab dslogic plus cable 2.jpg
File:Dreamsourcelab dslogic plus cable 3.jpg
File:Dreamsourcelab dslogic plus cable 4.jpg
File:Dreamsourcelab dslogic plus cable 5.jpg
File:Dreamsourcelab dslogic plus probe circuit.png|Probe cable circuit
File:Dreamsourcelab dslogic plus cable B xray 1.jpg|Revised Probe cable
File:Dreamsourcelab dslogic plus cable B xray 2.jpg|Revised Probe cable
</gallery>

== Firmware ==

See [[DreamSourceLab DSLogic#Firmware]].

== Resources ==

* [http://www.dreamsourcelab.com Vendor website]
* [https://www.dreamsourcelab.com/doc/DSLogic_Plus_Datasheet.pdf Vendor datasheet]
* [https://www.kickstarter.com/projects/dreamsourcelab/dslogic-multifunction-instruments-for-everyone Kickstarter page]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Supported]]

File:Dslogic plus V421 pcb rear.jpg

2023-03-30T05:01:39Z

Reversebias: PCB Marking DSLU2P-V421-P0217 Purchased 2023-03-15 from dreamsourcelabs.com

== Summary ==
PCB Marking DSLU2P-V421-P0217 Purchased 2023-03-15 from dreamsourcelabs.com
== Licensing ==
{{PD}}

File:Dslogic plus V421 pcb front.jpg

2023-03-30T05:00:25Z

Reversebias: PCB Marking DSLU2P-V421-P0217 Purchased 2023-03-15 from dreamsourcelabs.com

== Summary ==
PCB Marking DSLU2P-V421-P0217 Purchased 2023-03-15 from dreamsourcelabs.com
== Licensing ==
{{PD}}