https://sigrok.org/w/api.php?action=feedcontributions&feedformat=atom&user=Planet9sigrok - User contributions [en]2026-04-10T13:04:13ZUser contributionsMediaWiki 1.37.1https://sigrok.org/w/index.php?title=Kingst_LA2016&diff=16227Kingst LA20162021-11-19T11:22:12Z<p>Planet9: Add link to open fx2 firmware to encourage testing</p>
<hr />
<div>{{Infobox logic analyzer<br />
| image = [[File:Kingst la2016 mugshot.png|180px]]<br />
| name = Kingst LA2016<br />
| status = supported<br />
| source_code_dir = kingst-la2016<br />
| channels = 16<br />
| samplerate = 200MHz max.<br />
| samplerate_state = State analysis not supported<br />
| triggers = Level (multiple channels)<br/>Edge (one channel)<br />
| voltages = -50V &mdash; 50V<br />
| threshold = Configurable:<br/>-4V&mdash;4V, min step 0.01V<br />
| memory = 128MByte DDR2 SDRAM<br/>40M&mdash;10G samples<br />
| compression = Yes<br />
| website = [http://www.qdkingst.com/en qdkingst.com]<br />
}}<br />
<br />
The '''Kingst LA2016''' is a USB-based, 16-channel logic analyser with 200MHz maximum sampling rate and 128MB sample memory.<br />
The current vendor is "Qingdao Kingst Electronics Co., Ltd." but older models are branded "Jiankun" rather than "Kingst".<br />
Detailed specifications and the vendor software are available on the [http://www.qdkingst.com/en/products Kingst website].<br />
<br />
<br />
* '''Support Status:'''<br />
:03-OCT-2021 The Kingst LA2016 and LA1016 are now supported in the PulseView nightly build for Linux and Windows. The macOS build is not yet tested AFAIK.<br />
:19-NOV-2021 [https://github.com/sigrokproject/sigrok-firmware/pull/1 Open firmware] for the FX2 MCU is available for testing.<br />
* '''Known Issues:'''<br />
#PulseView allows the user to setup multiple edge triggers, but the analyser only supports one. Please only use one edge trigger to avoid undefined behaviour. Note the edge trigger can be combined with any number of level triggers.<br />
#The analyser input threshold can be adjusted in PulseView using a slider control, but there is no gui feedback to confirm the threshold voltage. Workaround for now is to view the log file for confirmation of the set trigger level. The analyser is always initialised to 1.6V input threshold on startup.<br />
#Unplugging the analyser and then attempting to start a capture causes PulseView to crash.<br />
#When using the LA1016, the maximum sampling rate is 100MHz but the driver name is still displayed as LA2016.<br />
<br />
<br />
== Hardware ==<br />
<br />
This logic analyser has been on the market since around 2012 and there are a few different revisions of it.<br />
The [[Media:Kingst_LA2016_LA1016_Schematic.zip|schematic]] has been reverse engineered from<br />
a unit purchased in 2020 containing a PCB marked as v1.3.0. <br />
The circuitry of older PCBs is similar but may have different voltage regulators, different input<br />
channel routing to the FPGA, and lack the input threshold adjustment.<br />
<br />
The LA1016 uses identical hardware with a different FPGA bitstream which limits the sample rate to 100MHz maximum.<br />
<br />
All of these devices use the same firmware for the FX2LP MCU but there are four different FPGA bitstreams;<br />
i.e. LA1016 & LA2016 bitstreams and the older versions of these (to swap some of the input channels as required by PCB routing changes).<br />
Once the FX2LP firmware has been loaded, a 'magic number' is read from EEPROM which identifies the<br />
device and thus allows the correct FPGA bitstream to be loaded.<br />
<br />
Note that the LA1016 cannot be boosted to 200MHz by changing the 'magic number' or the FPGA bitstream.<br />
When the FPGA initialises, its reads 16 bytes from U10 which are used to authenticate the bitstream; these bytes are different for 100 and 200MHz devices.<br />
Furthermore, the OEM software performs a challenge-response with U10 to authenticate the logic analyser as genuine 'Kingst'.<br />
The good news is that U10 does not impact sigrok support in any way and we don't need to communicate with it.<br />
<br />
<br />
Main components and their function:<br />
<br />
* '''MCU''' Cypress FX2LP<br />
:This MCU only has volatile memory and in this implementation it's firmware is loaded from the host by the application software.<br />
:Either the OEM firmware or open source firmware can be used.<br />
:In essence, it just performs data moving operations:<br />
#Endpoint 0 to EEPROM read/write<br />
#Endpoint 0 to SPI read/write for FPGA control registers<br />
#Endpoint 2 bulk out to SPI for loading FPGA bitstream<br />
#Endpoint 6 bulk in to read capture data from FPGA/SDRAM<br />
<br />
* '''EEPROM''' Atmel AT24C02 2Kbit<br />
:This non-volatile memory stores:<br />
#VID:PID which is 77a1:01a2 for LA1016 and LA2016 devices<br />
#'magic number' to identify model and revision<br />
#purchase date (presumably for warranty claims)<br />
#other information related to U10 but not of interest to sigrok<br />
<br />
* '''FPGA''' Altera EP4CE6<br />
:Currently requires the OEM bitstream.<br />
:Has a bank of approximately 60 byte-wide registers accessed via SPI which are used to contol FPGA functions.<br />
:Captures 16 input channels, performs compression (run length encoding, 16bit sample plus 8 bit repetition count).<br />
:Stores samples to SDRAM (or streams direct to USB but we don't implement that method).<br />
:Interestingly, this device (6K LE) shares the same die as the next up device EP4CE10 (10K LE) and can be programmed as such. However, functionality would not be guaranteed as CE6 devices may be CE10 rejects.<br />
:If open source FPGA code were to become available there would be capacity to experiment with more advanced triggers, such as pattern trigger for SPI or I2C.<br />
<br />
* '''SDRAM''' Samsung DDR2<br />
:Samples are stored as 3 bytes (16bit sample plus 8 bit repetition count).<br />
:A 'transfer packet' for upload is 16 bytes = 5 compressed samples plus a sequence number byte.<br />
:Burst read/write for this SDRAM is up to 16 bytes, which matches the transfer packet size and is likely used for all SDRAM read/writes.<br />
<br />
* '''U10''' Kingst Authentication Device<br />
:Not used by sigrok.<br />
#Provides fixed bytes identifier to FPGA for bitstream validation (either LA1016 100MHz or LA2016 200MHz bitstream)<br />
#Provides challenge-response rolling-code for OEM software to authenticate the device as genuine 'Kingst'<br />
<br />
<br />
Datasheets:<br />
<br />
:U1 [https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv.html EP4CE6F17C8N] Cyclone IV E FPGA<br />
:U2,4,5,7 [http://sxsemi.com/upfile/PDWL050019-SOT236.pdf PDWL050019] TVS Diode Array<br />
:U3 [https://www.cypress.com/part/cy7c68013a-100axc CY7C68013A-100AXC] EZUSB MCU<br />
:U6,U8 [http://www.sg-micro.com/show-product-510.html SGM2019] Linear Regulator<br />
:U9 [https://www.microchip.com/wwwproducts/en/AT24C02C AT24C02] EEPROM 2kbit<br />
:U10 (device not identified, small MCU of some type)<br />
:U11 K4T1G164QG-BCF8, DDR2 SDRAM, obsolete<br />
:U12,U13 [http://www.sg-micro.com/show-product-519.html SGM6013] Switch-mode Regulator<br />
:U14 [http://www.sg-micro.com/show-product-203.html SGM8272] Dual Op-amp<br />
:U15 [http://www.ti.com/lit/ds/symlink/tps60403.pdf TPS60403] Charge Pump Voltage Inverter<br />
<br />
<br />
== Photos ==<br />
<br />
<gallery><br />
File:Kingst la2016 package contents.jpg|<small>Package contents</small><br />
File:Kingst la2016 paper.jpg|<small>Paper</small><br />
File:Kingst la2016 device top.jpg|<small>Device, top</small><br />
File:Kingst la2016 device bottom.jpg|<small>Device, bottom</small><br />
File:Kingst la2016 pcb top.jpg|<small>PCB, top</small><br />
File:Kingst la2016 pcb bottom.jpg|<small>PCB, bottom</small><br />
File:Kingst la2016 cypress fx2.jpg|<small>Cypress FX2</small><br />
File:Kingst la2016 altera cyclone4 ep4ce6f17c8n.jpg|<small>Altera Cyclone IV</small><br />
File:Kingst la2016 samsung k4t1g164qg.jpg|<small>Samsung K4T1G164QG</small><br />
File:Kingst la2016 atmel 24c02n.jpg|<small>Atmel 24C02N</small><br />
File:Kingst la2016 unmarked ic.jpg|<small>Unmarked IC</small><br />
File:Kingst la2016 fpni.jpg|<small>PFNI</small><br />
</gallery><br />
<br />
== Firmware ==<br />
<br />
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/kingst-la sigrok-fwextract-kingst-la2016] script from the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree sigrok-util] repo and place them in one of the usual [[Firmware#Where_to_put_the_firmware_files|places where libsigrok expects firmware files]]:<br />
<br />
<small><br />
$ '''./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS'''<br />
saved 5430 bytes to kingst-la-01a2.fw (crc32=720551a9)<br />
saved 178362 bytes to kingst-la2016a1-fpga.bitstream (crc32=7cc894fa)<br />
saved 178542 bytes to kingst-la2016-fpga.bitstream (crc32=20694ff1)<br />
saved 178379 bytes to kingst-la1016a1-fpga.bitstream (crc32=166866be)<br />
saved 178151 bytes to kingst-la1016-fpga.bitstream (crc32=7db70001)<br />
</small><br />
<br />
== Resources ==<br />
<br />
* [http://www.qdkingst.com/en/download Vendor software]<br />
* [http://www.qdkingst.com/download/vis_ug_en User guide]<br />
* [[Media:Kingst_LA2016_LA1016_Schematic.zip|Reverse engineered schematic]]<br />
* More technical details (such as '''lsusb -v''' output) are available here: [[Kingst LA2016/Info]]<br />
<br />
[[Category:Device]]<br />
[[Category:Logic analyzer]]<br />
[[Category:Supported]]</div>Planet9https://sigrok.org/w/index.php?title=Kingst_LA2016&diff=16207Kingst LA20162021-10-03T10:19:04Z<p>Planet9: </p>
<hr />
<div>{{Infobox logic analyzer<br />
| image = [[File:Kingst la2016 mugshot.png|180px]]<br />
| name = Kingst LA2016<br />
| status = supported<br />
| source_code_dir = kingst-la2016<br />
| channels = 16<br />
| samplerate = 200MHz max.<br />
| samplerate_state = State analysis not supported<br />
| triggers = Level (multiple channels)<br/>Edge (one channel)<br />
| voltages = -50V &mdash; 50V<br />
| threshold = Configurable:<br/>-4V&mdash;4V, min step 0.01V<br />
| memory = 128MByte DDR2 SDRAM<br/>40M&mdash;10G samples<br />
| compression = Yes<br />
| website = [http://www.qdkingst.com/en qdkingst.com]<br />
}}<br />
<br />
The '''Kingst LA2016''' is a USB-based, 16-channel logic analyser with 200MHz maximum sampling rate and 128MB sample memory.<br />
The current vendor is "Qingdao Kingst Electronics Co., Ltd." but older models are branded "Jiankun" rather than "Kingst".<br />
Detailed specifications and the vendor software are available on the [http://www.qdkingst.com/en/products Kingst website].<br />
<br />
<br />
* '''Support Status:'''<br />
:03-OCT-2021 The Kingst LA2016 and LA1016 are now supported in the PulseView nightly build for Linux and Windows. The macOS build is not yet tested AFAIK.<br />
<br />
* '''Known Issues:'''<br />
#PulseView allows the user to setup multiple edge triggers, but the analyser only supports one. Please only use one edge trigger to avoid undefined behaviour. Note the edge trigger can be combined with any number of level triggers.<br />
#The analyser input threshold can be adjusted in PulseView using a slider control, but there is no gui feedback to confirm the threshold voltage. Workaround for now is to view the log file for confirmation of the set trigger level. The analyser is always initialised to 1.6V input threshold on startup.<br />
#Unplugging the analyser and then attempting to start a capture causes PulseView to crash.<br />
#When using the LA1016, the maximum sampling rate is 100MHz but the driver name is still displayed as LA2016.<br />
<br />
<br />
== Hardware ==<br />
<br />
This logic analyser has been on the market since around 2012 and there are a few different revisions of it.<br />
The [[Media:Kingst_LA2016_LA1016_Schematic.zip|schematic]] has been reverse engineered from<br />
a unit purchased in 2020 containing a PCB marked as v1.3.0. <br />
The circuitry of older PCBs is similar but may have different voltage regulators, different input<br />
channel routing to the FPGA, and lack the input threshold adjustment.<br />
<br />
The LA1016 uses identical hardware with a different FPGA bitstream which limits the sample rate to 100MHz maximum.<br />
<br />
All of these devices use the same firmware for the FX2LP MCU but there are four different FPGA bitstreams;<br />
i.e. LA1016 & LA2016 bitstreams and the older versions of these (to swap some of the input channels as required by PCB routing changes).<br />
Once the FX2LP firmware has been loaded, a 'magic number' is read from EEPROM which identifies the<br />
device and thus allows the correct FPGA bitstream to be loaded.<br />
<br />
Note that the LA1016 cannot be boosted to 200MHz by changing the 'magic number' or the FPGA bitstream.<br />
When the FPGA initialises, its reads 16 bytes from U10 which are used to authenticate the bitstream; these bytes are different for 100 and 200MHz devices.<br />
Furthermore, the OEM software performs a challenge-response with U10 to authenticate the logic analyser as genuine 'Kingst'.<br />
The good news is that U10 does not impact sigrok support in any way and we don't need to communicate with it.<br />
<br />
<br />
Main components and their function:<br />
<br />
* '''MCU''' Cypress FX2LP<br />
:This MCU only has volatile memory and in this implementation it's firmware is loaded from the host by the application software.<br />
:Either the OEM firmware or open source firmware can be used.<br />
:In essence, it just performs data moving operations:<br />
#Endpoint 0 to EEPROM read/write<br />
#Endpoint 0 to SPI read/write for FPGA control registers<br />
#Endpoint 2 bulk out to SPI for loading FPGA bitstream<br />
#Endpoint 6 bulk in to read capture data from FPGA/SDRAM<br />
<br />
* '''EEPROM''' Atmel AT24C02 2Kbit<br />
:This non-volatile memory stores:<br />
#VID:PID which is 77a1:01a2 for LA1016 and LA2016 devices<br />
#'magic number' to identify model and revision<br />
#purchase date (presumably for warranty claims)<br />
#other information related to U10 but not of interest to sigrok<br />
<br />
* '''FPGA''' Altera EP4CE6<br />
:Currently requires the OEM bitstream.<br />
:Has a bank of approximately 60 byte-wide registers accessed via SPI which are used to contol FPGA functions.<br />
:Captures 16 input channels, performs compression (run length encoding, 16bit sample plus 8 bit repetition count).<br />
:Stores samples to SDRAM (or streams direct to USB but we don't implement that method).<br />
:Interestingly, this device (6K LE) shares the same die as the next up device EP4CE10 (10K LE) and can be programmed as such. However, functionality would not be guaranteed as CE6 devices may be CE10 rejects.<br />
:If open source FPGA code were to become available there would be capacity to experiment with more advanced triggers, such as pattern trigger for SPI or I2C.<br />
<br />
* '''SDRAM''' Samsung DDR2<br />
:Samples are stored as 3 bytes (16bit sample plus 8 bit repetition count).<br />
:A 'transfer packet' for upload is 16 bytes = 5 compressed samples plus a sequence number byte.<br />
:Burst read/write for this SDRAM is up to 16 bytes, which matches the transfer packet size and is likely used for all SDRAM read/writes.<br />
<br />
* '''U10''' Kingst Authentication Device<br />
:Not used by sigrok.<br />
#Provides fixed bytes identifier to FPGA for bitstream validation (either LA1016 100MHz or LA2016 200MHz bitstream)<br />
#Provides challenge-response rolling-code for OEM software to authenticate the device as genuine 'Kingst'<br />
<br />
<br />
Datasheets:<br />
<br />
:U1 [https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv.html EP4CE6F17C8N] Cyclone IV E FPGA<br />
:U2,4,5,7 [http://sxsemi.com/upfile/PDWL050019-SOT236.pdf PDWL050019] TVS Diode Array<br />
:U3 [https://www.cypress.com/part/cy7c68013a-100axc CY7C68013A-100AXC] EZUSB MCU<br />
:U6,U8 [http://www.sg-micro.com/show-product-510.html SGM2019] Linear Regulator<br />
:U9 [https://www.microchip.com/wwwproducts/en/AT24C02C AT24C02] EEPROM 2kbit<br />
:U10 (device not identified, small MCU of some type)<br />
:U11 K4T1G164QG-BCF8, DDR2 SDRAM, obsolete<br />
:U12,U13 [http://www.sg-micro.com/show-product-519.html SGM6013] Switch-mode Regulator<br />
:U14 [http://www.sg-micro.com/show-product-203.html SGM8272] Dual Op-amp<br />
:U15 [http://www.ti.com/lit/ds/symlink/tps60403.pdf TPS60403] Charge Pump Voltage Inverter<br />
<br />
<br />
== Photos ==<br />
<br />
<gallery><br />
File:Kingst la2016 package contents.jpg|<small>Package contents</small><br />
File:Kingst la2016 paper.jpg|<small>Paper</small><br />
File:Kingst la2016 device top.jpg|<small>Device, top</small><br />
File:Kingst la2016 device bottom.jpg|<small>Device, bottom</small><br />
File:Kingst la2016 pcb top.jpg|<small>PCB, top</small><br />
File:Kingst la2016 pcb bottom.jpg|<small>PCB, bottom</small><br />
File:Kingst la2016 cypress fx2.jpg|<small>Cypress FX2</small><br />
File:Kingst la2016 altera cyclone4 ep4ce6f17c8n.jpg|<small>Altera Cyclone IV</small><br />
File:Kingst la2016 samsung k4t1g164qg.jpg|<small>Samsung K4T1G164QG</small><br />
File:Kingst la2016 atmel 24c02n.jpg|<small>Atmel 24C02N</small><br />
File:Kingst la2016 unmarked ic.jpg|<small>Unmarked IC</small><br />
File:Kingst la2016 fpni.jpg|<small>PFNI</small><br />
</gallery><br />
<br />
== Firmware ==<br />
<br />
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/kingst-la sigrok-fwextract-kingst-la2016] script from the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree sigrok-util] repo and place them in one of the usual [[Firmware#Where_to_put_the_firmware_files|places where libsigrok expects firmware files]]:<br />
<br />
<small><br />
$ '''./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS'''<br />
saved 5430 bytes to kingst-la-01a2.fw (crc32=720551a9)<br />
saved 178362 bytes to kingst-la2016a1-fpga.bitstream (crc32=7cc894fa)<br />
saved 178542 bytes to kingst-la2016-fpga.bitstream (crc32=20694ff1)<br />
saved 178379 bytes to kingst-la1016a1-fpga.bitstream (crc32=166866be)<br />
saved 178151 bytes to kingst-la1016-fpga.bitstream (crc32=7db70001)<br />
</small><br />
<br />
== Resources ==<br />
<br />
* [http://www.qdkingst.com/en/download Vendor software]<br />
* [http://www.qdkingst.com/download/vis_ug_en User guide]<br />
* [[Media:Kingst_LA2016_LA1016_Schematic.zip|Reverse engineered schematic]]<br />
* More technical details (such as '''lsusb -v''' output) are available here: [[Kingst LA2016/Info]]<br />
<br />
[[Category:Device]]<br />
[[Category:Logic analyzer]]<br />
[[Category:Supported]]</div>Planet9https://sigrok.org/w/index.php?title=Kingst_LA2016&diff=16201Kingst LA20162021-09-12T15:17:15Z<p>Planet9: </p>
<hr />
<div>{{Infobox logic analyzer<br />
| image = [[File:Kingst la2016 mugshot.png|180px]]<br />
| name = Kingst LA2016<br />
| status = supported<br />
| source_code_dir = kingst-la2016<br />
| channels = 16<br />
| samplerate = 200MHz max.<br />
| samplerate_state = State analysis not supported<br />
| triggers = Level (multiple channels)<br/>Edge (one channel)<br />
| voltages = -50V &mdash; 50V<br />
| threshold = Configurable:<br/>-4V&mdash;4V, min step 0.01V<br />
| memory = 128MByte DDR2 SDRAM<br/>40M&mdash;10G samples<br />
| compression = Yes<br />
| website = [http://www.qdkingst.com/en qdkingst.com]<br />
}}<br />
<br />
The '''Kingst LA2016''' is a USB-based, 16-channel logic analyser with 200MHz maximum sampling rate.<br />
The current vendor is "Qingdao Kingst Electronics Co., Ltd." but older models are branded "Jiankun" rather than "Kingst".<br />
The vendor software can be freely downloaded from their [http://www.qdkingst.com/en/products website].<br />
<br />
See [[Kingst LA2016/Info]] for more details (such as '''lsusb -v''' output) about the device.<br />
<br />
2021-09-12 status: The Kingst LA2016 and LA1016 are now supported in the PulseView nightly build for Linux.<br />
The macOS build is not yet tested AFAIK. There is a USB issue on the Windows build, so it's not useable at present but is being investigated. More info here:<br />
* [https://github.com/sigrokproject/libsigrok/pull/131 Driver changes]<br />
<br />
<br />
== Hardware ==<br />
<br />
This logic analyser has been on the market since around 2012 and there are a few different revisions of it.<br />
The [[Media:Kingst_LA2016_LA1016_Schematic.zip|schematic]] has been reverse engineered from<br />
a unit purchased in 2020 containing a PCB marked as v1.3.0. <br />
The circuitry of older PCBs is similar but may have different voltage regulators, different input<br />
channel routing to the FPGA, and lack the input threshold adjustment.<br />
<br />
The LA1016 uses identical hardware with a different FPGA bitstream which limits the sample rate to 100MHz maximum.<br />
<br />
All of these devices use the same firmware for the FX2LP MCU but there are four different FPGA bitstreams;<br />
i.e. LA1016 & LA2016 bitstreams and the older versions of these (to swap some of the input channels as required by PCB routing changes).<br />
Once the FX2LP firmware has been loaded, a 'magic number' is read from EEPROM which identifies the<br />
device and thus allows the correct FPGA bitstream to be loaded.<br />
<br />
Note that the LA1016 cannot be boosted to 200MHz by changing the 'magic number' or the FPGA bitstream.<br />
When the FPGA initialises, its reads 16 bytes from U10 which are used to authenticate the bitstream; these bytes are different for 100 and 200MHz devices.<br />
Furthermore, the OEM software performs a challenge-response with U10 to authenticate the logic analyser as genuine 'Kingst'.<br />
The good news is that U10 does not impact sigrok support in any way and we don't need to communicate with it.<br />
<br />
<br />
Main components and their function:<br />
<br />
* '''MCU''' Cypress FX2LP<br />
:This MCU only has volatile memory and in this implementation it's firmware is loaded from the host by the application software.<br />
:Either the OEM firmware or open source firmware can be used.<br />
:In essence, it just performs data moving operations:<br />
#Endpoint 0 to EEPROM read/write<br />
#Endpoint 0 to SPI read/write for FPGA control registers<br />
#Endpoint 2 bulk out to SPI for loading FPGA bitstream<br />
#Endpoint 6 bulk in to read capture data from FPGA/SDRAM<br />
<br />
* '''EEPROM''' Atmel AT24C02 2Kbit<br />
:This non-volatile memory stores:<br />
#VID:PID which is 77a1:01a2 for LA1016 and LA2016 devices<br />
#'magic number' to identify model and revision<br />
#purchase date (presumably for warranty claims)<br />
#other information related to U10 but not of interest to sigrok<br />
<br />
* '''FPGA''' Altera EP4CE6<br />
:Currently requires the OEM bitstream.<br />
:Has a bank of approximately 60 byte-wide registers accessed via SPI which are used to contol FPGA functions.<br />
:Captures 16 input channels, performs compression (run length encoding, 16bit sample plus 8 bit repetition count).<br />
:Stores samples to SDRAM (or streams direct to USB but we don't implement that method).<br />
:Interestingly, this device (6K LE) shares the same die as the next up device EP4CE10 (10K LE) and can be programmed as such. However, functionality would not be guaranteed as CE6 devices may be CE10 rejects.<br />
:If open source FPGA code were to become available there would be capacity to experiment with more advanced triggers, such as pattern trigger for SPI or I2C.<br />
<br />
* '''SDRAM''' Samsung DDR2<br />
:Samples are stored as 3 bytes (16bit sample plus 8 bit repetition count).<br />
:A 'transfer packet' for upload is 16 bytes = 5 compressed samples plus a sequence number byte.<br />
:Burst read/write for this SDRAM is up to 16 bytes, which matches the transfer packet size and is likely used for all SDRAM read/writes.<br />
<br />
* '''U10''' Kingst Authentication Device<br />
:Not used by sigrok.<br />
#Provides fixed bytes identifier to FPGA for bitstream validation (either LA1016 100MHz or LA2016 200MHz bitstream)<br />
#Provides challenge-response rolling-code for OEM software to authenticate the device as genuine 'Kingst'<br />
<br />
<br />
Datasheets:<br />
<br />
:U1 [https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv.html EP4CE6F17C8N] Cyclone IV E FPGA<br />
:U2,4,5,7 [http://sxsemi.com/upfile/PDWL050019-SOT236.pdf PDWL050019] TVS Diode Array<br />
:U3 [https://www.cypress.com/part/cy7c68013a-100axc CY7C68013A-100AXC] EZUSB MCU<br />
:U6,U8 [http://www.sg-micro.com/show-product-510.html SGM2019] Linear Regulator<br />
:U9 [https://www.microchip.com/wwwproducts/en/AT24C02C AT24C02] EEPROM 2kbit<br />
:U10 (device not identified, small MCU of some type)<br />
:U11 K4T1G164QG-BCF8, DDR2 SDRAM, obsolete<br />
:U12,U13 [http://www.sg-micro.com/show-product-519.html SGM6013] Switch-mode Regulator<br />
:U14 [http://www.sg-micro.com/show-product-203.html SGM8272] Dual Op-amp<br />
:U15 [http://www.ti.com/lit/ds/symlink/tps60403.pdf TPS60403] Charge Pump Voltage Inverter<br />
<br />
<br />
== Photos ==<br />
<br />
<gallery><br />
File:Kingst la2016 package contents.jpg|<small>Package contents</small><br />
File:Kingst la2016 paper.jpg|<small>Paper</small><br />
File:Kingst la2016 device top.jpg|<small>Device, top</small><br />
File:Kingst la2016 device bottom.jpg|<small>Device, bottom</small><br />
File:Kingst la2016 pcb top.jpg|<small>PCB, top</small><br />
File:Kingst la2016 pcb bottom.jpg|<small>PCB, bottom</small><br />
File:Kingst la2016 cypress fx2.jpg|<small>Cypress FX2</small><br />
File:Kingst la2016 altera cyclone4 ep4ce6f17c8n.jpg|<small>Altera Cyclone IV</small><br />
File:Kingst la2016 samsung k4t1g164qg.jpg|<small>Samsung K4T1G164QG</small><br />
File:Kingst la2016 atmel 24c02n.jpg|<small>Atmel 24C02N</small><br />
File:Kingst la2016 unmarked ic.jpg|<small>Unmarked IC</small><br />
File:Kingst la2016 fpni.jpg|<small>PFNI</small><br />
</gallery><br />
<br />
== Firmware ==<br />
<br />
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/kingst-la sigrok-fwextract-kingst-la2016] script from the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree sigrok-util] repo and place them in one of the usual [[Firmware#Where_to_put_the_firmware_files|places where libsigrok expects firmware files]]:<br />
<br />
<small><br />
$ '''./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS'''<br />
saved 5430 bytes to kingst-la-01a2.fw (crc32=720551a9)<br />
saved 178362 bytes to kingst-la2016a1-fpga.bitstream (crc32=7cc894fa)<br />
saved 178542 bytes to kingst-la2016-fpga.bitstream (crc32=20694ff1)<br />
saved 178379 bytes to kingst-la1016a1-fpga.bitstream (crc32=166866be)<br />
saved 178151 bytes to kingst-la1016-fpga.bitstream (crc32=7db70001)<br />
</small><br />
<br />
== Resources ==<br />
<br />
* [http://www.qdkingst.com/en/download Vendor software]<br />
* [http://www.qdkingst.com/download/vis_ug_en User guide]<br />
<br />
[[Category:Device]]<br />
[[Category:Logic analyzer]]<br />
[[Category:Supported]]</div>Planet9https://sigrok.org/w/index.php?title=Kingst_LA2016&diff=16200Kingst LA20162021-09-12T15:12:43Z<p>Planet9: </p>
<hr />
<div>{{Infobox logic analyzer<br />
| image = [[File:Kingst la2016 mugshot.png|180px]]<br />
| name = Kingst LA2016<br />
| status = supported<br />
| source_code_dir = kingst-la2016<br />
| channels = 16<br />
| samplerate = 200MHz max.<br />
| samplerate_state = State analysis not supported<br />
| triggers = Level (multiple channels)<br/>Edge (one channel)<br />
| voltages = -50V &mdash; 50V<br />
| threshold = Configurable:<br/>-4V&mdash;4V, min step 0.01V<br />
| memory = 128MByte DDR2 SDRAM<br/>40M&mdash;10G samples<br />
| compression = Yes<br />
| website = [http://www.qdkingst.com/en qdkingst.com]<br />
}}<br />
<br />
The '''Kingst LA2016''' is a USB-based, 16-channel logic analyser with 200MHz maximum sampling rate.<br />
The current vendor is "Qingdao Kingst Electronics Co., Ltd." but older models are branded "Jiankun" rather than "Kingst".<br />
The vendor software can be freely downloaded from their [http://www.qdkingst.com/en/products website].<br />
<br />
See [[Kingst LA2016/Info]] for more details (such as '''lsusb -v''' output) about the device.<br />
<br />
2021-09-12 status: The Kingst LA2016 and LA1016 are now supported in the PulseView nightly build for Linux.<br />
The macOS build is not yet tested AFAIK. There is a USB issue on the Windows build, so it's not useable at present but is being investigated. More info here:<br />
* [https://github.com/sigrokproject/libsigrok/pull/131 Driver changes]<br />
* [https://github.com/sigrokproject/sigrok-util/pull/7 Firmware extraction]<br />
<br />
<br />
== Hardware ==<br />
<br />
This logic analyser has been on the market since around 2012 and there are a few different revisions of it.<br />
The [[Media:Kingst_LA2016_LA1016_Schematic.zip|schematic]] has been reverse engineered from<br />
a unit purchased in 2020 containing a PCB marked as v1.3.0. <br />
The circuitry of older PCBs is similar but may have different voltage regulators, different input<br />
channel routing to the FPGA, and lack the input threshold adjustment.<br />
<br />
The LA1016 uses identical hardware with a different FPGA bitstream which limits the sample rate to 100MHz maximum.<br />
<br />
All of these devices use the same firmware for the FX2LP MCU but there are four different FPGA bitstreams;<br />
i.e. LA1016 & LA2016 bitstreams and the older versions of these (to swap some of the input channels as required by PCB routing changes).<br />
Once the FX2LP firmware has been loaded, a 'magic number' is read from EEPROM which identifies the<br />
device and thus allows the correct FPGA bitstream to be loaded.<br />
<br />
Note that the LA1016 cannot be boosted to 200MHz by changing the 'magic number' or the FPGA bitstream.<br />
When the FPGA initialises, its reads 16 bytes from U10 which are used to authenticate the bitstream; these bytes are different for 100 and 200MHz devices.<br />
Furthermore, the OEM software performs a challenge-response with U10 to authenticate the logic analyser as genuine 'Kingst'.<br />
The good news is that U10 does not impact sigrok support in any way and we don't need to communicate with it.<br />
<br />
<br />
Main components and their function:<br />
<br />
* '''MCU''' Cypress FX2LP<br />
:This MCU only has volatile memory and in this implementation it's firmware is loaded from the host by the application software.<br />
:Either the OEM firmware or open source firmware can be used.<br />
:In essence, it just performs data moving operations:<br />
#Endpoint 0 to EEPROM read/write<br />
#Endpoint 0 to SPI read/write for FPGA control registers<br />
#Endpoint 2 bulk out to SPI for loading FPGA bitstream<br />
#Endpoint 6 bulk in to read capture data from FPGA/SDRAM<br />
<br />
* '''EEPROM''' Atmel AT24C02 2Kbit<br />
:This non-volatile memory stores:<br />
#VID:PID which is 77a1:01a2 for LA1016 and LA2016 devices<br />
#'magic number' to identify model and revision<br />
#purchase date (presumably for warranty claims)<br />
#other information related to U10 but not of interest to sigrok<br />
<br />
* '''FPGA''' Altera EP4CE6<br />
:Currently requires the OEM bitstream.<br />
:Has a bank of approximately 60 byte-wide registers accessed via SPI which are used to contol FPGA functions.<br />
:Captures 16 input channels, performs compression (run length encoding, 16bit sample plus 8 bit repetition count).<br />
:Stores samples to SDRAM (or streams direct to USB but we don't implement that method).<br />
:Interestingly, this device (6K LE) shares the same die as the next up device EP4CE10 (10K LE) and can be programmed as such. However, functionality would not be guaranteed as CE6 devices may be CE10 rejects.<br />
:If open source FPGA code were to become available there would be capacity to experiment with more advanced triggers, such as pattern trigger for SPI or I2C.<br />
<br />
* '''SDRAM''' Samsung DDR2<br />
:Samples are stored as 3 bytes (16bit sample plus 8 bit repetition count).<br />
:A 'transfer packet' for upload is 16 bytes = 5 compressed samples plus a sequence number byte.<br />
:Burst read/write for this SDRAM is up to 16 bytes, which matches the transfer packet size and is likely used for all SDRAM read/writes.<br />
<br />
* '''U10''' Kingst Authentication Device<br />
:Not used by sigrok.<br />
#Provides fixed bytes identifier to FPGA for bitstream validation (either LA1016 100MHz or LA2016 200MHz bitstream)<br />
#Provides challenge-response rolling-code for OEM software to authenticate the device as genuine 'Kingst'<br />
<br />
<br />
Datasheets:<br />
<br />
:U1 [https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv.html EP4CE6F17C8N] Cyclone IV E FPGA<br />
:U2,4,5,7 [http://sxsemi.com/upfile/PDWL050019-SOT236.pdf PDWL050019] TVS Diode Array<br />
:U3 [https://www.cypress.com/part/cy7c68013a-100axc CY7C68013A-100AXC] EZUSB MCU<br />
:U6,U8 [http://www.sg-micro.com/show-product-510.html SGM2019] Linear Regulator<br />
:U9 [https://www.microchip.com/wwwproducts/en/AT24C02C AT24C02] EEPROM 2kbit<br />
:U10 (device not identified, small MCU of some type)<br />
:U11 K4T1G164QG-BCF8, DDR2 SDRAM, obsolete<br />
:U12,U13 [http://www.sg-micro.com/show-product-519.html SGM6013] Switch-mode Regulator<br />
:U14 [http://www.sg-micro.com/show-product-203.html SGM8272] Dual Op-amp<br />
:U15 [http://www.ti.com/lit/ds/symlink/tps60403.pdf TPS60403] Charge Pump Voltage Inverter<br />
<br />
<br />
== Photos ==<br />
<br />
<gallery><br />
File:Kingst la2016 package contents.jpg|<small>Package contents</small><br />
File:Kingst la2016 paper.jpg|<small>Paper</small><br />
File:Kingst la2016 device top.jpg|<small>Device, top</small><br />
File:Kingst la2016 device bottom.jpg|<small>Device, bottom</small><br />
File:Kingst la2016 pcb top.jpg|<small>PCB, top</small><br />
File:Kingst la2016 pcb bottom.jpg|<small>PCB, bottom</small><br />
File:Kingst la2016 cypress fx2.jpg|<small>Cypress FX2</small><br />
File:Kingst la2016 altera cyclone4 ep4ce6f17c8n.jpg|<small>Altera Cyclone IV</small><br />
File:Kingst la2016 samsung k4t1g164qg.jpg|<small>Samsung K4T1G164QG</small><br />
File:Kingst la2016 atmel 24c02n.jpg|<small>Atmel 24C02N</small><br />
File:Kingst la2016 unmarked ic.jpg|<small>Unmarked IC</small><br />
File:Kingst la2016 fpni.jpg|<small>PFNI</small><br />
</gallery><br />
<br />
== Firmware ==<br />
<br />
'''TODO This extraction script needs an update'''<br />
<br />
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/kingst-la sigrok-fwextract-kingst-la2016] script from the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree sigrok-util] repo and place them in one of the usual [[Firmware#Where_to_put_the_firmware_files|places where libsigrok expects firmware files]]:<br />
<br />
<small><br />
$ '''./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS'''<br />
saved 180224 bytes to kingst-la2016a-fpga.bitstream<br />
saved 5350 bytes to kingst-la-01a1.fw<br />
saved 5430 bytes to kingst-la-01a2.fw<br />
saved 5718 bytes to kingst-la-01a3.fw<br />
saved 142412 bytes to kingst-la-01a4.fw<br />
saved 5452 bytes to kingst-la-03a1.fw<br />
</small><br />
<br />
== Resources ==<br />
<br />
* [http://www.qdkingst.com/en/download Vendor software]<br />
* [http://www.qdkingst.com/download/vis_ug_en User guide]<br />
<br />
[[Category:Device]]<br />
[[Category:Logic analyzer]]<br />
[[Category:Supported]]</div>Planet9https://sigrok.org/w/index.php?title=Kingst_LA2016&diff=16130Kingst LA20162021-07-13T14:00:21Z<p>Planet9: </p>
<hr />
<div>{{Infobox logic analyzer<br />
| image = [[File:Kingst la2016 mugshot.png|180px]]<br />
| name = Kingst LA2016<br />
| status = supported<br />
| source_code_dir = kingst-la2016<br />
| channels = 16<br />
| samplerate = 200MHz max.<br />
| samplerate_state = State analysis not supported<br />
| triggers = Level (multiple channels)<br/>Edge (one channel)<br />
| voltages = -50V &mdash; 50V<br />
| threshold = Configurable:<br/>-4V&mdash;4V, min step 0.01V<br />
| memory = 128MByte DDR2 SDRAM<br/>40M&mdash;10G samples<br />
| compression = Yes<br />
| website = [http://www.qdkingst.com/en qdkingst.com]<br />
}}<br />
<br />
The '''Kingst LA2016''' is a USB-based, 16-channel logic analyser with 200MHz maximum sampling rate.<br />
The current vendor is "Qingdao Kingst Electronics Co., Ltd." but older models are branded "Jiankun" rather than "Kingst".<br />
The vendor software can be freely downloaded from their [http://www.qdkingst.com/en/products website].<br />
<br />
See [[Kingst LA2016/Info]] for more details (such as '''lsusb -v''' output) about the device.<br />
<br />
2021-03-30 status: This device is basically supported, captures can be made. <br />
But some important features still are not available or not fully operational. <br />
It's yet to get determined what these features are that currently don't work as intended.<br />
(This wiki page needs an update so that users can determine whether _their_ use case is covered.)<br />
<br />
2021-07-13 status: Some users are reporting this device does not function with PulseView. In this case, please try these PRs:<br />
<br />
* [https://github.com/sigrokproject/sigrok-util/pull/7 Firmware extraction]<br />
* [https://github.com/sigrokproject/libsigrok/pull/131 Driver changes]<br />
<br />
<br />
== Hardware ==<br />
<br />
This logic analyser has been on the market since around 2012 and there are a few different revisions of it.<br />
The [[Media:Kingst_LA2016_LA1016_Schematic.zip|schematic]] has been reverse engineered from<br />
a unit purchased in 2020 containing a PCB marked as v1.3.0. <br />
The circuitry of older PCBs is similar but may have different voltage regulators, different input<br />
channel routing to the FPGA, and lack the input threshold adjustment.<br />
<br />
The LA1016 uses identical hardware with a different FPGA bitstream which limits the sample rate to 100MHz maximum.<br />
<br />
All of these devices use the same firmware for the FX2LP MCU but there are four different FPGA bitstreams;<br />
i.e. LA1016 & LA2016 bitstreams and the older versions of these (to swap some of the input channels as required by PCB routing changes).<br />
Once the FX2LP firmware has been loaded, a 'magic number' is read from EEPROM which identifies the<br />
device and thus allows the correct FPGA bitstream to be loaded.<br />
<br />
Note that the LA1016 cannot be boosted to 200MHz by changing the 'magic number' or the FPGA bitstream.<br />
When the FPGA initialises, its reads 16 bytes from U10 which are used to authenticate the bitstream; these bytes are different for 100 and 200MHz devices.<br />
Furthermore, the OEM software performs a challenge-response with U10 to authenticate the logic analyser as genuine 'Kingst'.<br />
The good news is that U10 does not impact sigrok support in any way and we don't need to communicate with it.<br />
<br />
<br />
Main components and their function:<br />
<br />
* '''MCU''' Cypress FX2LP<br />
:This MCU only has volatile memory and in this implementation it's firmware is loaded from the host by the application software.<br />
:Either the OEM firmware or open source firmware can be used.<br />
:In essence, it just performs data moving operations:<br />
#Endpoint 0 to EEPROM read/write<br />
#Endpoint 0 to SPI read/write for FPGA control registers<br />
#Endpoint 2 bulk out to SPI for loading FPGA bitstream<br />
#Endpoint 6 bulk in to read capture data from FPGA/SDRAM<br />
<br />
* '''EEPROM''' Atmel AT24C02 2Kbit<br />
:This non-volatile memory stores:<br />
#VID:PID which is 77a1:01a2 for LA1016 and LA2016 devices<br />
#'magic number' to identify model and revision<br />
#purchase date (presumably for warranty claims)<br />
#other information related to U10 but not of interest to sigrok<br />
<br />
* '''FPGA''' Altera EP4CE6<br />
:Currently requires the OEM bitstream.<br />
:Has a bank of approximately 60 byte-wide registers accessed via SPI which are used to contol FPGA functions.<br />
:Captures 16 input channels, performs compression (run length encoding, 16bit sample plus 8 bit repetition count).<br />
:Stores samples to SDRAM (or streams direct to USB but we don't implement that method).<br />
:Interestingly, this device (6K LE) shares the same die as the next up device EP4CE10 (10K LE) and can be programmed as such. However, functionality would not be guaranteed as CE6 devices may be CE10 rejects.<br />
:If open source FPGA code were to become available there would be capacity to experiment with more advanced triggers, such as pattern trigger for SPI or I2C.<br />
<br />
* '''SDRAM''' Samsung DDR2<br />
:Samples are stored as 3 bytes (16bit sample plus 8 bit repetition count).<br />
:A 'transfer packet' for upload is 16 bytes = 5 compressed samples plus a sequence number byte.<br />
:Burst read/write for this SDRAM is up to 16 bytes, which matches the transfer packet size and is likely used for all SDRAM read/writes.<br />
<br />
* '''U10''' Kingst Authentication Device<br />
:Not used by sigrok.<br />
#Provides fixed bytes identifier to FPGA for bitstream validation (either LA1016 100MHz or LA2016 200MHz bitstream)<br />
#Provides challenge-response rolling-code for OEM software to authenticate the device as genuine 'Kingst'<br />
<br />
<br />
Datasheets:<br />
<br />
:U1 [https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv.html EP4CE6F17C8N] Cyclone IV E FPGA<br />
:U2,4,5,7 [http://sxsemi.com/upfile/PDWL050019-SOT236.pdf PDWL050019] TVS Diode Array<br />
:U3 [https://www.cypress.com/part/cy7c68013a-100axc CY7C68013A-100AXC] EZUSB MCU<br />
:U6,U8 [http://www.sg-micro.com/show-product-510.html SGM2019] Linear Regulator<br />
:U9 [https://www.microchip.com/wwwproducts/en/AT24C02C AT24C02] EEPROM 2kbit<br />
:U10 (device not identified, small MCU of some type)<br />
:U11 K4T1G164QG-BCF8, DDR2 SDRAM, obsolete<br />
:U12,U13 [http://www.sg-micro.com/show-product-519.html SGM6013] Switch-mode Regulator<br />
:U14 [http://www.sg-micro.com/show-product-203.html SGM8272] Dual Op-amp<br />
:U15 [http://www.ti.com/lit/ds/symlink/tps60403.pdf TPS60403] Charge Pump Voltage Inverter<br />
<br />
<br />
== Photos ==<br />
<br />
<gallery><br />
File:Kingst la2016 package contents.jpg|<small>Package contents</small><br />
File:Kingst la2016 paper.jpg|<small>Paper</small><br />
File:Kingst la2016 device top.jpg|<small>Device, top</small><br />
File:Kingst la2016 device bottom.jpg|<small>Device, bottom</small><br />
File:Kingst la2016 pcb top.jpg|<small>PCB, top</small><br />
File:Kingst la2016 pcb bottom.jpg|<small>PCB, bottom</small><br />
File:Kingst la2016 cypress fx2.jpg|<small>Cypress FX2</small><br />
File:Kingst la2016 altera cyclone4 ep4ce6f17c8n.jpg|<small>Altera Cyclone IV</small><br />
File:Kingst la2016 samsung k4t1g164qg.jpg|<small>Samsung K4T1G164QG</small><br />
File:Kingst la2016 atmel 24c02n.jpg|<small>Atmel 24C02N</small><br />
File:Kingst la2016 unmarked ic.jpg|<small>Unmarked IC</small><br />
File:Kingst la2016 fpni.jpg|<small>PFNI</small><br />
</gallery><br />
<br />
== Firmware ==<br />
<br />
'''TODO This extraction script needs an update'''<br />
<br />
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/kingst-la sigrok-fwextract-kingst-la2016] script from the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree sigrok-util] repo and place them in one of the usual [[Firmware#Where_to_put_the_firmware_files|places where libsigrok expects firmware files]]:<br />
<br />
<small><br />
$ '''./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS'''<br />
saved 180224 bytes to kingst-la2016a-fpga.bitstream<br />
saved 5350 bytes to kingst-la-01a1.fw<br />
saved 5430 bytes to kingst-la-01a2.fw<br />
saved 5718 bytes to kingst-la-01a3.fw<br />
saved 142412 bytes to kingst-la-01a4.fw<br />
saved 5452 bytes to kingst-la-03a1.fw<br />
</small><br />
<br />
== Resources ==<br />
<br />
* [http://www.qdkingst.com/en/download Vendor software]<br />
* [http://www.qdkingst.com/download/vis_ug_en User guide]<br />
<br />
[[Category:Device]]<br />
[[Category:Logic analyzer]]<br />
[[Category:Supported]]</div>Planet9https://sigrok.org/w/index.php?title=Kingst_LA2016/Info&diff=16073Kingst LA2016/Info2021-04-02T10:42:30Z<p>Planet9: </p>
<hr />
<div>== lsusb (before firmware upload) ==<br />
<br />
<small><br />
$ '''lsusb -v'''<br />
Bus 002 Device 008: ID '''77a1:01a2'''<br />
Device Descriptor:<br />
bLength 18<br />
bDescriptorType 1<br />
bcdUSB 2.00<br />
bDeviceClass 255 '''Vendor Specific Class'''<br />
bDeviceSubClass 255 '''Vendor Specific Subclass'''<br />
bDeviceProtocol 255 '''Vendor Specific Protocol'''<br />
bMaxPacketSize0 64<br />
idVendor 0x77a1 <br />
idProduct 0x01a2 <br />
bcdDevice 0.00<br />
iManufacturer 0 <br />
iProduct 0 <br />
iSerial 0 <br />
bNumConfigurations 1<br />
Configuration Descriptor:<br />
bLength 9<br />
bDescriptorType 2<br />
wTotalLength 171<br />
bNumInterfaces 1<br />
bConfigurationValue 1<br />
iConfiguration 0 <br />
bmAttributes 0x80<br />
(Bus Powered)<br />
MaxPower 100mA<br />
Interface Descriptor:<br />
bLength 9<br />
bDescriptorType 4<br />
bInterfaceNumber 0<br />
bAlternateSetting 0<br />
bNumEndpoints 0<br />
bInterfaceClass 255 Vendor Specific Class<br />
bInterfaceSubClass 255 Vendor Specific Subclass<br />
bInterfaceProtocol 255 Vendor Specific Protocol<br />
iInterface 0 <br />
Interface Descriptor:<br />
bLength 9<br />
bDescriptorType 4<br />
bInterfaceNumber 0<br />
bAlternateSetting 1<br />
bNumEndpoints 6<br />
bInterfaceClass 255 Vendor Specific Class<br />
bInterfaceSubClass 255 Vendor Specific Subclass<br />
bInterfaceProtocol 255 Vendor Specific Protocol<br />
iInterface 0 <br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x01 EP 1 OUT<br />
bmAttributes 2<br />
Transfer Type Bulk<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 0<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x81 EP 1 IN<br />
bmAttributes 2<br />
Transfer Type Bulk<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 0<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x02 EP 2 OUT<br />
bmAttributes 2<br />
Transfer Type Bulk<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 0<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x04 EP 4 OUT<br />
bmAttributes 2<br />
Transfer Type Bulk<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 0<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x86 EP 6 IN<br />
bmAttributes 2<br />
Transfer Type Bulk<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 0<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x88 EP 8 IN<br />
bmAttributes 2<br />
Transfer Type Bulk<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 0<br />
Interface Descriptor:<br />
bLength 9<br />
bDescriptorType 4<br />
bInterfaceNumber 0<br />
bAlternateSetting 2<br />
bNumEndpoints 6<br />
bInterfaceClass 255 Vendor Specific Class<br />
bInterfaceSubClass 255 Vendor Specific Subclass<br />
bInterfaceProtocol 255 Vendor Specific Protocol<br />
iInterface 0 <br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x01 EP 1 OUT<br />
bmAttributes 3<br />
Transfer Type Interrupt<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0040 1x 64 bytes<br />
bInterval 1<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x81 EP 1 IN<br />
bmAttributes 3<br />
Transfer Type Interrupt<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0040 1x 64 bytes<br />
bInterval 1<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x02 EP 2 OUT<br />
bmAttributes 3<br />
Transfer Type Interrupt<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 1<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x04 EP 4 OUT<br />
bmAttributes 2<br />
Transfer Type Bulk<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 0<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x86 EP 6 IN<br />
bmAttributes 3<br />
Transfer Type Interrupt<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 1<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x88 EP 8 IN<br />
bmAttributes 2<br />
Transfer Type Bulk<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 0<br />
Interface Descriptor:<br />
bLength 9<br />
bDescriptorType 4<br />
bInterfaceNumber 0<br />
bAlternateSetting 3<br />
bNumEndpoints 6<br />
bInterfaceClass 255 Vendor Specific Class<br />
bInterfaceSubClass 255 Vendor Specific Subclass<br />
bInterfaceProtocol 255 Vendor Specific Protocol<br />
iInterface 0 <br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x01 EP 1 OUT<br />
bmAttributes 3<br />
Transfer Type Interrupt<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0040 1x 64 bytes<br />
bInterval 1<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x81 EP 1 IN<br />
bmAttributes 3<br />
Transfer Type Interrupt<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0040 1x 64 bytes<br />
bInterval 1<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x02 EP 2 OUT<br />
bmAttributes 1<br />
Transfer Type Isochronous<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 1<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x04 EP 4 OUT<br />
bmAttributes 2<br />
Transfer Type Bulk<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 0<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x86 EP 6 IN<br />
bmAttributes 1<br />
Transfer Type Isochronous<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 1<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x88 EP 8 IN<br />
bmAttributes 2<br />
Transfer Type Bulk<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 0<br />
Device Qualifier (for other device speed):<br />
bLength 10<br />
bDescriptorType 6<br />
bcdUSB 2.00<br />
bDeviceClass 255 Vendor Specific Class<br />
bDeviceSubClass 255 Vendor Specific Subclass<br />
bDeviceProtocol 255 Vendor Specific Protocol<br />
bMaxPacketSize0 64<br />
bNumConfigurations 1<br />
Device Status: 0x0000<br />
(Bus Powered)<br />
</small><br />
<br />
== lsusb (after firmware upload) ==<br />
<br />
<small><br />
$ '''lsusb -v'''<br />
Bus 001 Device 022: ID '''77a1:01a2 Kingst Kingst Logic Analyzer'''<br />
Device Descriptor:<br />
bLength 18<br />
bDescriptorType 1<br />
bcdUSB 2.00<br />
bDeviceClass 0 <br />
bDeviceSubClass 0 <br />
bDeviceProtocol 0 <br />
bMaxPacketSize0 64<br />
idVendor 0x77a1 <br />
idProduct 0x01a2 <br />
bcdDevice 0.00<br />
iManufacturer 1 '''Kingst'''<br />
iProduct 2 '''Kingst Logic Analyzer'''<br />
iSerial 0 <br />
bNumConfigurations 1<br />
Configuration Descriptor:<br />
bLength 9<br />
bDescriptorType 2<br />
wTotalLength 0x0020<br />
bNumInterfaces 1<br />
bConfigurationValue 1<br />
iConfiguration 0 <br />
bmAttributes 0x80<br />
(Bus Powered)<br />
MaxPower 100mA<br />
Interface Descriptor:<br />
bLength 9<br />
bDescriptorType 4<br />
bInterfaceNumber 0<br />
bAlternateSetting 0<br />
bNumEndpoints 2<br />
bInterfaceClass 255 Vendor Specific Class<br />
bInterfaceSubClass 0 <br />
bInterfaceProtocol 0 <br />
iInterface 0 <br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x02 EP 2 OUT<br />
bmAttributes 2<br />
Transfer Type Bulk<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 0<br />
Endpoint Descriptor:<br />
bLength 7<br />
bDescriptorType 5<br />
bEndpointAddress 0x86 EP 6 IN<br />
bmAttributes 2<br />
Transfer Type Bulk<br />
Synch Type None<br />
Usage Type Data<br />
wMaxPacketSize 0x0200 1x 512 bytes<br />
bInterval 0<br />
Device Qualifier (for other device speed):<br />
bLength 10<br />
bDescriptorType 6<br />
bcdUSB 2.00<br />
bDeviceClass 0 <br />
bDeviceSubClass 0 <br />
bDeviceProtocol 0 <br />
bMaxPacketSize0 64<br />
bNumConfigurations 1<br />
Device Status: 0x0000<br />
(Bus Powered)<br />
</small><br />
<br />
== Observations of the LA2016 Internal SPI Bus ==<br />
<br />
<small><br />
<br />
The software on the host PC controls the logic analyser capture settings by writing to a set of byte-wide control registers within the FPGA.<br /><br />
It contains around 60 registers which are accessed using the SPI bus between the FX2 MCU and the FPGA (see schematic on sigrok wiki page).<br /><br />
The SPI bus is configured with the FX2 as master and FPGA as slave. Every SPI transaction is two bytes and is framed by SPI CS (active low).<br /><br />
The first byte contains the register address and a READ/write bit. The second byte contains the data, which is either written to the<br /><br />
FPGA or read from it. Note that these transactions are all least significant bit first on the SPI bus, so your LA will need to<br /><br />
reverse the bit order to interpret correctly.<br /><br />
<br /><br />
Capture status can be read from register address 0x00 and 0x01. After a capture has completed, information about the data location in SDRAM can<br /><br />
be read from addresses 0x10-0x1B. For other registers, reading is not implemented and they just read as 0xFF. Where reading is implemented, the<br /><br />
same address is used to access different registers based on read/write. For example, FPGA status is read from address 0x00 and 0x01 but writing 0x03<br /><br />
to address 0x00 starts an acquistion.<br /><br />
<br /><br />
The FX2 MCU is simply acting as a 'dumb' gateway, translating USB requests for FPGA access into SPI bus requests. USB control OUT vendor class<br /><br />
transfers with bRequest of 0x20 will write to the FPGA registers, whereas IN transfers will read them. For example, a USB request to read two<br /><br />
bytes starting from address 0x00 would cause the FX2 to issue a SPI read for address 0x00 and then a read for address 0x01.<br /><br />
<br /><br />
<br />
=== SPI bus activity during OEM software initialisation ===<br />
<br />
First byte is FPGA register address. The MSbit is set for READ transfers.<br />
|<br />
| Second byte is data being written or read<br />
| |<br />
| |<br />
80 FF <-- Read RUN STATUS<br />
81 FF<br />
<br />
80 FF <-- Read RUN STATUS<br />
81 FF<br />
<br />
68 3F <-- Write SET INPUT THRESHOLD <br />
69 02<br />
6A F2<br />
6B 00<br />
<br />
02 00 <-- Halt USER PWM outputs to begin settings change<br />
<br />
70 40 <-- USER PWM1 SETTINGS<br />
71 0D<br />
72 03<br />
73 00<br />
74 A0<br />
75 86<br />
76 01<br />
77 00<br />
<br />
78 D0 <-- USER PWM2 SETTINGS<br />
79 07<br />
7A 00<br />
7B 00<br />
7C E8<br />
7D 03<br />
7E 00<br />
7F 00<br />
<br />
02 03 <-- enable USER PWM outputs<br />
<br />
<br />
<br />
<br />
=== SPI bus activity during capture sequence ===<br />
<br />
<br />
OEM software with no triggers set does this to FPGA regs:<br />
<br />
<br />
First byte is FPGA register address. The MSbit is set for READ transfers.<br />
|<br />
| Second byte is data being written or read<br />
| |<br />
| |<br />
03 00 <-- Set capture mode to be "write to SDRAM", rather than stream mode (where reg 03 = 01)<br />
<br />
TRIGGER SETUP<br />
20 FF <-- enable all 16 channels (change on any channel will cause new repetition packet)<br />
21 FF<br />
22 00 <-- no triggers active<br />
23 00<br />
24 00<br />
25 00<br />
26 00<br />
27 00<br />
28 00<br />
29 00<br />
2A 00<br />
2B 00<br />
2C 00<br />
2D 00<br />
2E 00<br />
2F 00<br />
<br />
SAMPLING SETUP<br />
10 40 <-- 32 bit total samples count request<br />
11 42<br />
12 0F<br />
13 00<br />
14 00 <-- always zero<br />
15 00 <-- 32 bit pre-trigger samples<br />
16 00<br />
17 00<br />
18 00<br />
19 00 <- always zero<br />
1A 00 <--|<br />
1B 00 <--These 3 bytes are pre_trigger_mem_bytes, see set_sample_config()<br />
1C 04 <--|<br />
1D C8 <-- Capture rate 1D is divisor LSbyte 200MHz / divisor - sample rate<br />
1E 00 <-- 1E is divisor MSbyte<br />
1F 00<br />
<br />
<br />
00 03 <--- RUN now running the capture<br />
<br />
<br />
80 E2 Reading capture status every 100ms or so from register address 0x00 and 0x01<br />
81 85 The run_state values in order are:<br />
0x85E2: Pre-sampling (for samples before trigger position, e.g. half of samples when set at 50% capture ratio)<br />
0x85EA: Waiting for trigger<br />
0x85EE: Running<br />
0x85ED: Done<br />
<br />
80 EE <br />
81 85 <br />
<br />
80 EE<br />
81 85 <br />
<br />
80 ED<br />
81 85<br />
<br />
<br />
<br />
<br />
Read 12 bytes from the FPGA registers starting at address 0x10 FPGA_REG_CTRL_BULK to get:<br />
32bit n_rep_packets<br />
32bit n_rep_packets_before_trigger<br />
32bit write_pos <br />
90 xx<br />
91 xx<br />
92 xx<br />
93 xx<br />
94 xx see capture_info() driver function<br />
95 xx <br />
96 xx xx == value depends on capture data<br />
97 xx<br />
98 xx<br />
99 xx<br />
9A xx<br />
9B xx<br />
<br />
<br />
FPGA_REG_UPLOAD Write two 32 bit numbers, SDRAM start address and n bytes for bulk upload<br />
08 00<br />
09 00<br />
0A 00<br />
0B 00 values written are derived from the above info on capture data<br />
0C 20<br />
0D A9<br />
0E 61<br />
0F 00<br />
<br />
<br />
01 01 Write to start the transfer of capture data from SDRAM to FX2 fifos (issued by FX2 when it receives USB command 0x38 START BULK TRANSFER)<br />
<br />
3ms gap<br />
<br />
00 00 HALT capture engine<br />
<br />
</small><br />
<br />
<br />
__FORCETOC__</div>Planet9https://sigrok.org/w/index.php?title=Kingst_LA2016&diff=16064Kingst LA20162021-03-06T14:17:22Z<p>Planet9: </p>
<hr />
<div>{{Infobox logic analyzer<br />
| image = [[File:Kingst la2016 mugshot.png|180px]]<br />
| name = Kingst LA2016<br />
| status = in progress<br />
| source_code_dir = kingst-la2016<br />
| channels = 16<br />
| samplerate = 200MHz max.<br />
| samplerate_state = State analysis not supported<br />
| triggers = Level (multiple channels)<br/>Edge (one channel)<br />
| voltages = -50V &mdash; 50V<br />
| threshold = Configurable:<br/>-4V&mdash;4V, min step 0.01V<br />
| memory = 128MByte DDR2 SDRAM<br/>40M&mdash;10G samples<br />
| compression = Yes<br />
| website = [http://www.qdkingst.com/en qdkingst.com]<br />
}}<br />
<br />
'''5th March 2021:'''<br/><br />
'''This device was previously marked as supported, however, some users are reporting issues and we are working on driver changes.'''<br />
<br />
<br />
The '''Kingst LA2016''' is a USB-based, 16-channel logic analyser with 200MHz maximum sampling rate.<br />
The current vendor is "Qingdao Kingst Electronics Co., Ltd." but older models are branded "Jiankun" rather than "Kingst".<br />
The vendor software can be freely downloaded from their [http://www.qdkingst.com/en/products website].<br />
<br />
<br />
== Hardware ==<br />
This logic analyser has been on the market since around 2012 and there are a few different revisions of it.<br />
The [[Media:Kingst_LA2016_LA1016_Schematic.zip|schematic]] has been reverse engineered from<br />
a unit purchased in 2020 containing a PCB marked as v1.3.0. <br />
The circuitry of older PCBs is similar but may have different voltage regulators, different input<br />
channel routing to the FPGA, and lack the input threshold adjustment.<br />
<br />
The LA1016 uses identical hardware with a different FPGA bitstream which limits the sample rate to 100MHz maximum.<br />
<br />
All of these devices use the same firmware for the FX2LP MCU but there are four different FPGA bitstreams;<br />
i.e. LA1016 & LA2016 bitstreams and the older versions of these (to swap some of the input channels as required by PCB routing changes).<br />
Once the FX2LP firmware has been loaded, a 'magic number' is read from EEPROM which identifies the<br />
device and thus allows the correct FPGA bitstream to be loaded.<br />
<br />
Note that the LA1016 cannot be boosted to 200MHz by changing the 'magic number' or the FPGA bitstream.<br />
When the FPGA initialises, its reads 16 bytes from U10 which are used to authenticate the bitstream; these bytes are different for 100 and 200MHz devices.<br />
Furthermore, the OEM software performs a challenge-response with U10 to authenticate the logic analyser as genuine 'Kingst'.<br />
The good news is that U10 does not impact Sigrok support in any way and we don't need to communicate with it.<br />
<br />
<br />
Main components and their function:<br />
<br />
* '''MCU''' Cypress FX2LP<br />
:This MCU only has volatile memory and in this implementation it's firmware is loaded from the host by the application software.<br />
:Either the OEM firmware or open source firmware can be used.<br />
:In essence, it just performs data moving operations:<br />
#Endpoint 0 to EEPROM read/write<br />
#Endpoint 0 to SPI read/write for FPGA control registers<br />
#Endpoint 2 bulk out to SPI for loading FPGA bitstream<br />
#Endpoint 6 bulk in to read capture data from FPGA/SDRAM<br />
<br />
* '''EEPROM''' Atmel AT24C02 2Kbit<br />
:This non-volatile memory stores:<br />
#VID:PID which is 77a1:01a2 for LA1016 and LA2016 devices<br />
#'magic number' to identify model and revision<br />
#purchase date (presumably for warranty claims)<br />
#other information related to U10 but not of interest to Sigrok<br />
<br />
* '''FPGA''' Altera EP4CE6<br />
:Currently requires the OEM bitstream.<br />
:Has a bank of approximately 60 byte-wide registers accessed via SPI which are used to contol FPGA functions.<br />
:Captures 16 input channels, performs compression (run length encoding, 16bit sample plus 8 bit repetition count).<br />
:Stores samples to SDRAM (or streams direct to USB but we don't implement that method).<br />
:Interestingly, this device (6K LE) shares the same die as the next up device EP4CE10 (10K LE) and can be programmed as such. However, functionality would not be guaranteed as CE6 devices may be CE10 rejects.<br />
:If open source FPGA code were to become available there would be capacity to experiment with more advanced triggers, such as pattern trigger for SPI or I2C.<br />
<br />
* '''SDRAM''' Samsung DDR2<br />
:Samples are stored as 3 bytes (16bit sample plus 8 bit repetition count).<br />
:A 'transfer packet' for upload is 16 bytes = 5 compressed samples plus a sequence number byte.<br />
:Burst read/write for this SDRAM is up to 16 bytes, which matches the transfer packet size and is likely used for all SDRAM read/writes.<br />
<br />
* '''U10''' Kingst Authentication Device<br />
:Not used by Sigrok.<br />
#Provides fixed bytes identifier to FPGA for bitstream validation (either LA1016 100MHz or LA2016 200MHz bitstream)<br />
#Provides challenge-response rolling-code for OEM software to authenticate the device as genuine 'Kingst'<br />
<br />
<br />
Datasheets:<br />
<br />
:U1 [https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv.html EP4CE6F17C8N] Cyclone IV E FPGA<br />
:U2,4,5,7 [http://sxsemi.com/upfile/PDWL050019-SOT236.pdf PDWL050019] TVS Diode Array<br />
:U3 [https://www.cypress.com/part/cy7c68013a-100axc CY7C68013A-100AXC] EZUSB MCU<br />
:U6,U8 [http://www.sg-micro.com/show-product-510.html SGM2019] Linear Regulator<br />
:U9 [https://www.microchip.com/wwwproducts/en/AT24C02C AT24C02] EEPROM 2kbit<br />
:U10 (device not identified, small MCU of some type)<br />
:U11 K4T1G164QG-BCF8, DDR2 SDRAM, obsolete<br />
:U12,U13 [http://www.sg-micro.com/show-product-519.html SGM6013] Switch-mode Regulator<br />
:U14 [http://www.sg-micro.com/show-product-203.html SGM8272] Dual Op-amp<br />
:U15 [http://www.ti.com/lit/ds/symlink/tps60403.pdf TPS60403] Charge Pump Voltage Inverter<br />
<br />
<br />
== Photos ==<br />
<br />
<gallery><br />
File:Kingst la2016 package contents.jpg|<small>Package contents</small><br />
File:Kingst la2016 paper.jpg|<small>Paper</small><br />
File:Kingst la2016 device top.jpg|<small>Device, top</small><br />
File:Kingst la2016 device bottom.jpg|<small>Device, bottom</small><br />
File:Kingst la2016 pcb top.jpg|<small>PCB, top</small><br />
File:Kingst la2016 pcb bottom.jpg|<small>PCB, bottom</small><br />
File:Kingst la2016 cypress fx2.jpg|<small>Cypress FX2</small><br />
File:Kingst la2016 altera cyclone4 ep4ce6f17c8n.jpg|<small>Altera Cyclone IV</small><br />
File:Kingst la2016 samsung k4t1g164qg.jpg|<small>Samsung K4T1G164QG</small><br />
File:Kingst la2016 atmel 24c02n.jpg|<small>Atmel 24C02N</small><br />
File:Kingst la2016 unmarked ic.jpg|<small>Unmarked IC</small><br />
File:Kingst la2016 fpni.jpg|<small>PFNI</small><br />
</gallery><br />
<br />
== Firmware ==<br />
<br />
'''TODO This extraction script needs updated'''<br />
<br />
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/kingst-la sigrok-fwextract-kingst-la2016] script from the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree sigrok-util] repo and place them in one of the usual [[Firmware#Where_to_put_the_firmware_files|places where libsigrok expects firmware files]]:<br />
<br />
<small><br />
$ '''./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS'''<br />
saved 180224 bytes to kingst-la2016a-fpga.bitstream<br />
saved 5350 bytes to kingst-la-01a1.fw<br />
saved 5430 bytes to kingst-la-01a2.fw<br />
saved 5718 bytes to kingst-la-01a3.fw<br />
saved 142412 bytes to kingst-la-01a4.fw<br />
saved 5452 bytes to kingst-la-03a1.fw<br />
</small><br />
<br />
== Resources ==<br />
<br />
* [http://www.qdkingst.com/en/download Vendor software]<br />
* [http://www.qdkingst.com/download/vis_ug_en User guide]<br />
<br />
[[Category:Device]]<br />
[[Category:Logic analyzer]]<br />
[[Category:In progress]]</div>Planet9https://sigrok.org/w/index.php?title=Kingst_LA2016&diff=16063Kingst LA20162021-03-06T14:00:57Z<p>Planet9: </p>
<hr />
<div>{{Infobox logic analyzer<br />
| image = [[File:Kingst la2016 mugshot.png|180px]]<br />
| name = Kingst LA2016<br />
| status = in progress<br />
| source_code_dir = kingst-la2016<br />
| channels = 16<br />
| samplerate = 200MHz max.<br />
| samplerate_state = State analysis not supported<br />
| triggers = Level (multiple channels)<br/>Edge (one channel)<br />
| voltages = -50V &mdash; 50V<br />
| threshold = Configurable:<br/>-4V&mdash;4V, min step 0.01V<br />
| memory = 128MByte DDR2 SDRAM<br/>40M&mdash;10G samples<br />
| compression = Yes<br />
| website = [http://www.qdkingst.com/en qdkingst.com]<br />
}}<br />
<br />
'''5th March 2021:'''<br/><br />
'''This device was previously marked as supported, however, some users are reporting issues and we are working on driver changes.'''<br />
<br />
<br />
The '''Kingst LA2016''' is a USB-based, 16-channel logic analyser with 200MHz maximum sampling rate.<br />
The current vendor is "Qingdao Kingst Electronics Co., Ltd." but older models are branded "Jiankun" rather than "Kingst".<br />
The vendor software can be freely downloaded from their [http://www.qdkingst.com/en/products website].<br />
<br />
<br />
== Hardware ==<br />
This logic analyser has been on the market since around 2012 and there are a few different revisions of it.<br />
This [[Media:Kingst_LA2016_LA1016_Schematic.zip|schematic]] has been reverse engineered from<br />
a unit purchased in 2020 containing a PCB marked as v1.3.0. <br />
The circuitry of older PCBs is similar but may have different voltage regulators, different input<br />
channel routing to the FPGA, and lack the input threshold adjustment.<br />
<br />
The LA1016 uses identical hardware with a different FPGA bitstream which limits the sample rate to 100MHz maximum.<br />
<br />
All of these devices use the same firmware for the FX2LP MCU but there are four different FPGA bitstreams;<br />
i.e. LA1016 & LA2016 bitstreams and the older versions of these (to swap some of the input channels as required by PCB routing changes).<br />
Once the FX2LP firmware has been loaded, a 'magic number' is read from EEPROM which identifies the<br />
device and thus allows the correct FPGA bitstream to be loaded.<br />
<br />
Note that the LA1016 cannot be boosted to 200MHz by changing the 'magic number' or the FPGA bitstream.<br />
When the FPGA initialises, its reads 16 bytes from U10 which are used to authenticate the bitstream; these bytes are different for 100 and 200MHz devices.<br />
Furthermore, the OEM software performs a challenge-response with U10 to authenticate the logic analyser as genuine 'Kingst'.<br />
The good news is that U10 does not impact Sigrok support in any way and we don't need to communicate with it.<br />
<br />
<br />
Main components and their function:<br />
<br />
* '''MCU''' Cypress FX2LP<br />
:This MCU only has volatile memory and in this implementation it's firmware is loaded from the host by the application software.<br />
:Either the OEM firmware or open source firmware can be used.<br />
:In essence, it just performs data moving operations:<br />
#Endpoint 0 to EEPROM read/write<br />
#Endpoint 0 to SPI read/write for FPGA control registers<br />
#Endpoint 2 bulk out to SPI for loading FPGA bitstream<br />
#Endpoint 6 bulk in to read capture data from FPGA/SDRAM<br />
<br />
* '''EEPROM''' Atmel AT24C02 2Kbit<br />
:This non-volatile memory stores:<br />
#VID:PID which is 77a1:01a2 for LA1016 and LA2016 devices<br />
#'magic number' to identify model and revision<br />
#purchase date (presumably for warranty claims)<br />
#other information related to U10 but not of interest to Sigrok<br />
<br />
* '''FPGA''' Altera EP4CE6<br />
:Currently requires the OEM bitstream.<br />
:Has a bank of approximately 60 byte-wide registers accessed via SPI which are used to contol FPGA functions.<br />
:Captures 16 input channels, performs compression (run length encoding, 16bit sample plus 8 bit repetition count).<br />
:Stores samples to SDRAM (or streams direct to USB but we don't implement that method).<br />
:Interestingly, this device (6K LE) shares the same die as the next up device EP4CE10 (10K LE) and can be programmed as such. However, functionality would not be guaranteed as CE6 devices may be CE10 rejects.<br />
:If open source FPGA code were to become available there would be capacity to experiment with more advanced triggers, such as pattern trigger for SPI or I2C.<br />
<br />
* '''SDRAM''' Samsung DDR2<br />
:Samples are stored as 3 bytes (16bit sample plus 8 bit repetition count).<br />
:A 'transfer packet' for upload is 16 bytes = 5 compressed samples plus a sequence number byte.<br />
:Burst read/write for this SDRAM is up to 16 bytes, which matches the transfer packet size and is likely used for all SDRAM read/writes.<br />
<br />
* '''U10''' Kingst Authentication Device<br />
:Not used by Sigrok.<br />
#Provides fixed bytes identifier to FPGA for bitstream validation (either LA1016 100MHz or LA2016 200MHz bitstream)<br />
#Provides challenge-response rolling-code for OEM software to authenticate the device as genuine 'Kingst'<br />
<br />
<br />
Datasheets:<br />
<br />
:U1 [https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv.html EP4CE6F17C8N] Cyclone IV E FPGA<br />
:U2,4,5,7 [http://sxsemi.com/upfile/PDWL050019-SOT236.pdf PDWL050019] TVS Diode Array<br />
:U3 [https://www.cypress.com/part/cy7c68013a-100axc CY7C68013A-100AXC] EZUSB MCU<br />
:U6,U8 [http://www.sg-micro.com/show-product-510.html SGM2019] Linear Regulator<br />
:U9 [https://www.microchip.com/wwwproducts/en/AT24C02C AT24C02] EEPROM 2kbit<br />
:U10 (device not identified, small MCU of some type)<br />
:U11 K4T1G164QG-BCF8, DDR2 SDRAM, obsolete<br />
:U12,U13 [http://www.sg-micro.com/show-product-519.html SGM6013] Switch-mode Regulator<br />
:U14 [http://www.sg-micro.com/show-product-203.html SGM8272] Dual Op-amp<br />
:U15 [http://www.ti.com/lit/ds/symlink/tps60403.pdf TPS60403] Charge Pump Voltage Inverter<br />
<br />
<br />
== Photos ==<br />
<br />
<gallery><br />
File:Kingst la2016 package contents.jpg|<small>Package contents</small><br />
File:Kingst la2016 paper.jpg|<small>Paper</small><br />
File:Kingst la2016 device top.jpg|<small>Device, top</small><br />
File:Kingst la2016 device bottom.jpg|<small>Device, bottom</small><br />
File:Kingst la2016 pcb top.jpg|<small>PCB, top</small><br />
File:Kingst la2016 pcb bottom.jpg|<small>PCB, bottom</small><br />
File:Kingst la2016 cypress fx2.jpg|<small>Cypress FX2</small><br />
File:Kingst la2016 altera cyclone4 ep4ce6f17c8n.jpg|<small>Altera Cyclone IV</small><br />
File:Kingst la2016 samsung k4t1g164qg.jpg|<small>Samsung K4T1G164QG</small><br />
File:Kingst la2016 atmel 24c02n.jpg|<small>Atmel 24C02N</small><br />
File:Kingst la2016 unmarked ic.jpg|<small>Unmarked IC</small><br />
File:Kingst la2016 fpni.jpg|<small>PFNI</small><br />
</gallery><br />
<br />
== Firmware ==<br />
<br />
'''TODO This extraction script needs updated'''<br />
<br />
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/kingst-la sigrok-fwextract-kingst-la2016] script from the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree sigrok-util] repo and place them in one of the usual [[Firmware#Where_to_put_the_firmware_files|places where libsigrok expects firmware files]]:<br />
<br />
<small><br />
$ '''./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS'''<br />
saved 180224 bytes to kingst-la2016a-fpga.bitstream<br />
saved 5350 bytes to kingst-la-01a1.fw<br />
saved 5430 bytes to kingst-la-01a2.fw<br />
saved 5718 bytes to kingst-la-01a3.fw<br />
saved 142412 bytes to kingst-la-01a4.fw<br />
saved 5452 bytes to kingst-la-03a1.fw<br />
</small><br />
<br />
== Resources ==<br />
<br />
* [http://www.qdkingst.com/en/download Vendor software]<br />
* [http://www.qdkingst.com/download/vis_ug_en User guide]<br />
<br />
[[Category:Device]]<br />
[[Category:Logic analyzer]]<br />
[[Category:In progress]]</div>Planet9https://sigrok.org/w/index.php?title=Kingst_LA2016&diff=16062Kingst LA20162021-03-06T13:51:49Z<p>Planet9: </p>
<hr />
<div>{{Infobox logic analyzer<br />
| image = [[File:Kingst la2016 mugshot.png|180px]]<br />
| name = Kingst LA2016<br />
| status = in progress<br />
| source_code_dir = kingst-la2016<br />
| channels = 16<br />
| samplerate = 200MHz max.<br />
| samplerate_state = State analysis not supported<br />
| triggers = Level (multiple channels)<br/>Edge (one channel)<br />
| voltages = -50V &mdash; 50V<br />
| threshold = Configurable:<br/>-4V&mdash;4V, min step 0.01V<br />
| memory = 128MByte DDR2 SDRAM<br/>40M&mdash;10G samples<br />
| compression = Yes<br />
| website = [http://www.qdkingst.com/en qdkingst.com]<br />
}}<br />
<br />
'''5th March 2021:'''<br/><br />
'''This device was previously marked as supported, however, some users are reporting issues and we are working on driver changes.'''<br />
<br />
<br />
The '''Kingst LA2016''' is a USB-based, 16-channel logic analyser with 200MHz maximum sampling rate.<br />
The current vendor is "Qingdao Kingst Electronics Co., Ltd." but older models are branded "Jiankun" rather than "Kingst".<br />
The vendor software can be freely downloaded from their [http://www.qdkingst.com/en/products website].<br />
<br />
<br />
== Hardware ==<br />
This logic analyser has been on the market since around 2012 and there are a few different revisions of it.<br />
This [[Media:Kingst_LA2016_LA1016_Schematic.zip|schematic]] has been reverse engineered from<br />
a unit purchased in 2020 containing a PCB marked as v1.3.0. <br />
The circuitry of older PCBs is similar but may have different voltage regulators, different input<br />
channel routing to the FPGA, and lack the input threshold adjustment.<br />
<br />
The LA1016 uses identical hardware with a different FPGA bitstream which limits the sample rate to 100MHz maximum.<br />
<br />
All of these devices use the same firmware for the FX2LP MCU but there are four different FPGA bitstreams;<br />
i.e. LA1016 & LA2016 bitstreams and the older versions of these (to swap some of the input channels as required by PCB routing changes).<br />
Once the FX2LP firmware has been loaded, a 'magic number' is read from EEPROM which identifies the<br />
device and thus allows the correct FPGA bitstream to be loaded.<br />
<br />
Note that the LA1016 cannot be boosted to 200MHz by changing the 'magic number' or the FPGA bitstream.<br />
When the FPGA initialises, its reads 16 bytes from U10 which are used to authenticate the bitstream; these bytes are different for 100 and 200MHz devices.<br />
Furthermore, the OEM software performs a challenge-response with U10 to authenticate the logic analyser as genuine 'Kingst'.<br />
The good news is that U10 does not impact Sigrok support in any way and we don't need to communicate with it.<br />
<br />
<br />
Main components and their function:<br />
<br />
* '''MCU''' Cypress FX2LP<br />
:This MCU only has volatile memory and in this implementation it's firmware is loaded from the host by the application software.<br />
:Either the OEM firmware or open source firmware can be used.<br />
:In essence, it just performs data moving operations:<br />
#Endpoint 0 to EEPROM read/write<br />
#Endpoint 0 to SPI read/write for FPGA control registers<br />
#Endpoint 2 bulk out to SPI for loading FPGA bitstream<br />
#Endpoint 6 bulk in to read capture data from FPGA/SDRAM<br />
<br />
* '''EEPROM''' Atmel AT24C02 2Kbit<br />
:This non-volatile memory stores:<br />
#VID:PID which is 77a1:01a2 for LA1016 and LA2016 devices<br />
#'magic number' to identify model and revision<br />
#purchase date (presumably for warranty claims)<br />
#other information related to U10 but not of interest to Sigrok<br />
<br />
* '''FPGA''' Altera EP4CE6<br />
:Currently requires the OEM bitstream.<br />
:Has a bank of approximately 60 byte-wide registers accessed via SPI which are used to contol FPGA functions.<br />
:Captures 16 input channels, performs compression (run length encoding, 16bit sample plus 8 bit repetition count).<br />
:Stores samples to SDRAM (or streams direct to USB but we don't implement that method).<br />
:Interestingly, this device (6K LE) shares the same die as the next up device EP4CE10 (10K LE) and can be programmed as such. However, functionality would not be guaranteed as CE6 devices may be CE10 rejects.<br />
<br />
* '''SDRAM''' Samsung DDR2<br />
:Samples are stored as 3 bytes (16bit sample plus 8 bit repetition count).<br />
:A 'transfer packet' for upload is 16 bytes = 5 compressed samples plus a sequence number byte.<br />
:Burst read/write for this SDRAM is up to 16 bytes, which matches the transfer packet size and is likely used for all SDRAM read/writes.<br />
<br />
* '''U10''' Kingst Authentication Device<br />
:Not used by Sigrok.<br />
#Provides fixed bytes identifier to FPGA for bitstream validation (either LA1016 100MHz or LA2016 200MHz bitstream)<br />
#Provides challenge-response rolling-code for OEM software to authenticate the device as genuine 'Kingst'<br />
<br />
<br />
Datasheets:<br />
<br />
:U1 [https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv.html EP4CE6F17C8N] Cyclone IV E FPGA<br />
:U2,4,5,7 [http://sxsemi.com/upfile/PDWL050019-SOT236.pdf PDWL050019] TVS Diode Array<br />
:U3 [https://www.cypress.com/part/cy7c68013a-100axc CY7C68013A-100AXC] EZUSB MCU<br />
:U6,U8 [http://www.sg-micro.com/show-product-510.html SGM2019] Linear Regulator<br />
:U9 [https://www.microchip.com/wwwproducts/en/AT24C02C AT24C02] EEPROM 2kbit<br />
:U10 (device not identified, small MCU of some type)<br />
:U11 K4T1G164QG-BCF8, DDR2 SDRAM, obsolete<br />
:U12,U13 [http://www.sg-micro.com/show-product-519.html SGM6013] Switch-mode Regulator<br />
:U14 [http://www.sg-micro.com/show-product-203.html SGM8272] Dual Op-amp<br />
:U15 [http://www.ti.com/lit/ds/symlink/tps60403.pdf TPS60403] Charge Pump Voltage Inverter<br />
<br />
<br />
== Photos ==<br />
<br />
<gallery><br />
File:Kingst la2016 package contents.jpg|<small>Package contents</small><br />
File:Kingst la2016 paper.jpg|<small>Paper</small><br />
File:Kingst la2016 device top.jpg|<small>Device, top</small><br />
File:Kingst la2016 device bottom.jpg|<small>Device, bottom</small><br />
File:Kingst la2016 pcb top.jpg|<small>PCB, top</small><br />
File:Kingst la2016 pcb bottom.jpg|<small>PCB, bottom</small><br />
File:Kingst la2016 cypress fx2.jpg|<small>Cypress FX2</small><br />
File:Kingst la2016 altera cyclone4 ep4ce6f17c8n.jpg|<small>Altera Cyclone IV</small><br />
File:Kingst la2016 samsung k4t1g164qg.jpg|<small>Samsung K4T1G164QG</small><br />
File:Kingst la2016 atmel 24c02n.jpg|<small>Atmel 24C02N</small><br />
File:Kingst la2016 unmarked ic.jpg|<small>Unmarked IC</small><br />
File:Kingst la2016 fpni.jpg|<small>PFNI</small><br />
</gallery><br />
<br />
== Firmware ==<br />
<br />
'''TODO This extraction script needs updated'''<br />
<br />
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/kingst-la sigrok-fwextract-kingst-la2016] script from the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree sigrok-util] repo and place them in one of the usual [[Firmware#Where_to_put_the_firmware_files|places where libsigrok expects firmware files]]:<br />
<br />
<small><br />
$ '''./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS'''<br />
saved 180224 bytes to kingst-la2016a-fpga.bitstream<br />
saved 5350 bytes to kingst-la-01a1.fw<br />
saved 5430 bytes to kingst-la-01a2.fw<br />
saved 5718 bytes to kingst-la-01a3.fw<br />
saved 142412 bytes to kingst-la-01a4.fw<br />
saved 5452 bytes to kingst-la-03a1.fw<br />
</small><br />
<br />
== Resources ==<br />
<br />
* [http://www.qdkingst.com/en/download Vendor software]<br />
* [http://www.qdkingst.com/download/vis_ug_en User guide]<br />
<br />
[[Category:Device]]<br />
[[Category:Logic analyzer]]<br />
[[Category:In progress]]</div>Planet9https://sigrok.org/w/index.php?title=Kingst_LA2016&diff=16061Kingst LA20162021-03-05T17:27:37Z<p>Planet9: </p>
<hr />
<div>{{Infobox logic analyzer<br />
| image = [[File:Kingst la2016 mugshot.png|180px]]<br />
| name = Kingst LA2016<br />
| status = in progress<br />
| source_code_dir = kingst-la2016<br />
| channels = 16<br />
| samplerate = 200MHz max.<br />
| samplerate_state = State analysis not supported<br />
| triggers = Level (multiple channels)<br/>Edge (one channel)<br />
| voltages = -50V &mdash; 50V<br />
| threshold = Configurable:<br/>-4V&mdash;4V, min step 0.01V<br />
| memory = 128MByte DDR2 SDRAM<br/>40M&mdash;10G samples<br />
| compression = Yes<br />
| website = [http://www.qdkingst.com/en qdkingst.com]<br />
}}<br />
<br />
'''5th March 2021:'''<br/><br />
'''This device was previously marked as supported, however, some users are reporting issues with this device and we are working on some driver changes.'''<br />
<br />
<br />
The '''Kingst LA2016''' is a USB-based, 16-channel logic analyser with 200MHz maximum sampling rate.<br />
The current vendor is "Qingdao Kingst Electronics Co., Ltd." but older models appear to be branded "Jiankun" rather than "Kingst".<br />
The vendor software can be freely downloaded from their [http://www.qdkingst.com/en/products website].<br />
<br />
<br />
== Hardware ==<br />
This logic analyser has been on the market since around 2012 and there are a few different revisions of it.<br />
This [[Media:Kingst_LA2016_LA1016_Schematic.zip|schematic]] has been reverse engineered from<br />
a unit purchased in 2020 containing a PCB marked as v1.3.0. <br />
The circuitry of older PCBs is similar but may have different voltage regulators, different input<br />
channel routing to the FPGA and no input threshold adjustment.<br />
<br />
The LA1016 uses identical hardware with a different FPGA bitstream which limits the sample rate to 100MHz maximum.<br />
<br />
All of these devices use the same firmware for the FX2LP MCU but there are four different FPGA bitstreams;<br />
i.e. LA1016 & LA2016 bitstreams and the older versions of these (to swap some of the input channels).<br />
Once the FX2LP firmware has been loaded, a 'magic number' is read from EEPROM which identifies the<br />
device and thus allows the correct FPGA bitstream to be loaded.<br />
<br />
Note that the LA1016 cannot be boosted to 200MHz by<br />
changing the 'magic number' or the FPGA bitstream because of device U10 which<br />
is used by the FPGA to authenticate the bitstream. It is also used by the OEM software to authenticate<br />
the logic analyser as genuine 'Kingst'. U10 does not impact Sigrok support in any way and we don't need<br />
to communicate with it.<br />
<br />
<br />
Main components and their function:<br />
<br />
* '''MCU''' Cypress FX2LP<br />
:This MCU only has volatile memory and in this implementation it's firmware is loaded from the host by the application software.<br />
:Either the OEM firmware or open source firmware can be used.<br />
:In essence, it just performs data moving operations:<br />
#Endpoint 0 to EEPROM read/write<br />
#Endpoint 0 to SPI read/write for FPGA control registers<br />
#Endpoint 2 bulk out to SPI for loading FPGA bitstream<br />
#Endpoint 6 bulk in to read capture data from FPGA/SDRAM<br />
<br />
* '''EEPROM''' Atmel AT24C02 2Kbit<br />
:This non-volatile memory stores:<br />
#VID:PID which is 77a1:01a2 for LA1016 and LA2016 devices.<br />
#'magic number' to identify model and revision<br />
#purchase date (presumably for warranty claims)<br />
#other information related to U10 but not of interest to Sigrok<br />
<br />
* '''FPGA''' Altera EP4CE6<br />
:Currently requires the OEM bitstream.<br />
:Has a bank of approximately 60 byte-wide registers accessed via SPI which are used to contol FPGA functions.<br />
:Captures 16 input channels, performs compression (run length encoding, 16bit sample plus 8 bit repetition count).<br />
:Stores samples to SDRAM (or streams direct to USB but we don't implement that method).<br />
:Interestingly, this device (6K LE) shares the same die as the next up device EP4CE10 (10K LE) and can be programmed as such. However, functionality would not be guaranteed as CE6 devices may be CE10 rejects.<br />
<br />
* '''SDRAM''' Samsung DDR2<br />
:Samples are stored as 3 bytes (16bit sample plus 8 bit repetition count)<br />
:A 'transfer packet' for upload is 16 bytes = 5 compressed samples plus a sequence number byte<br />
:Burst read/write for this SDRAM is up to 16 bytes, which matches the transfer packet size and is likely used for all SDRAM read/writes.<br />
<br />
* '''U10''' Kingst Authentication Device<br />
:Not used by Sigrok<br />
#Provides fixed bytes identifier to FPGA for bitstream validation (either LA1016 100MHz or LA2016 200MHz bitstream)<br />
#Provides challenge-response rolling-code for OEM software to authenticate the device as genuine Kingst<br />
<br />
<br />
Datasheets:<br />
<br />
:U1 [https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv.html EP4CE6F17C8N] Cyclone IV E FPGA<br />
:U2,4,5,7 [http://sxsemi.com/upfile/PDWL050019-SOT236.pdf PDWL050019] TVS Diode Array<br />
:U3 [https://www.cypress.com/part/cy7c68013a-100axc CY7C68013A-100AXC] EZUSB MCU<br />
:U6,U8 [http://www.sg-micro.com/show-product-510.html SGM2019] Linear Regulator<br />
:U9 [https://www.microchip.com/wwwproducts/en/AT24C02C AT24C02] EEPROM 2kbit<br />
:U10 (device not identified, small MCU of some type)<br />
:U11 K4T1G164QG-BCF8, DDR2 SDRAM, obsolete<br />
:U12,U13 [http://www.sg-micro.com/show-product-519.html SGM6013] Switch-mode Regulator<br />
:U14 [http://www.sg-micro.com/show-product-203.html SGM8272] Dual Op-amp<br />
:U15 [http://www.ti.com/lit/ds/symlink/tps60403.pdf TPS60403] Charge Pump Voltage Inverter<br />
<br />
<br />
== Photos ==<br />
<br />
<gallery><br />
File:Kingst la2016 package contents.jpg|<small>Package contents</small><br />
File:Kingst la2016 paper.jpg|<small>Paper</small><br />
File:Kingst la2016 device top.jpg|<small>Device, top</small><br />
File:Kingst la2016 device bottom.jpg|<small>Device, bottom</small><br />
File:Kingst la2016 pcb top.jpg|<small>PCB, top</small><br />
File:Kingst la2016 pcb bottom.jpg|<small>PCB, bottom</small><br />
File:Kingst la2016 cypress fx2.jpg|<small>Cypress FX2</small><br />
File:Kingst la2016 altera cyclone4 ep4ce6f17c8n.jpg|<small>Altera Cyclone IV</small><br />
File:Kingst la2016 samsung k4t1g164qg.jpg|<small>Samsung K4T1G164QG</small><br />
File:Kingst la2016 atmel 24c02n.jpg|<small>Atmel 24C02N</small><br />
File:Kingst la2016 unmarked ic.jpg|<small>Unmarked IC</small><br />
File:Kingst la2016 fpni.jpg|<small>PFNI</small><br />
</gallery><br />
<br />
== Firmware ==<br />
<br />
'''TODO This extraction script needs updated'''<br />
<br />
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/kingst-la sigrok-fwextract-kingst-la2016] script from the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree sigrok-util] repo and place them in one of the usual [[Firmware#Where_to_put_the_firmware_files|places where libsigrok expects firmware files]]:<br />
<br />
<small><br />
$ '''./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS'''<br />
saved 180224 bytes to kingst-la2016a-fpga.bitstream<br />
saved 5350 bytes to kingst-la-01a1.fw<br />
saved 5430 bytes to kingst-la-01a2.fw<br />
saved 5718 bytes to kingst-la-01a3.fw<br />
saved 142412 bytes to kingst-la-01a4.fw<br />
saved 5452 bytes to kingst-la-03a1.fw<br />
</small><br />
<br />
== Resources ==<br />
<br />
* [http://www.qdkingst.com/en/download Vendor software]<br />
* [http://www.qdkingst.com/download/vis_ug_en User guide]<br />
<br />
[[Category:Device]]<br />
[[Category:Logic analyzer]]<br />
[[Category:In progress]]</div>Planet9https://sigrok.org/w/index.php?title=Kingst_LA2016&diff=16060Kingst LA20162021-03-05T17:16:57Z<p>Planet9: </p>
<hr />
<div>{{Infobox logic analyzer<br />
| image = [[File:Kingst la2016 mugshot.png|180px]]<br />
| name = Kingst LA2016<br />
| status = in progress<br />
| source_code_dir = kingst-la2016<br />
| channels = 16<br />
| samplerate = 200MHz max.<br />
| samplerate_state = State analysis not supported<br />
| triggers = Level (multiple channels)<br/>Edge (one channel)<br />
| voltages = -50V &mdash; 50V<br />
| threshold = Configurable:<br/>-4V&mdash;4V, min step 0.01V<br />
| memory = 128MByte DDR2 SDRAM<br/>40M&mdash;10G samples<br />
| compression = Yes<br />
| website = [http://www.qdkingst.com/en qdkingst.com]<br />
}}<br />
<br />
'''5th March 2021:'''<br/><br />
'''This device was previously marked as supported, however, some users are reporting issues with this device and we are working on some driver changes.'''<br />
<br />
<br />
The '''Kingst LA2016''' is a USB-based, 16-channel logic analyser with 200MHz maximum sampling rate.<br />
The current vendor is "Qingdao Kingst Electronics Co., Ltd." but older models appear to be branded "Jiankun" rather than "Kingst".<br />
The vendor software can be freely downloaded from their [http://www.qdkingst.com/en/products website].<br />
<br />
<br />
== Hardware ==<br />
This logic analyser has been on the market since around 2012 and there are a few different revisions of it.<br />
This [[Media:Kingst_LA2016_LA1016_Schematic.zip|schematic]] has been reverse engineered from<br />
a unit purchased in 2020 containing a PCB marked as v1.3.0. <br />
The circuitry of older PCBs is similar but may have different voltage regulators, different input<br />
channel routing to the FPGA and no input threshold adjustment.<br />
<br />
The LA1016 uses identical hardware with a different FPGA bitstream which limits the sample rate to 100MHz maximum.<br />
<br />
All of these devices use the same firmware for the FX2LP MCU but there are four different FPGA bitstreams;<br />
i.e. LA1016 & LA2016 bitstreams and the older versions of these (to swap some of the input channels).<br />
Once the FX2LP firmware has been loaded, a 'magic number' is read from EEPROM which identifies the<br />
device and thus allows the correct FPGA bitstream to be loaded.<br />
<br />
Note that the LA1016 cannot be boosted to 200MHz by<br />
changing the 'magic number' or the FPGA bitstream because of device U10 which<br />
is used by the FPGA to authenticate the bitstream. It is also used by the OEM software to authenticate<br />
the logic analyser as genuine 'Kingst'. U10 does not impact Sigrok support in any way and we don't need<br />
to communicate with it.<br />
<br />
<br />
Main components and their function:<br />
<br />
* '''MCU''' Cypress FX2LP<br />
:This MCU only has volatile memory and in this implementation it's firmware is loaded from the host by the application software.<br />
:Either the OEM firmware or open source firmware can be used.<br />
:In essence, it just performs data moving operations:<br />
#Endpoint 0 to EEPROM read/write<br />
#Endpoint 0 to SPI read/write for FPGA control registers<br />
#Endpoint 2 bulk out to SPI for loading FPGA bitstream<br />
#Endpoint 6 bulk in to read capture data from FPGA/SDRAM<br />
<br />
* '''EEPROM''' Atmel AT24C02 2Kbit<br />
:This non-volatile memory stores:<br />
#VID:PID which is 77a1:01a2 for LA1016 and LA2016 devices.<br />
#'magic number' to identify model and revision<br />
#purchase date (presumably for warranty claims)<br />
#other information related to U10 but not of interest to Sigrok<br />
<br />
* '''FPGA''' Altera EP4CE6<br />
:Currently requires the OEM bitstream.<br />
:Has a bank of approximately 60 byte-wide registers accessed via SPI which are used to contol FPGA functions.<br />
:Captures 16 input channels, performs compression (run length encoding, 16bit sample plus 8 bit repetition count).<br />
:Stores samples to SDRAM (or streams direct to USB but we don't implement that method).<br />
:Interestingly, this device (6K LE) shares the same die as the next up device EP4CE10 (10K LE) and can be programmed as such. However, functionality would not be guaranteed as CE6 devices may be CE10 rejects.<br />
<br />
* '''SDRAM''' Samsung DDR2<br />
:Samples are stored as 3 bytes (16bit sample plus 8 bit repetition count)<br />
:A 'transfer packet' for upload is 16 bytes = 5 compressed samples plus a sequence number byte<br />
:Burst read/write for this SDRAM is up to 16 bytes, which matches the transfer packet size and is likely used for all SDRAM read/writes.<br />
<br />
<br />
Datasheets:<br />
<br />
:U1 [https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv.html EP4CE6F17C8N] Cyclone IV E FPGA<br />
:U2,4,5,7 [http://sxsemi.com/upfile/PDWL050019-SOT236.pdf PDWL050019] TVS Diode Array<br />
:U3 [https://www.cypress.com/part/cy7c68013a-100axc CY7C68013A-100AXC] EZUSB MCU<br />
:U6,U8 [http://www.sg-micro.com/show-product-510.html SGM2019] Linear Regulator<br />
:U9 [https://www.microchip.com/wwwproducts/en/AT24C02C AT24C02] EEPROM 2kbit<br />
:U10 (device not identified, small MCU of some type)<br />
:U11 K4T1G164QG-BCF8, DDR2 SDRAM, obsolete<br />
:U12,U13 [http://www.sg-micro.com/show-product-519.html SGM6013] Switch-mode Regulator<br />
:U14 [http://www.sg-micro.com/show-product-203.html SGM8272] Dual Op-amp<br />
:U15 [http://www.ti.com/lit/ds/symlink/tps60403.pdf TPS60403] Charge Pump Voltage Inverter<br />
<br />
<br />
== Photos ==<br />
<br />
<gallery><br />
File:Kingst la2016 package contents.jpg|<small>Package contents</small><br />
File:Kingst la2016 paper.jpg|<small>Paper</small><br />
File:Kingst la2016 device top.jpg|<small>Device, top</small><br />
File:Kingst la2016 device bottom.jpg|<small>Device, bottom</small><br />
File:Kingst la2016 pcb top.jpg|<small>PCB, top</small><br />
File:Kingst la2016 pcb bottom.jpg|<small>PCB, bottom</small><br />
File:Kingst la2016 cypress fx2.jpg|<small>Cypress FX2</small><br />
File:Kingst la2016 altera cyclone4 ep4ce6f17c8n.jpg|<small>Altera Cyclone IV</small><br />
File:Kingst la2016 samsung k4t1g164qg.jpg|<small>Samsung K4T1G164QG</small><br />
File:Kingst la2016 atmel 24c02n.jpg|<small>Atmel 24C02N</small><br />
File:Kingst la2016 unmarked ic.jpg|<small>Unmarked IC</small><br />
File:Kingst la2016 fpni.jpg|<small>PFNI</small><br />
</gallery><br />
<br />
== Firmware ==<br />
<br />
'''TODO This extraction script needs updated'''<br />
<br />
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/kingst-la sigrok-fwextract-kingst-la2016] script from the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree sigrok-util] repo and place them in one of the usual [[Firmware#Where_to_put_the_firmware_files|places where libsigrok expects firmware files]]:<br />
<br />
<small><br />
$ '''./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS'''<br />
saved 180224 bytes to kingst-la2016a-fpga.bitstream<br />
saved 5350 bytes to kingst-la-01a1.fw<br />
saved 5430 bytes to kingst-la-01a2.fw<br />
saved 5718 bytes to kingst-la-01a3.fw<br />
saved 142412 bytes to kingst-la-01a4.fw<br />
saved 5452 bytes to kingst-la-03a1.fw<br />
</small><br />
<br />
== Resources ==<br />
<br />
* [http://www.qdkingst.com/en/download Vendor software]<br />
* [http://www.qdkingst.com/download/vis_ug_en User guide]<br />
<br />
[[Category:Device]]<br />
[[Category:Logic analyzer]]<br />
[[Category:In progress]]</div>Planet9https://sigrok.org/w/index.php?title=Kingst_LA2016&diff=16059Kingst LA20162021-03-05T14:17:59Z<p>Planet9: </p>
<hr />
<div>{{Infobox logic analyzer<br />
| image = [[File:Kingst la2016 mugshot.png|180px]]<br />
| name = Kingst LA2016<br />
| status = in progress<br />
| source_code_dir = kingst-la2016<br />
| channels = 16<br />
| samplerate = 200MHz max.<br />
| samplerate_state = State analysis not supported<br />
| triggers = Level (multiple channels)<br/>Edge (one channel)<br />
| voltages = -50V &mdash; 50V<br />
| threshold = Configurable:<br/>-4V&mdash;4V, min step 0.01V<br />
| memory = 128MByte DDR2 SDRAM<br/>40M&mdash;10G samples<br />
| compression = Yes<br />
| website = [http://www.qdkingst.com/en qdkingst.com]<br />
}}<br />
<br />
'''5th March 2021:'''<br/><br />
'''This device was previously marked as supported, however, some users are reporting issues with this device and we are working on some driver changes.'''<br />
<br />
<br />
The '''Kingst LA2016''' is a USB-based, 16-channel logic analyser with 200MHz maximum sampling rate.<br />
The current vendor is "Qingdao Kingst Electronics Co., Ltd." but older models appear to be branded "Jiankun" rather than "Kingst".<br />
The vendor software can be freely downloaded from their [http://www.qdkingst.com/en/products website].<br />
<br />
<br />
== Hardware ==<br />
This logic analyser has been on the market since around 2012 and there are a few different revisions of it.<br />
This [[Media:Kingst_LA2016_LA1016_Schematic.zip|schematic]] has been reverse engineered from<br />
a unit purchased in 2020 containing a PCB marked as v1.3.0. <br />
The circuitry of early issue PCBs is similar but may have different voltage regulators, different input<br />
channel routing to the FPGA and no input threshold adjustment.<br />
<br />
The LA1016 uses identical hardware with a different FPGA bitstream which limits the sample rate to 100MHz maximum.<br />
<br />
All of these devices use the same firmware for the FX2LP MCU but there are four different FPGA bitstreams;<br />
i.e. LA1016 & LA2016 bitstreams and the older versions of these (to swap some of the input channels).<br />
Once the FX2LP firmware has been loaded, a 'magic number' is read from EEPROM which identifies the<br />
device and thus allows the correct FPGA bitstream to be loaded.<br />
<br />
Note that the LA1016 cannot be boosted to 200MHz by<br />
changing the 'magic number' or the FPGA bitstream because of device U10 which<br />
is used by the FPGA to authenticate the bitstream. It is also used by the OEM software to authenticate<br />
the logic analyser as genuine 'Kingst'. U10 does not impact Sigrok support in any way and we don't need<br />
to communicate with it.<br />
<br />
<br />
Main components and their function:<br />
<br />
* Cypress FX2LP '''MCU'''<br />
:This MCU only has volatile memory and in this implementation it's firmware is loaded from the host by the application software.<br />
:Either the OEM firmware or open source firmware can be used.<br />
:In essence, it just performs data moving operations:<br />
#Endpoint 0 to EEPROM read/write<br />
#Endpoint 0 to SPI read/write for FPGA control registers<br />
#Endpoint 2 bulk out to SPI for loading FPGA bitstream<br />
#Endpoint 6 bulk in to read capture data from FPGA/SDRAM<br />
<br />
* Atmel AT24C02 2Kbit '''EEPROM'''<br />
:This non-volatile memory stores:<br />
#VID:PID which is 77a1:01a2 for LA1016 and LA2016 devices.<br />
#'magic number' to identify model and revision<br />
#purchase date (presumably for warranty claims)<br />
#other information related to U10 but not of interest to Sigrok<br />
<br />
* Altera EP4CE6 '''FPGA'''<br />
:Currently uses the OEM bitstream.<br />
:Has a bank of approximately 60 byte-wide registers accessed via SPI which are used to contol FPGA functions.<br />
:Captures 16 input channels, performs compression (run length encoding, 16bit sample plus 8 bit repetition count).<br />
:Stores samples to SDRAM (or streams direct to USB but we don't implement that method).<br />
:Interestingly, this device (6K LE) shares the same die as the next up device EP4CE10 (10K LE) and can be programmed as such. However, functionality would not be guaranteed as CE6 devices may be CE10 rejects.<br />
<br />
* Samsung DDR2 '''SDRAM'''<br />
:Samples are stored as 3 bytes (16bit sample plus 8 bit repetition count)<br />
:A 'transfer packet' for upload is 16 bytes = 5 compressed samples plus a sequence number byte<br />
:Burst read/write for this SDRAM is up to 16 bytes, which matches the transfer packet size and is likely used for all SDRAM read/writes.<br />
<br />
<br />
Datasheets:<br />
<br />
U15 [http://www.ti.com/lit/ds/symlink/tps60403.pdf TPS60403] Charge pump voltage inverter<br />
<br />
<br />
== Photos ==<br />
<br />
<gallery><br />
File:Kingst la2016 package contents.jpg|<small>Package contents</small><br />
File:Kingst la2016 paper.jpg|<small>Paper</small><br />
File:Kingst la2016 device top.jpg|<small>Device, top</small><br />
File:Kingst la2016 device bottom.jpg|<small>Device, bottom</small><br />
File:Kingst la2016 pcb top.jpg|<small>PCB, top</small><br />
File:Kingst la2016 pcb bottom.jpg|<small>PCB, bottom</small><br />
File:Kingst la2016 cypress fx2.jpg|<small>Cypress FX2</small><br />
File:Kingst la2016 altera cyclone4 ep4ce6f17c8n.jpg|<small>Altera Cyclone IV</small><br />
File:Kingst la2016 samsung k4t1g164qg.jpg|<small>Samsung K4T1G164QG</small><br />
File:Kingst la2016 atmel 24c02n.jpg|<small>Atmel 24C02N</small><br />
File:Kingst la2016 unmarked ic.jpg|<small>Unmarked IC</small><br />
File:Kingst la2016 fpni.jpg|<small>PFNI</small><br />
</gallery><br />
<br />
== Firmware ==<br />
<br />
'''TODO This extraction script needs updated'''<br />
<br />
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/kingst-la sigrok-fwextract-kingst-la2016] script from the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree sigrok-util] repo and place them in one of the usual [[Firmware#Where_to_put_the_firmware_files|places where libsigrok expects firmware files]]:<br />
<br />
<small><br />
$ '''./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS'''<br />
saved 180224 bytes to kingst-la2016a-fpga.bitstream<br />
saved 5350 bytes to kingst-la-01a1.fw<br />
saved 5430 bytes to kingst-la-01a2.fw<br />
saved 5718 bytes to kingst-la-01a3.fw<br />
saved 142412 bytes to kingst-la-01a4.fw<br />
saved 5452 bytes to kingst-la-03a1.fw<br />
</small><br />
<br />
== Resources ==<br />
<br />
* [http://www.qdkingst.com/en/download Vendor software]<br />
* [http://www.qdkingst.com/download/vis_ug_en User guide]<br />
<br />
[[Category:Device]]<br />
[[Category:Logic analyzer]]<br />
[[Category:In progress]]</div>Planet9https://sigrok.org/w/index.php?title=Kingst_LA2016&diff=16058Kingst LA20162021-03-05T14:17:21Z<p>Planet9: </p>
<hr />
<div>{{Infobox logic analyzer<br />
| image = [[File:Kingst la2016 mugshot.png|180px]]<br />
| name = Kingst LA2016<br />
| status = in progress<br />
| source_code_dir = kingst-la2016<br />
| channels = 16<br />
| samplerate = 200MHz max.<br />
| samplerate_state = State analysis not supported<br />
| triggers = Level (multiple channels)<br/>Edge (one channel)<br />
| voltages = -50V &mdash; 50V<br />
| threshold = Configurable:<br/>-4V&mdash;4V, min step 0.01V<br />
| memory = 128MByte DDR2 SDRAM<br/>40M&mdash;10G samples<br />
| compression = Yes<br />
| website = [http://www.qdkingst.com/en qdkingst.com]<br />
}}<br />
<br />
'''5th March 2021:'''<br/><br />
'''This device was previously marked as supported, however, some users are reporting issues with this device and we are working on some driver changes.'''<br />
<br />
<br />
The '''Kingst LA2016''' is a USB-based, 16-channel logic analyser with 200MHz maximum sampling rate.<br />
The current vendor is "Qingdao Kingst Electronics Co., Ltd." but older models appear to be branded "Jiankun" rather than "Kingst".<br />
The vendor software can be freely downloaded from their [http://www.qdkingst.com/en/products website].<br />
<br />
<br />
== Hardware ==<br />
This logic analyser has been on the market since around 2012 and there are a few different revisions of it.<br />
This [[Media:Kingst_LA2016_LA1016_Schematic.zip|schematic]] has been reverse engineered from<br />
a unit purchased in 2020 containing a PCB marked as v1.3.0. <br />
The circuitry of early issue PCBs is similar but may have different voltage regulators, different input<br />
channel routing to the FPGA and no input threshold adjustment.<br />
<br />
The LA1016 uses identical hardware with a different FPGA bitstream which limits the sample rate to 100MHz maximum.<br />
<br />
All of these devices use the same firmware for the FX2LP MCU but there are four different FPGA bitstreams;<br />
i.e. LA1016 & LA2016 bitstreams and the older versions of these (to swap some of the input channels).<br />
Once the FX2LP firmware has been loaded, a 'magic number' is read from EEPROM which identifies the<br />
device and thus allows the correct FPGA bitstream to be loaded.<br />
<br />
Note that the LA1016 cannot be boosted to 200MHz by<br />
changing the 'magic number' or the FPGA bitstream because of device U10 which<br />
is used by the FPGA to authenticate the bitstream. It is also used by the OEM software to authenticate<br />
the logic analyser as genuine 'Kingst'. U10 does not impact Sigrok support in any way and we don't need<br />
to communicate with it.<br />
<br />
<br />
Main components and their function:<br />
<br />
* Cypress FX2LP '''MCU'''<br />
:This MCU only has volatile memory and in this implementation it's firmware is loaded from the host by the application software.<br />
:Either the OEM firmware or open source firmware can be used.<br />
:In essence, it just performs data moving operations:<br />
#Endpoint 0 to EEPROM read/write<br />
#Endpoint 0 to SPI read/write for FPGA control registers<br />
#Endpoint 2 bulk out to SPI for loading FPGA bitstream<br />
#Endpoint 6 bulk in to read capture data from FPGA/SDRAM<br />
<br />
* Atmel AT24C02 2Kbit '''EEPROM'''<br />
:This non-volatile memory stores:<br />
#VID:PID which is 77a1:01a2 for LA1016 and LA2016 devices.<br />
#'magic number' to identify model and revision<br />
#purchase date (presumably for warranty claims)<br />
#other information related to U10 but not of interest to Sigrok<br />
<br />
* Altera EP4CE6 '''FPGA'''<br />
:Currently uses the OEM bitstream.<br />
:Has a bank of approximately 60 byte-wide registers accessed via SPI which are used to contol FPGA functions.<br />
:Captures 16 input channels, performs compression (run length encoding, 16bit sample plus 8 bit repetition count).<br />
:Stores samples to SDRAM (or streams direct to USB but we don't implement that method).<br />
:Interestingly, this device (6K LE) shares the same die as the next up device EP4CE10 (10K LE) and can be programmed as such. However, functionality would not be guaranteed as CE6 devices may be CE10 rejects.<br />
<br />
* Samsung DDR2 '''SDRAM'''<br />
:Samples are stored as 3 bytes (16bit sample plus 8 bit repetition count)<br />
:A 'transfer packet' for upload is 16 bytes = 5 compressed samples plus a sequence number byte<br />
:Burst read/write for this SDRAM is up to 16 bytes, which matches the transfer packet size and is likely used for all SDRAM read/writes.<br />
<br />
<br />
Datasheets<br />
<br />
U15 [http://www.ti.com/lit/ds/symlink/tps60403.pdf TPS60403] Charge pump voltage inverter<br />
<br />
<br />
== Photos ==<br />
<br />
<gallery><br />
File:Kingst la2016 package contents.jpg|<small>Package contents</small><br />
File:Kingst la2016 paper.jpg|<small>Paper</small><br />
File:Kingst la2016 device top.jpg|<small>Device, top</small><br />
File:Kingst la2016 device bottom.jpg|<small>Device, bottom</small><br />
File:Kingst la2016 pcb top.jpg|<small>PCB, top</small><br />
File:Kingst la2016 pcb bottom.jpg|<small>PCB, bottom</small><br />
File:Kingst la2016 cypress fx2.jpg|<small>Cypress FX2</small><br />
File:Kingst la2016 altera cyclone4 ep4ce6f17c8n.jpg|<small>Altera Cyclone IV</small><br />
File:Kingst la2016 samsung k4t1g164qg.jpg|<small>Samsung K4T1G164QG</small><br />
File:Kingst la2016 atmel 24c02n.jpg|<small>Atmel 24C02N</small><br />
File:Kingst la2016 unmarked ic.jpg|<small>Unmarked IC</small><br />
File:Kingst la2016 fpni.jpg|<small>PFNI</small><br />
</gallery><br />
<br />
== Firmware ==<br />
<br />
'''TODO This extraction script needs updated'''<br />
<br />
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/kingst-la sigrok-fwextract-kingst-la2016] script from the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree sigrok-util] repo and place them in one of the usual [[Firmware#Where_to_put_the_firmware_files|places where libsigrok expects firmware files]]:<br />
<br />
<small><br />
$ '''./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS'''<br />
saved 180224 bytes to kingst-la2016a-fpga.bitstream<br />
saved 5350 bytes to kingst-la-01a1.fw<br />
saved 5430 bytes to kingst-la-01a2.fw<br />
saved 5718 bytes to kingst-la-01a3.fw<br />
saved 142412 bytes to kingst-la-01a4.fw<br />
saved 5452 bytes to kingst-la-03a1.fw<br />
</small><br />
<br />
== Resources ==<br />
<br />
* [http://www.qdkingst.com/en/download Vendor software]<br />
* [http://www.qdkingst.com/download/vis_ug_en User guide]<br />
<br />
[[Category:Device]]<br />
[[Category:Logic analyzer]]<br />
[[Category:In progress]]</div>Planet9https://sigrok.org/w/index.php?title=Kingst_LA2016&diff=16057Kingst LA20162021-03-05T12:53:01Z<p>Planet9: </p>
<hr />
<div>{{Infobox logic analyzer<br />
| image = [[File:Kingst la2016 mugshot.png|180px]]<br />
| name = Kingst LA2016<br />
| status = supported<br />
| source_code_dir = kingst-la2016<br />
| channels = 16<br />
| samplerate = 200MHz<br />
| samplerate_state = &mdash;<br />
| triggers = high/low level, on one channel rising/falling edge<br />
| voltages = -50V &mdash; 50V<br />
| threshold = configurable:<br />-4V&mdash;4V, min step 0.01V<br />
| memory = 128MByte DDR2 SDRAM<br />
| compression = yes<br />
| website = [http://www.qdkingst.com/en/products qdkingst.com]<br />
}}<br />
<br />
The '''Kingst LA2016''' is a USB-based, 16-channel logic analyzer with 200MHz sampling rate.<br />
<br />
The vendor is "Qingdao Kingst Electronics Co., Ltd." according to the user guide, and the vendor software can be downloaded from a website with "kingst" in the name. The device housing reads "Jiankun" however, not "Kingst".<br />
<br />
See [[Kingst LA2016/Info]] for more details (such as '''lsusb -v''' output) about the device.<br />
<br />
== Hardware ==<br />
<br />
The IC marked PFNI is a http://www.ti.com/lit/ds/symlink/tps60403.pdf<br />
<br />
== Photos ==<br />
<br />
<gallery><br />
File:Kingst la2016 package contents.jpg|<small>Package contents</small><br />
File:Kingst la2016 paper.jpg|<small>Paper</small><br />
File:Kingst la2016 device top.jpg|<small>Device, top</small><br />
File:Kingst la2016 device bottom.jpg|<small>Device, bottom</small><br />
File:Kingst la2016 pcb top.jpg|<small>PCB, top</small><br />
File:Kingst la2016 pcb bottom.jpg|<small>PCB, bottom</small><br />
File:Kingst la2016 cypress fx2.jpg|<small>Cypress FX2</small><br />
File:Kingst la2016 altera cyclone4 ep4ce6f17c8n.jpg|<small>Altera Cyclone IV</small><br />
File:Kingst la2016 samsung k4t1g164qg.jpg|<small>Samsung K4T1G164QG</small><br />
File:Kingst la2016 atmel 24c02n.jpg|<small>Atmel 24C02N</small><br />
File:Kingst la2016 unmarked ic.jpg|<small>Unmarked IC</small><br />
File:Kingst la2016 fpni.jpg|<small>PFNI</small><br />
</gallery><br />
<br />
== Firmware ==<br />
<br />
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/kingst-la sigrok-fwextract-kingst-la2016] script from the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree sigrok-util] repo and place them in one of the usual [[Firmware#Where_to_put_the_firmware_files|places where libsigrok expects firmware files]]:<br />
<br />
<small><br />
$ '''./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS'''<br />
saved 180224 bytes to kingst-la2016a-fpga.bitstream<br />
saved 5350 bytes to kingst-la-01a1.fw<br />
saved 5430 bytes to kingst-la-01a2.fw<br />
saved 5718 bytes to kingst-la-01a3.fw<br />
saved 142412 bytes to kingst-la-01a4.fw<br />
saved 5452 bytes to kingst-la-03a1.fw<br />
</small><br />
<br />
== Resources ==<br />
<br />
* [http://www.qdkingst.com/en/download Vendor software]<br />
* [http://www.qdkingst.com/download/vis_ug_en User guide]<br />
<br />
[[Category:Device]]<br />
[[Category:Logic analyzer]]<br />
[[Category:Supported]]</div>Planet9https://sigrok.org/w/index.php?title=Kingst_LA2016&diff=16056Kingst LA20162021-03-05T12:52:28Z<p>Planet9: </p>
<hr />
<div>{{Infobox logic analyzer<br />
| image = [[File:Kingst la2016 mugshot.png|180px]]<br />
| name = Kingst LA2016<br />
| status = in progress<br />
| source_code_dir = kingst-la2016<br />
| channels = 16<br />
| samplerate = 200MHz max.<br />
| samplerate_state = State analysis not supported<br />
| triggers = Level (multiple channels)<br/>Edge (one channel)<br />
| voltages = -50V &mdash; 50V<br />
| threshold = Configurable:<br/>-4V&mdash;4V, min step 0.01V<br />
| memory = 128MByte DDR2 SDRAM<br/>40M&mdash;10G samples<br />
| compression = Yes<br />
| website = [http://www.qdkingst.com/en qdkingst.com]<br />
}}<br />
<br />
'''5th March 2021:'''<br/><br />
'''This device was previously marked as supported, however, some users are reporting issues with this device and we are working on some driver changes.'''<br />
<br />
<br />
The '''Kingst LA2016''' is a USB-based, 16-channel logic analyser with 200MHz maximum sampling rate.<br />
The current vendor is "Qingdao Kingst Electronics Co., Ltd." but older models appear to be branded "Jiankun" rather than "Kingst".<br />
The vendor software can be freely downloaded from their [http://www.qdkingst.com/en/products website].<br />
<br />
<br />
== Hardware ==<br />
This logic analyser has been on the market since around 2012 and there are a few different revisions of it.<br />
This [[Media:Kingst_LA2016_LA1016_Schematic.zip|schematic]] has been reverse engineered from<br />
a unit purchased in 2020 containing a PCB marked as v1.3.0. <br />
The circuitry of early issue PCBs is similar but may have different voltage regulators, different input<br />
channel routing to the FPGA and no input threshold adjustment.<br />
<br />
The LA1016 uses identical hardware with a different FPGA bitstream which limits the sample rate to 100MHz maximum.<br />
<br />
All of these devices use the same firmware for the FX2LP MCU but there are four different FPGA bitstreams.<br />
i.e. LA1016 & LA2016 bitstreams and the older versions of these (to swap some of the input channels).<br />
Once the FX2LP firmware has been loaded, a 'magic number' in the EEPROM is used to identify the different<br />
models and thus allow the correct FPGA bitstream to be loaded.<br />
<br />
Note that the LA1016 cannot be boosted to 200MHz by<br />
changing the 'magic number' or the FPGA bitstream because of device U10 which<br />
is used by the FPGA to authenticate the bitstream. It is also used by the OEM software to authenticate<br />
the logic analyser as genuine 'Kingst'. U10 does not impact Sigrok support in any way and we don't need<br />
to communicate with it.<br />
<br />
<br />
Main components and their function:<br />
<br />
* '''I2C EEPROM''': 2Kbit [http://www.atmel.com/devices/AT24C02B.aspx Atmel 24C02B] (markings: "ATMEL317 24C02BN SU27 D") ([http://www.atmel.com/Images/doc5126.pdf datasheet])<br />
<br />
<br />
<br />
* Cypress FX2LP MCU<br />
<br />
See [[Kingst LA2016/Info]] for '''lsusb -v''' endpoint information.<br />
<br />
* Atmel AT24C02 2Kbit EEPROM<br />
<br />
<br />
* Altera EP4CE6 FPGA<br />
<br />
<br />
* Samsung DDR2 SDRAM<br />
<br />
<br />
<br />
Datasheets<br />
<br />
U15 [http://www.ti.com/lit/ds/symlink/tps60403.pdf TPS60403] Charge pump voltage inverter<br />
<br />
The IC marked PFNI is a http://www.ti.com/lit/ds/symlink/tps60403.pdf<br />
<br />
== Photos ==<br />
<br />
<gallery><br />
File:Kingst la2016 package contents.jpg|<small>Package contents</small><br />
File:Kingst la2016 paper.jpg|<small>Paper</small><br />
File:Kingst la2016 device top.jpg|<small>Device, top</small><br />
File:Kingst la2016 device bottom.jpg|<small>Device, bottom</small><br />
File:Kingst la2016 pcb top.jpg|<small>PCB, top</small><br />
File:Kingst la2016 pcb bottom.jpg|<small>PCB, bottom</small><br />
File:Kingst la2016 cypress fx2.jpg|<small>Cypress FX2</small><br />
File:Kingst la2016 altera cyclone4 ep4ce6f17c8n.jpg|<small>Altera Cyclone IV</small><br />
File:Kingst la2016 samsung k4t1g164qg.jpg|<small>Samsung K4T1G164QG</small><br />
File:Kingst la2016 atmel 24c02n.jpg|<small>Atmel 24C02N</small><br />
File:Kingst la2016 unmarked ic.jpg|<small>Unmarked IC</small><br />
File:Kingst la2016 fpni.jpg|<small>PFNI</small><br />
</gallery><br />
<br />
== Firmware ==<br />
<br />
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/kingst-la sigrok-fwextract-kingst-la2016] script from the [https://sigrok.org/gitweb/?p=sigrok-util.git;a=tree sigrok-util] repo and place them in one of the usual [[Firmware#Where_to_put_the_firmware_files|places where libsigrok expects firmware files]]:<br />
<br />
<small><br />
$ '''./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS'''<br />
saved 180224 bytes to kingst-la2016a-fpga.bitstream<br />
saved 5350 bytes to kingst-la-01a1.fw<br />
saved 5430 bytes to kingst-la-01a2.fw<br />
saved 5718 bytes to kingst-la-01a3.fw<br />
saved 142412 bytes to kingst-la-01a4.fw<br />
saved 5452 bytes to kingst-la-03a1.fw<br />
</small><br />
<br />
== Resources ==<br />
<br />
* [http://www.qdkingst.com/en/download Vendor software]<br />
* [http://www.qdkingst.com/download/vis_ug_en User guide]<br />
<br />
[[Category:Device]]<br />
[[Category:Logic analyzer]]<br />
[[Category:In progress]]</div>Planet9https://sigrok.org/w/index.php?title=File:Kingst_LA2016_LA1016_Schematic.zip&diff=16055File:Kingst LA2016 LA1016 Schematic.zip2021-03-05T11:17:13Z<p>Planet9: Electrical schematic of LA1016/LA2016 PCB v1.3.0</p>
<hr />
<div>== Summary ==<br />
Electrical schematic of LA1016/LA2016 PCB v1.3.0<br />
== Licensing ==<br />
{{PD}}</div>Planet9