sigrok - User contributions [en]

Saleae Logic16

2013-08-08T15:48:53Z

Jani: Added most likely part for I2C configuration EEPROM

{{Infobox logic analyzer
| image = [[File:Saleae Logic16.jpg|180px]]
| name = Saleae Logic16
| status = in progress
| source_code_dir =
| channels = 2/4/8/16
| samplerate = 100/50/25/12.5MHz
| samplerate_state = —
| triggers = none (SW-only)
| voltages = -0.9V — 6V
| threshold = configurable: for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V for 5V systems: VIH=3.6V, VIL=1.4V
| memory = none
| compression = yes
| website = [http://www.saleae.com/logic16/ saleae.com]
}}

The '''Saleae Logic16''' is a USB-based, 16-channel logic analyzer with 100/50/25/12.5MHz sampling rate (at 2/4/8/16 enabled channels).

The case requires a '''Torx T5''' screwdriver to open.

See [[Saleae Logic16/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

See [[Saleae Logic]] for the predecessor product of the Saleae Logic16.

== Hardware ==

* '''FPGA''': [http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/spartan-3a.html Xilinx Spartan-3A XC3S200A], 200K gates ([http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf datasheeet])
* '''USB interface chip''': [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A-56PVXC (FX2LP)] ([http://www.cypress.com/?docID=34060 datasheet])
* '''Ultralow capacitance ESD protection''': 4x [http://www.st.com/web/catalog/sense_power/FM114/CL1137/SC1490/PF109008 ST DVIULC6-4SC6] ([http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00065974.pdf datasheet])
* '''I2C EEPROM''': Marking: "B2TH". [http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en010774 Microchip 24AA02] has markings "B2??" in SOT-23 case ([http://ww1.microchip.com/downloads/en/DeviceDoc/21709J.pdf datasheet])
* '''Voltage regulators''': 2x [http://www.semtech.com/power-management/switching-regulators/sc189 Semtech SC189 Step Down Switching Regulator]. "189Z" for 3.3V and "189C" for 1.2V. ([http://www.semtech.com/images/datasheet/sc189.pdf datasheet])
* '''?''': 2x Unknown 3-pin IC. Markings: "72Y7".

'''Pinouts and connections:'''

'''JTAG header (FPGA):'''

The '''J3''' pin header is a JTAG connector wired to the FPGA. The pins are (from left to right, the right-most pin, pin number 1, is square):

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!5
!4
!3
!2
!1

|-
| GND
| TMS
| TCK
| TDO
| TDI

|}

'''Testpoints:'''

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!T1
!T2
!T3

|-
| 1.2V
| 3.3V
| GND (FX2)

|}

'''Cypress FX2:'''


{{chip_56pin
| 1=(FPGA 15, IO_L05P_3) PD5
| 2=(FPGA 13, IO_L04N_3) PD6
| 3=(FPGA 10, IO_L03N_3) PD7
| 4=GND
| 5=(FPGA 90, IO_0) CLKOUT
| 6=VCC
| 7=GND
| 8=(FPGA 3, IO_L01P_3) RDY0/*SLRD
| 9=(FPGA 3, IO_L01P_3) RDY1/*SLWR
| 10=AVCC
| 11=(24MHz crystal) XTALOUT
| 12=(24MHz crystal) XTALIN
| 13=AGND
| 14=AVCC

| 15=(USB D+) DPLUS
| 16=(USB D-) DMINUS
| 17=AGND
| 18=VCC
| 19=GND
| 20=(FPGA 84, IO_L02N_0) *IFCLK
| 21=RESERVED
| 22=(EEPROM SCL) SCL
| 23=(EEPROM SDA) SDA
| 24=VCC
| 25=(FPGA 40, IO_L08P_2) PB0
| 26=(FPGA 78, IO_L01N_0) PB1
| 27=(FPGA 77, IO_L01P_0) PB2
| 28=(FPGA 50, IO_L11P_2) PB3

| 29=PB4 (FPGA 46, MOSI)
| 30=PB5 (FPGA 41, IO_L08N_2)
| 31=PB6 (FPGA 37, IO_L07N_2)
| 32=PB7 (FPGA 93, IO_L05P_0)
| 33=GND
| 34=VCC
| 35=GND
| 36=CTL0 (FPGA 94, IO_L05N_0)
| 37=CTL1 (FPGA 97, IP_0)
| 38=CTL2 (FPGA 100, PROG_B)
| 39=VCC
| 40=PA0 (FPGA 54, DONE)
| 41=PA1 (FPGA 48, INIT_B)
| 42=PA2 (FPGA 53, CCLK)

| 43=PA3 (FPGA 51, MISO)
| 44=PA4 (FPGA 98, IO_L06P_0)
| 45=PA5 (FPGA 85, IO_L03P_0)
| 46=PA6 (FPGA 30, IO_L04P_2)
| 47=PA7 (FPGA 9, IO_L03P_3)
| 48=GND
| 49=RESET# (3.3V via D2 (diode?))
| 50=VCC
| 51=*WAKEUP (3.3V)
| 52=PD0 (FPGA 6, IO_L02N_3)
| 53=PD1 (FPGA 4, IO_L01N_3)
| 54=PD2 (FPGA 5, IO_L02P_3)
| 55=PD3 (FPGA 44, IO_L09N_2)
| 56=PD4 (FPGA 12, IO_L04P_3)

}}


== Photos ==

<gallery>
File:Saleae Logic16.jpg|Device, front
File:Saleae Logic16 bottom.jpg|Device, bottom
File:Saleae Logic16 PCB top.jpg|PCB, top
File:Saleae Logic16 PCB bottom.jpg|PCB, bottom
File:Saleae logic16 xilinx xc3s200a.jpg|Xilinx XC3S200A
File:Saleae logic16 cypress fx2lp.jpg|Cypress FX2LP
File:Saleae logic16 eeprom b2th.jpg|I2C EEPROM
File:Saleae logic16 dl46.jpg|ST DVIULC6-4SC6
File:Saleae logic16 189z 189c.jpg|Voltage regulators
File:Saleae logic16 72y7.jpg|72Y7

</gallery>

== Firmware ==

The firmware for the FX2LP is embedded in the vendor application as a set of Intel HEX lines. Each line is uploaded individually with a separate control transfer. The firmware currently occupies the address range [0x0000-0x145d], but is uploaded out of order. TODO: Make a tool to extract the firmware from the application binary.

See [[Saleae Logic16/Firmware]] for more details on the vendor firmware.

== Protocol ==

'''Sample format''':

The samples (as received via USB) for the enabled probes (3, 6, 9, or 16) are organized as follows:

'''0xLL 0xLL 0xMM 0xMM 0xNN 0xNN 0xPP 0xPP 0xQQ 0xQQ 0xRR 0xRR ...'''

In the above example, 3 probes are enabled. For each probe there are 2 bytes / 16 bits (e.g. 0xLL 0xLL for probe 0), then the next probe's data is received (0xMM 0xMM for probe 1), then 0xNN 0xNN for probe 2. When 2 bytes have been received for all enabled probes, the process restarts with probe 0 again.

The 16 bits of data per probe seem to contain the pin state of the respective probe (1: high, 0: low) at 16 different sampling points/times (which ones depends on the samplerate).

'''Configuration''':

Endpoint 1 is used for configuration of the analyzer. The transfers are "encrypted" using a simple series of additions and XORs. Two kinds of transfers are used; a 3 byte out transfer starting with 0x81 followed by a 1 byte in transfer, and a 4 byte out transfer starting with 0x80. It's quite plausible that these provide raw read/write access to memory locations.

{| class="wikitable"
!colspan="2"|Channel number configuration
|-
|3 channels
|<tt>0x80 0x01 0x02 0x07 0x80 0x01 0x03 0x00</tt>
|-
|6 channels
|<tt>0x80 0x01 0x02 0x3f 0x80 0x01 0x03 0x00</tt>
|-
|9 channels
|<tt>0x80 0x01 0x02 0xff 0x80 0x01 0x03 0x01</tt>
|-
|16 channels
|<tt>0x80 0x01 0x02 0xff 0x80 0x01 0x03 0xff</tt>
|}

{| class="wikitable"
!colspan="2"|Sampling frequency
|-
|500 kHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0xc7</tt>
|-
|1 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x63</tt>
|-
|2 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x31</tt>
|-
|4 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x18</tt>
|-
|5 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x13</tt>
|-
|8 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x13</tt>
|-
|10 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x09</tt>
|-
|12.5 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x07</tt>
|-
|16 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x09</tt>
|-
|25 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x03</tt>
|-
|32 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x04</tt>
|-
|40 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x03</tt>
|-
|50 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x01</tt>
|-
|80 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x01</tt>
|-
|100 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x00</tt>
|}

== Resources ==

* [http://downloads.saleae.com/Logic+Guide.pdf Manual]
* [http://www.saleae.com/downloads Vendor software]
* [http://community.saleae.com/ SDKs]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:In progress]]

Saleae Logic16

2013-08-08T06:51:06Z

Jani: Changed JTAG connector J3 pin numbering, square pin is pin number 1

{{Infobox logic analyzer
| image = [[File:Saleae Logic16.jpg|180px]]
| name = Saleae Logic16
| status = planned
| source_code_dir =
| channels = 2/4/8/16
| samplerate = 100/50/25/12.5MHz
| samplerate_state = —
| triggers = none (SW-only)
| voltages = -0.9V — 6V
| threshold = configurable: for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V for 5V systems: VIH=3.6V, VIL=1.4V
| memory = none
| compression = yes
| website = [http://www.saleae.com/logic16/ saleae.com]
}}

The '''Saleae Logic16''' is a USB-based, 16-channel logic analyzer with 100/50/25/12.5MHz sampling rate (at 2/4/8/16 enabled channels).

The case requires a '''Torx T5''' screwdriver to open.

See [[Saleae Logic16/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

See [[Saleae Logic]] for the predecessor product of the Saleae Logic16.

== Hardware ==

* '''FPGA''': [http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/spartan-3a.html Xilinx Spartan-3A XC3S200A], 200K gates ([http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf datasheeet])
* '''USB interface chip''': [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A-56PVXC (FX2LP)] ([http://www.cypress.com/?docID=34060 datasheet])
* '''Ultralow capacitance ESD protection''': 4x [http://www.st.com/web/catalog/sense_power/FM114/CL1137/SC1490/PF109008 ST DVIULC6-4SC6] ([http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00065974.pdf datasheet])
* '''I2C EEPROM''': Unknown. Marking: "B2TH".
* '''Voltage regulators''': 2x [http://www.semtech.com/power-management/switching-regulators/sc189 Semtech SC189 Step Down Switching Regulator]. "189Z" for 3.3V and "189C" for 1.2V. ([http://www.semtech.com/images/datasheet/sc189.pdf datasheet])
* '''?''': 2x Unknown 3-pin IC. Markings: "72Y7".

'''Pinouts and connections:'''

'''JTAG header (FPGA):'''

The '''J3''' pin header is a JTAG connector wired to the FPGA. The pins are (from left to right, the right-most pin, pin number 1, is square):

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!5
!4
!3
!2
!1

|-
| GND
| TMS
| TCK
| TDO
| TDI

|}

'''Testpoints:'''

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!T1
!T2
!T3

|-
| 1.2V
| 3.3V
| GND (FX2)

|}

'''Cypress FX2:'''


{{chip_56pin
| 1=(FPGA 15, IO_L05P_3) PD5
| 2=(FPGA 13, IO_L04N_3) PD6
| 3=(FPGA 10, IO_L03N_3) PD7
| 4=GND
| 5=(FPGA 90, IO_0) CLKOUT
| 6=VCC
| 7=GND
| 8=(FPGA 3, IO_L01P_3) RDY0/*SLRD
| 9=(FPGA 3, IO_L01P_3) RDY1/*SLWR
| 10=AVCC
| 11=(24MHz crystal) XTALOUT
| 12=(24MHz crystal) XTALIN
| 13=AGND
| 14=AVCC

| 15=(USB D+) DPLUS
| 16=(USB D-) DMINUS
| 17=AGND
| 18=VCC
| 19=GND
| 20=(FPGA 84, IO_L02N_0) *IFCLK
| 21=RESERVED
| 22=(EEPROM SCL) SCL
| 23=(EEPROM SDA) SDA
| 24=VCC
| 25=(FPGA 40, IO_L08P_2) PB0
| 26=(FPGA 78, IO_L01N_0) PB1
| 27=(FPGA 77, IO_L01P_0) PB2
| 28=(FPGA 50, IO_L11P_2) PB3

| 29=PB4 (FPGA 46, MOSI)
| 30=PB5 (FPGA 41, IO_L08N_2)
| 31=PB6 (FPGA 37, IO_L07N_2)
| 32=PB7 (FPGA 93, IO_L05P_0)
| 33=GND
| 34=VCC
| 35=GND
| 36=CTL0 (FPGA 94, IO_L05N_0)
| 37=CTL1 (FPGA 97, IP_0)
| 38=CTL2 (FPGA 100, PROG_B)
| 39=VCC
| 40=PA0 (FPGA 54, DONE)
| 41=PA1 (FPGA 48, INIT_B)
| 42=PA2 (FPGA 53, CCLK)

| 43=PA3 (FPGA 51, MISO)
| 44=PA4 (FPGA 98, IO_L06P_0)
| 45=PA5 (FPGA 85, IO_L03P_0)
| 46=PA6 (FPGA 30, IO_L04P_2)
| 47=PA7 (FPGA 9, IO_L03P_3)
| 48=GND
| 49=RESET# (3.3V via D2 (diode?))
| 50=VCC
| 51=*WAKEUP (3.3V)
| 52=PD0 (FPGA 6, IO_L02N_3)
| 53=PD1 (FPGA 4, IO_L01N_3)
| 54=PD2 (FPGA 5, IO_L02P_3)
| 55=PD3 (FPGA 44, IO_L09N_2)
| 56=PD4 (FPGA 12, IO_L04P_3)

}}


== Photos ==

<gallery>
File:Saleae Logic16.jpg|Device, front
File:Saleae Logic16 bottom.jpg|Device, bottom
File:Saleae Logic16 PCB top.jpg|PCB, top
File:Saleae Logic16 PCB bottom.jpg|PCB, bottom
File:Saleae logic16 xilinx xc3s200a.jpg|Xilinx XC3S200A
File:Saleae logic16 cypress fx2lp.jpg|Cypress FX2LP
File:Saleae logic16 eeprom b2th.jpg|I2C EEPROM
File:Saleae logic16 dl46.jpg|ST DVIULC6-4SC6
File:Saleae logic16 189z 189c.jpg|Voltage regulators
File:Saleae logic16 72y7.jpg|72Y7

</gallery>

== Firmware ==

The firmware for the FX2LP is embedded in the vendor application as a set of Intel HEX lines. Each line is uploaded individually with a separate control transfer. The firmware currently occupies the address range [0x0000-0x145d], but is uploaded out of order. TODO: Make a tool to extract the firmware from the application binary.

See [[Saleae Logic16/Firmware]] for more details on the vendor firmware.

== Protocol ==

'''Sample format''':

The samples (as received via USB) for the enabled probes (3, 6, 9, or 16) are organized as follows:

'''0xLL 0xLL 0xMM 0xMM 0xNN 0xNN 0xPP 0xPP 0xQQ 0xQQ 0xRR 0xRR ...'''

In the above example, 3 probes are enabled. For each probe there are 2 bytes / 16 bits (e.g. 0xLL 0xLL for probe 0), then the next probe's data is received (0xMM 0xMM for probe 1), then 0xNN 0xNN for probe 2. When 2 bytes have been received for all enabled probes, the process restarts with probe 0 again.

The 16 bits of data per probe seem to contain the pin state of the respective probe (1: high, 0: low) at 16 different sampling points/times (which ones depends on the samplerate).

'''Configuration''':

Endpoint 1 is used for configuration of the analyzer. The transfers are "encrypted" using a simple series of additions and XORs. Two kinds of transfers are used; a 3 byte out transfer starting with 0x81 followed by a 1 byte in transfer, and a 4 byte out transfer starting with 0x80. It's quite plausible that these provide raw read/write access to memory locations.

{| class="wikitable"
!colspan="2"|Channel number configuration
|-
|3 channels
|<tt>0x80 0x01 0x02 0x07 0x80 0x01 0x03 0x00</tt>
|-
|6 channels
|<tt>0x80 0x01 0x02 0x3f 0x80 0x01 0x03 0x00</tt>
|-
|9 channels
|<tt>0x80 0x01 0x02 0xff 0x80 0x01 0x03 0x01</tt>
|-
|16 channels
|<tt>0x80 0x01 0x02 0xff 0x80 0x01 0x03 0xff</tt>
|}

{| class="wikitable"
!colspan="2"|Sampling frequency
|-
|500 kHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0xc7</tt>
|-
|1 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x63</tt>
|-
|2 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x31</tt>
|-
|4 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x18</tt>
|-
|5 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x13</tt>
|-
|8 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x13</tt>
|-
|10 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x09</tt>
|-
|12.5 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x07</tt>
|-
|16 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x09</tt>
|-
|25 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x03</tt>
|-
|32 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x04</tt>
|-
|40 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x03</tt>
|-
|50 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x01</tt>
|-
|80 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x01</tt>
|-
|100 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x00</tt>
|}

== Resources ==

* [http://downloads.saleae.com/Logic+Guide.pdf Manual]
* [http://www.saleae.com/downloads Vendor software]
* [http://community.saleae.com/ SDKs]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Planned]]

Saleae Logic16

2013-08-08T06:35:52Z

Jani: Added voltage regulator information

{{Infobox logic analyzer
| image = [[File:Saleae Logic16.jpg|180px]]
| name = Saleae Logic16
| status = planned
| source_code_dir =
| channels = 2/4/8/16
| samplerate = 100/50/25/12.5MHz
| samplerate_state = —
| triggers = none (SW-only)
| voltages = -0.9V — 6V
| threshold = configurable: for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V for 5V systems: VIH=3.6V, VIL=1.4V
| memory = none
| compression = yes
| website = [http://www.saleae.com/logic16/ saleae.com]
}}

The '''Saleae Logic16''' is a USB-based, 16-channel logic analyzer with 100/50/25/12.5MHz sampling rate (at 2/4/8/16 enabled channels).

The case requires a '''Torx T5''' screwdriver to open.

See [[Saleae Logic16/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

See [[Saleae Logic]] for the predecessor product of the Saleae Logic16.

== Hardware ==

* '''FPGA''': [http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/spartan-3a.html Xilinx Spartan-3A XC3S200A], 200K gates ([http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf datasheeet])
* '''USB interface chip''': [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A-56PVXC (FX2LP)] ([http://www.cypress.com/?docID=34060 datasheet])
* '''Ultralow capacitance ESD protection''': 4x [http://www.st.com/web/catalog/sense_power/FM114/CL1137/SC1490/PF109008 ST DVIULC6-4SC6] ([http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00065974.pdf datasheet])
* '''I2C EEPROM''': Unknown. Marking: "B2TH".
* '''Voltage regulators''': 2x [http://www.semtech.com/power-management/switching-regulators/sc189 Semtech SC189 Step Down Switching Regulator]. "189Z" for 3.3V and "189C" for 1.2V. ([http://www.semtech.com/images/datasheet/sc189.pdf datasheet])
* '''?''': 2x Unknown 3-pin IC. Markings: "72Y7".

'''Pinouts and connections:'''

'''JTAG header (FPGA):'''

The '''J3''' pin header is a JTAG connector wired to the FPGA. The pins are (from left to right, the right-most pin is square):

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!1
!2
!3
!4
!5

|-
| GND
| TMS
| TCK
| TDO
| TDI

|}

'''Testpoints:'''

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!T1
!T2
!T3

|-
| 1.2V
| 3.3V
| GND (FX2)

|}

'''Cypress FX2:'''


{{chip_56pin
| 1=(FPGA 15, IO_L05P_3) PD5
| 2=(FPGA 13, IO_L04N_3) PD6
| 3=(FPGA 10, IO_L03N_3) PD7
| 4=GND
| 5=(FPGA 90, IO_0) CLKOUT
| 6=VCC
| 7=GND
| 8=(FPGA 3, IO_L01P_3) RDY0/*SLRD
| 9=(FPGA 3, IO_L01P_3) RDY1/*SLWR
| 10=AVCC
| 11=(24MHz crystal) XTALOUT
| 12=(24MHz crystal) XTALIN
| 13=AGND
| 14=AVCC

| 15=(USB D+) DPLUS
| 16=(USB D-) DMINUS
| 17=AGND
| 18=VCC
| 19=GND
| 20=(FPGA 84, IO_L02N_0) *IFCLK
| 21=RESERVED
| 22=(EEPROM SCL) SCL
| 23=(EEPROM SDA) SDA
| 24=VCC
| 25=(FPGA 40, IO_L08P_2) PB0
| 26=(FPGA 78, IO_L01N_0) PB1
| 27=(FPGA 77, IO_L01P_0) PB2
| 28=(FPGA 50, IO_L11P_2) PB3

| 29=PB4 (FPGA 46, MOSI)
| 30=PB5 (FPGA 41, IO_L08N_2)
| 31=PB6 (FPGA 37, IO_L07N_2)
| 32=PB7 (FPGA 93, IO_L05P_0)
| 33=GND
| 34=VCC
| 35=GND
| 36=CTL0 (FPGA 94, IO_L05N_0)
| 37=CTL1 (FPGA 97, IP_0)
| 38=CTL2 (FPGA 100, PROG_B)
| 39=VCC
| 40=PA0 (FPGA 54, DONE)
| 41=PA1 (FPGA 48, INIT_B)
| 42=PA2 (FPGA 53, CCLK)

| 43=PA3 (FPGA 51, MISO)
| 44=PA4 (FPGA 98, IO_L06P_0)
| 45=PA5 (FPGA 85, IO_L03P_0)
| 46=PA6 (FPGA 30, IO_L04P_2)
| 47=PA7 (FPGA 9, IO_L03P_3)
| 48=GND
| 49=RESET# (3.3V via D2 (diode?))
| 50=VCC
| 51=*WAKEUP (3.3V)
| 52=PD0 (FPGA 6, IO_L02N_3)
| 53=PD1 (FPGA 4, IO_L01N_3)
| 54=PD2 (FPGA 5, IO_L02P_3)
| 55=PD3 (FPGA 44, IO_L09N_2)
| 56=PD4 (FPGA 12, IO_L04P_3)

}}


== Photos ==

<gallery>
File:Saleae Logic16.jpg|Device, front
File:Saleae Logic16 bottom.jpg|Device, bottom
File:Saleae Logic16 PCB top.jpg|PCB, top
File:Saleae Logic16 PCB bottom.jpg|PCB, bottom
File:Saleae logic16 xilinx xc3s200a.jpg|Xilinx XC3S200A
File:Saleae logic16 cypress fx2lp.jpg|Cypress FX2LP
File:Saleae logic16 eeprom b2th.jpg|I2C EEPROM
File:Saleae logic16 dl46.jpg|ST DVIULC6-4SC6
File:Saleae logic16 189z 189c.jpg|Voltage regulators
File:Saleae logic16 72y7.jpg|72Y7

</gallery>

== Firmware ==

The firmware for the FX2LP is embedded in the vendor application as a set of Intel HEX lines. Each line is uploaded individually with a separate control transfer. The firmware currently occupies the address range [0x0000-0x145d], but is uploaded out of order. TODO: Make a tool to extract the firmware from the application binary.

See [[Saleae Logic16/Firmware]] for more details on the vendor firmware.

== Protocol ==

'''Sample format''':

The samples (as received via USB) for the enabled probes (3, 6, 9, or 16) are organized as follows:

'''0xLL 0xLL 0xMM 0xMM 0xNN 0xNN 0xPP 0xPP 0xQQ 0xQQ 0xRR 0xRR ...'''

In the above example, 3 probes are enabled. For each probe there are 2 bytes / 16 bits (e.g. 0xLL 0xLL for probe 0), then the next probe's data is received (0xMM 0xMM for probe 1), then 0xNN 0xNN for probe 2. When 2 bytes have been received for all enabled probes, the process restarts with probe 0 again.

The 16 bits of data per probe seem to contain the pin state of the respective probe (1: high, 0: low) at 16 different sampling points/times (which ones depends on the samplerate).

'''Configuration''':

Endpoint 1 is used for configuration of the analyzer. The transfers are "encrypted" using a simple series of additions and XORs. Two kinds of transfers are used; a 3 byte out transfer starting with 0x81 followed by a 1 byte in transfer, and a 4 byte out transfer starting with 0x80. It's quite plausible that these provide raw read/write access to memory locations.

{| class="wikitable"
!colspan="2"|Channel number configuration
|-
|3 channels
|<tt>0x80 0x01 0x02 0x07 0x80 0x01 0x03 0x00</tt>
|-
|6 channels
|<tt>0x80 0x01 0x02 0x3f 0x80 0x01 0x03 0x00</tt>
|-
|9 channels
|<tt>0x80 0x01 0x02 0xff 0x80 0x01 0x03 0x01</tt>
|-
|16 channels
|<tt>0x80 0x01 0x02 0xff 0x80 0x01 0x03 0xff</tt>
|}

{| class="wikitable"
!colspan="2"|Sampling frequency
|-
|500 kHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0xc7</tt>
|-
|1 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x63</tt>
|-
|2 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x31</tt>
|-
|4 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x18</tt>
|-
|5 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x13</tt>
|-
|8 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x13</tt>
|-
|10 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x09</tt>
|-
|12.5 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x07</tt>
|-
|16 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x09</tt>
|-
|25 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x03</tt>
|-
|32 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x04</tt>
|-
|40 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x03</tt>
|-
|50 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x01</tt>
|-
|80 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x01</tt>
|-
|100 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x00</tt>
|}

== Resources ==

* [http://downloads.saleae.com/Logic+Guide.pdf Manual]
* [http://www.saleae.com/downloads Vendor software]
* [http://community.saleae.com/ SDKs]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Planned]]