https://sigrok.org/w/api.php?action=feedcontributions&feedformat=atom&user=Gussigrok - User contributions [en]2026-05-22T21:45:40ZUser contributionsMediaWiki 1.37.1https://sigrok.org/w/index.php?title=Main_Page&diff=2084Main Page2012-06-01T14:31:28Z<p>Gus: </p>
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The '''sigrok''' project aims at creating a '''portable, cross-platform, Free/Libre/Open-Source signal analysis software suite''' that supports various '''logic analyzers, oscilloscopes, multimeters, data loggers''', and more. It is licensed under the terms of the '''GNU GPL'''. Design goals and features include:<br />
<small><br />
* '''Broad hardware support'''. Supports many different logic analyzers, oscilloscopes, multimeters, data loggers etc. from various vendors.<br />
* '''Cross-platform'''. Works on [[Linux]], [[Mac OS X]], [[Windows]], and [[FreeBSD]] (and on x86, ARM, Sparc, PowerPC, ...).<br />
* '''Scriptable protocol decoding'''. Extendable with stackable [[protocol decoders]] written in Python 3.<br />
* '''File format support'''. Supports various [[Input output formats|input/output file formats]] (binary, ASCII, hex, CSV, gnuplot, [http://en.wikipedia.org/wiki/Value_change_dump VCD], ...).<br />
* '''Reusable code'''. Consists of the [[libsigrok]] and [[libsigrokdecode]] shared libraries which can be used by various frontends/GUIs.<br />
</small><br />
</div><br />
<br />
== <span style="font-variant:small-caps">Supported hardware</span> <small>([[File:Nuvola OK.png|12px]]: supported, [[File:Nuvola Orange.png|12px]]: work in progress, [[File:Nuvola Red.png|12px]]: planned)</small> ==<br />
<br />
{| border="0" style="font-size: smaller; width: 100%"<br />
<br />
|- bgcolor="#bbbbbb"<br />
| colspan="5" | '''[[Supported_hardware#Logic_analyzers|Logic analyzers:]]'''<br />
<br />
|- bgcolor="#fafafa"<br />
| [[File:Saleae Logic.jpg|40x25px|link=Saleae Logic]]&nbsp;<small>[[File:Nuvola OK.png|16px]]<br />[[Saleae Logic]]</small><br />
| [[File:Eeelec xla esla100.jpg|40x25px|link=EE Electronics ESLA100]]&nbsp;<small>[[File:Nuvola OK.png|16px]]<br />[[EE Electronics ESLA100]]</small><br />
| [[File:ASIX SIGMA.jpg|40x25px|link=ASIX SIGMA]]&nbsp;<small>[[File:Nuvola OK.png|16px]]<br />[[ASIX SIGMA / SIGMA2]]</small><br />
| [[File:Openbench logic sniffer front.jpg|40x25px|link=Openbench Logic Sniffer]]&nbsp;<small>[[File:Nuvola OK.png|16px]]<br />[[Openbench Logic Sniffer]]</small><br />
| [[File:logic-shrimp-front.png|40x25px|link=Logic Shrimp]]&nbsp;<small>[[File:Nuvola OK.png|16px]]<br />[[Logic Shrimp]]</small><br />
|- bgcolor="#eeeeee"<br />
| [[File:Zeroplus Logic Cube.jpg|40x25px|link=ZEROPLUS Logic Cube LAP-C]]&nbsp;<small>[[File:Nuvola OK.png|16px]]<br />[[ZEROPLUS Logic Cube LAP-C|Zeroplus Logic Cube LAP-C]]</small><br />
| [[File:Chronovu la8 device.jpg|40x25px|link=ChronoVu LA8]]&nbsp;<small>[[File:Nuvola OK.png|16px]]<br />[[ChronoVu LA8]]</small><br />
| [[File:Buglogic3.jpg|40x27px|link=Robomotic BugLogic 3]]&nbsp;<small>[[File:Nuvola OK.png|16px]]<br />[[Robomotic BugLogic 3]]</small><br />
| [[File:Robomotic minilogic.jpg|40x25px|link=Robomotic MiniLogic]]&nbsp;<small>[[File:Nuvola OK.png|16px]]<br />[[Robomotic MiniLogic]]</small><br />
| [[File:Lcsoft-miniboard-front.png|40x25px|link=Lcsoft Mini Board]]&nbsp;<small>[[File:Nuvola OK.png|16px]]<br />[[Lcsoft Mini Board]]</small><br />
|- bgcolor="#fafafa"<br />
| [[File:Braintechnology usb lps.jpg|40x25px|link=Braintechnology USB-LPS]]&nbsp;<small>[[File:Nuvola OK.png|16px]]<br />[[Braintechnology USB-LPS]]</small><br />
| [[File:Cwav usbee sx.jpg|40x25px|link=CWAV USBee SX]]&nbsp;<small>[[File:Nuvola OK.png|16px]]<br />[[CWAV USBee SX]]</small><br />
| [[File:Buspirate v3 front.jpg|40x25px|link=Buspirate]]&nbsp;<small>[[File:Nuvola Orange.png|16px]]<br />[[Buspirate]]</small><br />
| [[File:Ant18e closed.jpg|40x25px|link=RockyLogic Ant18e]]&nbsp;<small>[[File:Nuvola Orange.png|16px]]<br />[[RockyLogic Ant18e]]</small><br />
| [[File:Rockylogic ant8 device.jpg|40x25px|link=RockyLogic Ant8]]&nbsp;<small>[[File:Nuvola Orange.png|16px]]<br />[[RockyLogic Ant8]]</small><br />
|- bgcolor="#eeeeee"<br />
| [[File:Ikalogic scanalogic2 device with probes.jpg|40x25px|link=Ikalogic SCANALOGIC-2 PRO]]&nbsp;<small>[[File:Nuvola Red.png|16px]]<br />[[Ikalogic SCANALOGIC-2 PRO]]</small><br />
| [[File:Microchip pickit2 device front.jpg|40x25px|link=Microchip PICkit2]]&nbsp;<small>[[File:Nuvola Red.png|16px]]<br />[[Microchip PICkit2]]</small><br />
| [[File:Minila mockup.jpg|40x25px|link=MiniLA Mockup]]&nbsp;<small>[[File:Nuvola Red.png|16px]]<br />[[MiniLA Mockup]]</small><br />
| [[File:Acute_pkla1216_front.jpg|40x25px|link=Acute PKLA-1216]]&nbsp;<small>[[File:Nuvola Red.png|16px]]<br />[[Acute PKLA-1216]]</small><br />
| [[File:Saleae_logic16_front.jpg|40x25px|link=Saleae Logic16]]&nbsp;<small>[[File:Nuvola Red.png|16px]]<br />[[Saleae Logic16]]</small><br />
|- bgcolor="#fafafa"<br />
| [[File:Intronix Logicport.jpg|40x25px|link=Intronix Logicport]]&nbsp;<small>[[File:Nuvola Red.png|16px]]<br />[[Intronix Logicport LA1034]]</small><br />
<br />
|- bgcolor="#bbbbbb"<br />
| colspan="5" | '''[[Supported_hardware#Mixed-signal_devices|Mixed-signal devices:]]'''<br />
<br />
|- bgcolor="#fafafa"<br />
| [[File:AX-Pro.JPG|40x25px|link=ARMFLY AX-Pro]]&nbsp;<small>[[File:Nuvola OK.png|16px]]<br />[[ARMFLY AX-Pro]]</small><br />
| [[File:Esla201a.JPG|40x25px|link=EE Electronics ESLA201A]]&nbsp;<small>[[File:Nuvola OK.png|16px]]<br />[[EE Electronics ESLA201A]]</small><br />
| [[File:MSO-19.JPG|40x25px|link=Link Instruments MSO-19]]&nbsp;<small>[[File:Nuvola Orange.png|16px]]<br />[[Link Instruments MSO-19]]</small><br />
| [[File:QA100 Full.JPG|40x25px|link=QuantAsylum QA100]]&nbsp;<small>[[File:Nuvola Red.png|16px]]<br />[[QuantAsylum QA100]]</small><br />
| [[File:Polabs poscope basic2 device top.jpg|40x25px|link=PoLabs PoScope Basic2]]&nbsp;<small>[[File:Nuvola Red.png|16px]]<br />[[PoLabs PoScope Basic2]]</small><br />
|- bgcolor="#eeeeee"<br />
| [[File:Rigol_VS5202D_Full.jpg|40x25px|link=Rigol VS5202D]]&nbsp;<small>[[File:Nuvola Red.png|16px]]<br/>[[Rigol VS5202D]]</small><br />
| [[File:Agilent MSO7104A.jpg|40x25px|link=Agilent MSO7104A]]&nbsp;<small>[[File:Nuvola Red.png|16px]]<br/>[[Agilent MSO7104A]]</small><br />
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|- bgcolor="#bbbbbb"<br />
| colspan="5" | '''[[Supported_hardware#Oscilloscopes|Oscilloscopes:]]'''<br />
<br />
|- bgcolor="#fafafa"<br />
| [[File:Dso2090-case-top-small.jpg|40x25px|link=Hantek DSO-2090]]&nbsp;<small>[[File:Nuvola Orange.png|16px]]<br />[[Hantek DSO-2090]]</small><br />
| [[File:Velleman pcsu1000 pcb front.jpg|40x25px|link=Velleman PCSU1000]]&nbsp;<small>[[File:Nuvola Orange.png|16px]]<br />[[Velleman PCSU1000]]</small><br />
| [[File:Picoscope 2203 front.jpg|40x25px|link=Pico Technology PicoScope 2203]]&nbsp;<small>[[File:Nuvola Red.png|16px]]<br />[[Pico Technology PicoScope 2203|Pico Tech PicoScope 2203]]</small><br />
|}<br />
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== [[File:Sigrok_stone.png]] <span style="font-variant:small-caps">Documentation</span> ==<br />
<br />
* Building: [[Linux]], [[Mac OS X]], [[Windows]], [[FreeBSD]]<br />
* [[libsigrok]] (hardware access lib)<br />
* [[libsigrokdecode]] (protocol decoder lib)<br />
* [[sigrok-cli]] (command-line)<br />
* [[sigrok-qt]] (cross-platform Qt GUI)<br />
* [[sigrok-gtk]] (cross-platform GTK+ GUI)<br />
* [[Input output formats]]<br />
* [[Protocol decoders]]<br />
* [[Firmware]], [[fx2lafw]]<br />
* [[Example dumps]]<br />
* [[Logic analyzer comparison]]<br />
* [[GPIB interface comparison]]<br />
* [[Probe comparison]]<br />
<br />
</td><td style="vertical-align:top" width="32%"><br />
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== [[File:Sigrok_stone.png]] <span style="font-variant:small-caps">Development</span> ==<br />
* [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok;a=tree Browse Source Code]<br />
* [[TODO]]<br />
* [[Protocol decoder HOWTO]]<br />
* [[Protocol decoder API]]<br />
* [[Formats and structures]]<br />
* [[Hardware plugin API]]<br />
* [[Input API]]<br />
* [[Output API]]<br />
* [[GUI design]]<br />
* [[GPIB]]/[[IEEE-488]] support project<br />
* [[gpibgrok]] project<br />
<br />
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== [[File:Sigrok_stone.png]] <span style="font-variant:small-caps">Getting in touch</span> ==<br />
<br />
* Mailing lists: [https://lists.sourceforge.net/lists/listinfo/sigrok-devel sigrok-devel] ([http://news.gmane.org/gmane.comp.debugging.sigrok.devel archive]), [https://lists.sourceforge.net/lists/listinfo/sigrok-commits sigrok-commits] ([http://sourceforge.net/mailarchive/forum.php?forum_name=sigrok-commits archive])<br />
* IRC: '''[irc://chat.freenode.net/sigrok #sigrok]''' on [http://www.freenode.net Freenode]<br />
* identi.ca: [http://www.identi.ca/group/sigrok sigrok group], [https://identi.ca/search/notice?q=sigrok search], Twitter: [https://twitter.com/#!/search/realtime/sigrok search]<br />
* Google+: [https://plus.google.com/s/sigrok search]<br />
* Sites: [http://sourceforge.net/projects/sigrok/ SF], Fm: [http://freecode.com/projects/libsigrokdecode sr]/[http://freecode.com/projects/libsigrokdecode srd]/[http://freecode.com/projects/sigrok cli]/[http://freecode.com/projects/sigrok-dumps dumps], [https://www.ohloh.net/p/sigrok ohloh], [http://delicious.com/url/d8996d567839064c799ac217b263b2c8 del.icio.us], [http://www.reddit.com/search?q=sigrok Reddit], [http://digg.com/search?q=sigrok Digg], [[Press#Other|others]]<br />
* Other: [[Logo|sigrok logo]]<br />
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[[File:Probes various.jpg|center|thumb|<small>Logic analyzer probe collection</small>]]<br />
<br />
<br clear=all /><br />
<br />
'''<span style="font-variant:small-caps; font-size:120%">[[File:Sigrok_stone.png]] [[News]] / [[Current events|Events]] / [[Press]]</span>'''<hr /><br />
<!-- Please always make this list 7 items long (7 most recent news items). --><br />
<small><br />
* '''2012/05/18:''' [[News#2012.2F05.2F18_sigrok-dumps_0.1.0_released|sigrok-dumps 0.1.0]]<br />
* '''2012/05/02:''' [[News#2012.2F05.2F02_Slashdotted.21|Slashdotted!]]<br />
* '''2012/04/26:''' [[News#2012.2F04.2F26_New_protocol_decoder:_JTAG|New decoder: JTAG]]<br />
* '''2012/04/17:''' [[News#2012.2F04.2F17_libsigrok_0.1.0_released|libsigrok 0.1.0]]<br />
* '''2012/04/17:''' [[News#2012.2F04.2F17_libsigrokdecode_0.1.0_released|libsigrokdecode 0.1.0]]<br />
* '''2012/04/17:''' [[News#2012.2F04.2F17_sigrok-cli_0.3.0_released|sigrok-cli 0.3.0]]<br />
* '''2011/12/27:''' [[News##2011.2F12.2F27_sigrok_.40_28C3|sigrok @ 28C3]]<br />
</small><br />
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</td></tr></table><br />
<br />
----<br />
<small><br />
'''IMPORTANT: Unless explicitly specified otherwise, all contents in this wiki (including text and images) are released under the <span style="color:red">CC-BY-SA 3.0</span> license. If you don't want that, please explicitly specify another free-ish license when adding pages/images!'''<br />
</small><br />
__NOTOC__<br />
__NOEDITSECTION__</div>Gushttps://sigrok.org/w/index.php?title=Current_events&diff=1719Current events2012-04-26T21:12:08Z<p>Gus: </p>
<hr />
<div>== Upcoming Events ==<br />
<br />
None, currently.<br />
<br />
== Past Events ==<br />
<br />
'''2012'''<br />
<br />
* Apr 26, 2012: Arduino workshop with Sigrok introduction at [http://www.meetup.com/bitraf/events/60983702/ Bitraf] in Oslo.<br />
<br />
'''2011'''<br />
<br />
* Dec 27-30, 2011: sigrok hacking at [http://events.ccc.de/congress/2011/wiki/Main_Page 28C3] in Berlin.<br />
<br />
'''2010'''<br />
<br />
* Dec 27-30, 2010: sigrok hacking at [http://events.ccc.de/congress/2010/wiki/Main_Page 27C3] in Berlin.<br />
* Apr 10, 2010: [[User:Uwe Hermann|Uwe Hermann]] presented sigrok at the [http://www.bytewerk.org/index.php/Eroeffnungsveranstaltung "bytewerk" hackerspace] (Ingolstadt, Germany).<br />
* Mar 19, 2010: [[User:Bert|Bert Vermeulen]] presented sigrok at the [http://0x20.be/Opening_Weekend "Whitespace" hackerspace] (Ghent, Belgium).</div>Gushttps://sigrok.org/w/index.php?title=Current_events&diff=1718Current events2012-04-26T21:11:48Z<p>Gus: /* Past Events */</p>
<hr />
<div>== Upcoming Events ==<br />
<br />
None, currently.<br />
<br />
== Past Events ==<br />
<br />
'''2012'''<br />
<br />
* Apr 26, 2012: Arduino workshop with Sigrok introduction [http://www.meetup.com/bitraf/events/60983702/ Bitraf] in Oslo.<br />
<br />
'''2011'''<br />
<br />
* Dec 27-30, 2011: sigrok hacking at [http://events.ccc.de/congress/2011/wiki/Main_Page 28C3] in Berlin.<br />
<br />
'''2010'''<br />
<br />
* Dec 27-30, 2010: sigrok hacking at [http://events.ccc.de/congress/2010/wiki/Main_Page 27C3] in Berlin.<br />
* Apr 10, 2010: [[User:Uwe Hermann|Uwe Hermann]] presented sigrok at the [http://www.bytewerk.org/index.php/Eroeffnungsveranstaltung "bytewerk" hackerspace] (Ingolstadt, Germany).<br />
* Mar 19, 2010: [[User:Bert|Bert Vermeulen]] presented sigrok at the [http://0x20.be/Opening_Weekend "Whitespace" hackerspace] (Ghent, Belgium).</div>Gushttps://sigrok.org/w/index.php?title=Input_output_formats&diff=802Input output formats2011-01-19T22:44:59Z<p>Gus: </p>
<hr />
<div>== Input formats ==<br />
<br />
=== Logic analyzer ===<br />
<br />
TODO<br />
<br />
=== sigrok session ===<br />
<br />
TODO<br />
<br />
== Output formats ==<br />
<br />
=== sigrok session ===<br />
<br />
TODO<br />
<br />
=== ASCII bits ===<br />
<br />
<small><br />
$ '''sigrok-cli --samples 1000 -f bits'''<br />
Acquisition with 8/8 probes at 200 KHz<br />
1:11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 <br />
2:00000000 00011111 11111111 11100000 00000000 00011111 11111111 11110000 <br />
3:11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 <br />
4:11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 <br />
5:11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 <br />
6:01111000 01001100 01111100 01100000 00011100 01101100 00011100 00100011 <br />
7:11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 <br />
8:11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 <br />
1:11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 <br />
2:00000000 00001111 11111111 11110000 00000000 00000111 11111111 11111000 <br />
3:11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 <br />
4:11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 <br />
5:11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 <br />
6:00011110 00100111 00001110 00110000 01001110 00110010 01101110 00010000 <br />
7:11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 <br />
8:11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 <br />
[...]<br />
</small><br />
<br />
=== ASCII ===<br />
<br />
<small><br />
$ sigrok-cli -d 0 --time 10 -p 1,2 -o samplerate=1M -f ascii<br />
Acquisition with 2/16 probes at 1 MHz<br />
1:/""""""""\.........../""""""""\.........../""""""""\.........../""""""""\.<br />
2 :........../"""""""""""""""""""\...................../"""""""""""""""""""\.<br />
1:........./"""""""""\........../"""""""""\........../"""""""""\........../"<br />
2:..................../"""""""""""""""""""\..................../""""""""""""<br />
1:""""""""\........../""""""""\.........../""""""""\.........../""""""""\...<br />
2:"""""""\...................../"""""""""""""""""""\...................../""<br />
1:......../""""""""\........../"""""""""\........../"""""""""\........../"""<br />
2:"""""""""""""""""\...................../"""""""""""""""""""\..............<br />
1:""""""\........../"""""""""\........../""""""""\.........../""""""""\.....<br />
2:....../"""""""""""""""""""\...................../"""""""""""""""""""\.....<br />
</small><br />
<br />
=== hex ===<br />
<br />
<small><br />
$ '''sigrok-cli --samples 1000 -f hex'''<br />
Acquisition with 8/8 probes at 200 KHz<br />
1:ff ff ff ff ff ff ff ff <br />
2:00 7f ff c0 00 3f ff c0 <br />
3:ff ff ff ff ff ff ff ff <br />
4:ff ff ff ff ff ff ff ff <br />
5:ff ff ff ff ff ff ff ff <br />
6:71 b2 71 8f 70 9f 78 c0 <br />
7:ff ff ff ff ff ff ff ff <br />
8:ff ff ff ff ff ff ff ff <br />
1:ff ff ff ff ff ff ff ff <br />
2:00 3f ff e0 00 1f ff e0 <br />
3:ff ff ff ff ff ff ff ff <br />
4:ff ff ff ff ff ff ff ff <br />
5:ff ff ff ff ff ff ff ff <br />
6:f8 d8 f8 c0 3c 4c 1c 63 <br />
7:ff ff ff ff ff ff ff ff <br />
8:ff ff ff ff ff ff ff ff <br />
[...]<br />
</small><br />
<br />
=== Binary ===<br />
<br />
Raw, binary output format without any metadata. In the example below every byte contains one sample consisting of 8 probe values (each bit denotes the high or low value of one probe; bit 0 corresponds to probe 0, and so on). In the example, probe 6 is tied to GND (i.e., low), all others are high.<br />
<br />
<small><br />
$ '''sigrok-cli --samples 1000 -f binary > somefile.dat'''<br />
$ '''hexdump -Cv somefile.dat'''<br />
00000000 bf bf bf bf bf bf bf bf bf bf bf bf bf bf bf bf |................|<br />
00000010 bf bf bf bf bf bf bf bf bf bf bf bf bf bf bf bf |................|<br />
00000020 bf bf bf bf bf bf bf bf bf bf bf bf bf bf bf bf |................|<br />
00000030 bf bf bf bf bf bf bf bf bf bf bf bf bf bf bf bf |................|<br />
[...]<br />
</small><br />
<br />
=== Value Change Dump (VCD) ===<br />
<br />
[[File:Sigrok vcd output in gtkwave.png|thumb|320px|right|sigrok VCD output viewed in gtkwave]]<br />
<br />
<small><br />
$ '''sigrok-cli --samples 1000 -f vcd'''<br />
$date<br />
TODO<br />
$end<br />
$version<br />
sigrok 0.1pre<br />
$end<br />
$comment<br />
Acquisition with 8/8 probes at 200 KHz<br />
$end<br />
$timescale<br />
1 ns<br />
$end<br />
$scope module sigrok $end<br />
$var wire 1 ! channel1 $end<br />
$var wire 1 " channel2 $end<br />
$var wire 1 # channel3 $end<br />
$var wire 1 $ channel4 $end<br />
$var wire 1 % channel5 $end<br />
$var wire 1 & channel6 $end<br />
$var wire 1 ' channel7 $end<br />
$var wire 1 ( channel8 $end<br />
$upscope $end<br />
$enddefinitions $end<br />
$dumpvars<br />
#0<br />
1!<br />
#0<br />
0"<br />
#0<br />
1#<br />
#0<br />
1$<br />
#0<br />
1%<br />
#0<br />
0&<br />
#0<br />
1'<br />
#0<br />
1(<br />
#3<br />
1&<br />
#8<br />
0&<br />
#11<br />
1&<br />
#13<br />
1"<br />
#13<br />
0&<br />
[...]<br />
$dumpoff<br />
$end<br />
</small><br />
<br />
=== Gnuplot ===<br />
<br />
[[File:Sigrok gnuplot output.png|thumb|right|320px|sigrok gnuplot output format, PNG format]]<br />
<br />
<small><br />
$ '''sigrok-cli --samples 1000 -f gnuplot'''<br />
# Sample data in space-separated columns format usable by gnuplot<br />
#<br />
# Generated by: sigrok 0.1pre on TODO<br />
# Comment: Acquisition with 8/8 probes at 200 KHz<br />
# Timescale: 1 ns<br />
# Column assignment:<br />
# Column 0: channel 1<br />
# Column 1: channel 2<br />
# Column 2: channel 3<br />
# Column 3: channel 4<br />
# Column 4: channel 5<br />
# Column 5: channel 6<br />
# Column 6: channel 7<br />
# Column 7: channel 8<br />
<br />
0 1 0 1 1 1 0 1 1 <br />
1 1 0 1 1 1 0 1 1 <br />
2 1 0 1 1 1 0 1 1 <br />
3 1 0 1 1 1 0 1 1 <br />
4 1 0 1 1 1 0 1 1 <br />
5 1 0 1 1 1 0 1 1 <br />
6 1 0 1 1 1 1 1 1 <br />
7 1 0 1 1 1 1 1 1 <br />
8 1 0 1 1 1 1 1 1 <br />
9 1 0 1 1 1 1 1 1 <br />
10 1 0 1 1 1 1 1 1 <br />
11 1 0 1 1 1 0 1 1 <br />
12 1 0 1 1 1 0 1 1 <br />
13 1 0 1 1 1 0 1 1 <br />
14 1 0 1 1 1 1 1 1 <br />
[...]<br />
</small><br />
<br />
== LaTeX ==<br />
[http://www.ctan.org/tex-archive/graphics/pgf/contrib/tikz-timing TODO]</div>Gushttps://sigrok.org/w/index.php?title=TODO&diff=714TODO2011-01-12T22:13:08Z<p>Gus: </p>
<hr />
<div>This is a random list of TODO items for the code and/or ideas for improvements.<br />
<br />
== General ==<br />
<br />
* Possibly remove the dependency on glib and gthread (various reasons), at least in libsigrok, probably also in sigrok-cli.<br />
** A new linked list implementation must be found, or written, that duplicates the important parts of glib's GSList (singly-linked list).<br />
** However, glib solves a number of portability issues for us, so it'll probably stay.<br />
* sigrok uses uint64_t as an internal datatype to represent a sample, limiting the number of probes on supported hardware to 64. But high-end logic analyzers can have hundreds of probes. A solution would be to switch to either a roll-our-own byte array type, or use [http://gmplib.org/ GMP]. In any case, the overhead of switching over shouldn't be too bad: the filter code and frontend datafeed callback functions will need to use it, but hardware drivers should have enough with a couple of lightweight wrappers.<br />
<br />
== Sigrok 0.1 (Stable) Release-critical issues ==<br />
<br />
Sigrok 0.1 comprises only sigrok-cli, i.e. GUI and protocol decoders are not part of the release.<br />
<br />
* Ensure that segfaults are rare / non-existing in CLI<br />
* Windows port<br />
* more?<br />
<br />
== libsigrok ==<br />
<br />
* Fix/workaround libusb 1.0 [[Windows]] port issues:<br />
** Device renumeration not yet supported (needed for FX2 based LAs)<br />
** File descriptor / socket based polling not supported in Windows. Workaround (short-term): Use a thread in sigrok.<br />
* Session loading from file.<br />
* sigrok_errno:<br />
** Most backend functions return status as an integer, which is SIGROK_OK if all went well, or SIGROK_ERR_* and similar if an error occurred.<br />
** However there is no way to pass any information back as to what went wrong &mdash; and this is important for user-friendliness.<br />
** Perhaps an error code is not enough; maybe something like sigrok_errno(errorcode, "unsupported device") is better.<br />
** Both the cmdline and GUI interfaces need this, really, so it should be a backend library thing.<br />
* <s>configure: Add --enable-hw-foo options to enable/disable support for every device at compile-time. This is useful for different platforms where not all libs are fully supported/available yet (libusb, libftdi, etc), for example.</s><br />
* Make sure all optional components are really optional in the build system:<br />
** <s>Link against libftdi/libusb/etc only if one of the enabled drivers needs those.</s><br />
** Only require Python if the users wants protocol decoders, the rest should also build/compile/run fine without Python installed.<br />
** ...<br />
* Add output for latex package [http://www.ctan.org/tex-archive/graphics/pgf/contrib/tikz-timing tikz-timing]<br />
<br />
== libsigrokdecode ==<br />
<br />
* <s>Keep this independent of libsigrok and any logic analyzer hardware. It should work purely on streams / buffers of bytes to be usable by other projects.</s><br />
<br />
== Hardware drivers ==<br />
<br />
* <s>Bus/driver-independent device instance struct, to replace usb_device_instance and serial_device_instance. Once this is done, device instance-specific information can be cleanly separated and tacked on to the generic device instance:</s><br />
** <s>Vendor/model/version scheme in hardware drivers.</s><br />
** Clean up device-specific globals in hardware drivers, to properly permit multiple devices per driver.<br />
<br />
{{fontcolor|green|Bert is working on this.}}<br />
<br />
==== Demo driver ====<br />
<br />
<s>It would be good if sigrok would ship with a built-in driver that always works, regardless of hardware connected. This driver would be configurable to provide a clock on a virtual pin, with configurable frequency. It could support multiple of these, at different frequencies.<br />
<br />
In addition to giving anyone something to do with sigrok to try it out, this may also have some use cases outside of this: perhaps as a reference clock, next to a live capture.<br />
<br />
Since this driver only needs to change to 0/1 at a configurable interval, and the interval is exactly the same as the count of the samples in the datafeed it outputs, the signal it generates would thus be 100% perfect, making it an interesting reference.</s><br />
<br />
==== Open-source firmware for the FX2 devices ====<br />
<br />
The Cypress FX2-based devices, such as the Saleae Logic and the USBee SX, use only a minimal vendor-provided firmware. The only thing it really does is set the sample rate and turn on the chip's auto-mode. Nevertheless, the vendors provide the firmware as a binary blob, with no source.<br />
<br />
It would be great if sigrok could ship with an own firmware implementation for these devices. Some links:<br />
<br />
* [http://sdcc.sourceforge.net/ SDCC], the Small Devices C Compiler, is a compiler specifically suited to small MCUs, and has support for the 8051 core in the FX2.<br />
* [http://allmybrain.com/2008/12/05/an-open-source-library-for-writing-firmware-on-the-cypress-fx2-with-sdcc/ fx2lib] is an open-source library for writing firmware on the FX2. It has a number of interesting functions, including implementing custom USB vendor commands.<br />
* [http://gnuradio.org/ GNU Radio]'s USRP2 board has an FX2 on it, and GNU Radio has extensive custom firmware for it.<br />
<br />
[[User:Uwe Hermann|Uwe Hermann]] is working on an open-source FX2 firmware for use with various logic analyzers.<br />
<br />
== sigrok-cli ==<br />
<br />
* Implement full support for all possible trigger types to be specified via the command-line.<br />
<br />
== sigrok-gui ==<br />
<br />
* ...<br />
<br />
== Decoders ==<br />
<br />
* Find/evaluate alternatives to '''psyco''' for performance improvements on non-x86 architectures.<br />
<br />
== Windows installer ==<br />
<br />
* Add support for downloading/installing the Python Windows installer.<br />
* ...<br />
<br />
== Code quality and build ==<br />
<br />
* <s>Consistently use uint64_t for large data types such as samplerate, number of samples, etc.</s></div>Gushttps://sigrok.org/w/index.php?title=TODO&diff=713TODO2011-01-12T22:04:57Z<p>Gus: </p>
<hr />
<div>This is a random list of TODO items for the code and/or ideas for improvements.<br />
<br />
== General ==<br />
<br />
* Possibly remove the dependency on glib and gthread (various reasons), at least in libsigrok, probably also in sigrok-cli.<br />
** A new linked list implementation must be found, or written, that duplicates the important parts of glib's GSList (singly-linked list).<br />
** However, glib solves a number of portability issues for us, so it'll probably stay.<br />
* sigrok uses uint64_t as an internal datatype to represent a sample, limiting the number of probes on supported hardware to 64. But high-end logic analyzers can have hundreds of probes. A solution would be to switch to either a roll-our-own byte array type, or use [http://gmplib.org/ GMP]. In any case, the overhead of switching over shouldn't be too bad: the filter code and frontend datafeed callback functions will need to use it, but hardware drivers should have enough with a couple of lightweight wrappers.<br />
<br />
== Sigrok 0.1 Stable Release-critical Bugs ==<br />
<br />
Sigrok 0.1 comprises only sigrok-cli, i.e. GUI and protocol decoders are not part of the release.<br />
<br />
* Ensure that segfaults are rare / non-existing in CLI<br />
* Windows port<br />
* more?<br />
<br />
== libsigrok ==<br />
<br />
* Fix/workaround libusb 1.0 [[Windows]] port issues:<br />
** Device renumeration not yet supported (needed for FX2 based LAs)<br />
** File descriptor / socket based polling not supported in Windows. Workaround (short-term): Use a thread in sigrok.<br />
* Session loading from file.<br />
* sigrok_errno:<br />
** Most backend functions return status as an integer, which is SIGROK_OK if all went well, or SIGROK_ERR_* and similar if an error occurred.<br />
** However there is no way to pass any information back as to what went wrong &mdash; and this is important for user-friendliness.<br />
** Perhaps an error code is not enough; maybe something like sigrok_errno(errorcode, "unsupported device") is better.<br />
** Both the cmdline and GUI interfaces need this, really, so it should be a backend library thing.<br />
* <s>configure: Add --enable-hw-foo options to enable/disable support for every device at compile-time. This is useful for different platforms where not all libs are fully supported/available yet (libusb, libftdi, etc), for example.</s><br />
* Make sure all optional components are really optional in the build system:<br />
** <s>Link against libftdi/libusb/etc only if one of the enabled drivers needs those.</s><br />
** Only require Python if the users wants protocol decoders, the rest should also build/compile/run fine without Python installed.<br />
** ...<br />
* Add output for latex package [http://www.ctan.org/tex-archive/graphics/pgf/contrib/tikz-timing tikz-timing]<br />
<br />
== libsigrokdecode ==<br />
<br />
* <s>Keep this independent of libsigrok and any logic analyzer hardware. It should work purely on streams / buffers of bytes to be usable by other projects.</s><br />
<br />
== Hardware drivers ==<br />
<br />
* <s>Bus/driver-independent device instance struct, to replace usb_device_instance and serial_device_instance. Once this is done, device instance-specific information can be cleanly separated and tacked on to the generic device instance:</s><br />
** <s>Vendor/model/version scheme in hardware drivers.</s><br />
** Clean up device-specific globals in hardware drivers, to properly permit multiple devices per driver.<br />
<br />
{{fontcolor|green|Bert is working on this.}}<br />
<br />
==== Demo driver ====<br />
<br />
<s>It would be good if sigrok would ship with a built-in driver that always works, regardless of hardware connected. This driver would be configurable to provide a clock on a virtual pin, with configurable frequency. It could support multiple of these, at different frequencies.<br />
<br />
In addition to giving anyone something to do with sigrok to try it out, this may also have some use cases outside of this: perhaps as a reference clock, next to a live capture.<br />
<br />
Since this driver only needs to change to 0/1 at a configurable interval, and the interval is exactly the same as the count of the samples in the datafeed it outputs, the signal it generates would thus be 100% perfect, making it an interesting reference.</s><br />
<br />
==== Open-source firmware for the FX2 devices ====<br />
<br />
The Cypress FX2-based devices, such as the Saleae Logic and the USBee SX, use only a minimal vendor-provided firmware. The only thing it really does is set the sample rate and turn on the chip's auto-mode. Nevertheless, the vendors provide the firmware as a binary blob, with no source.<br />
<br />
It would be great if sigrok could ship with an own firmware implementation for these devices. Some links:<br />
<br />
* [http://sdcc.sourceforge.net/ SDCC], the Small Devices C Compiler, is a compiler specifically suited to small MCUs, and has support for the 8051 core in the FX2.<br />
* [http://allmybrain.com/2008/12/05/an-open-source-library-for-writing-firmware-on-the-cypress-fx2-with-sdcc/ fx2lib] is an open-source library for writing firmware on the FX2. It has a number of interesting functions, including implementing custom USB vendor commands.<br />
* [http://gnuradio.org/ GNU Radio]'s USRP2 board has an FX2 on it, and GNU Radio has extensive custom firmware for it.<br />
<br />
[[User:Uwe Hermann|Uwe Hermann]] is working on an open-source FX2 firmware for use with various logic analyzers.<br />
<br />
== sigrok-cli ==<br />
<br />
* Implement full support for all possible trigger types to be specified via the command-line.<br />
<br />
== sigrok-gui ==<br />
<br />
* ...<br />
<br />
== Decoders ==<br />
<br />
* Find/evaluate alternatives to '''psyco''' for performance improvements on non-x86 architectures.<br />
<br />
== Windows installer ==<br />
<br />
* Add support for downloading/installing the Python Windows installer.<br />
* ...<br />
<br />
== Code quality and build ==<br />
<br />
* <s>Consistently use uint64_t for large data types such as samplerate, number of samples, etc.</s></div>Gushttps://sigrok.org/w/index.php?title=Linux&diff=520Linux2010-05-22T18:01:14Z<p>Gus: </p>
<hr />
<div>[[File:sigrok linux.png|right|thumb|320px|sigrok-gui on Linux]]<br />
<br />
This page describes how to build sigrok on Linux.<br />
<br />
== Requirements ==<br />
<br />
* git (for cloning the source code repository)<br />
* gcc, g++, make, ...<br />
* autoconf, automake, libtool, pkg-config<br />
* [http://library.gnome.org/devel/glib/unstable/ libglib] >= 2.0<br />
* [http://www.libusb.org libusb] >= 1.0.5<br />
* [http://nih.at/libzip/ libzip] >= 0.8<br />
* [http://www.intra2net.com/en/developer/libftdi/ libftdi] (optional, only required for some devices)<br />
<!-- * [http://www.intra2net.com/en/developer/libftdi/ libftdi] >= 0.17 (optional, only required for some devices) --><br />
* [http://www.python.org Python] >= 2.5 (optional, only required for protocol decoders)<br />
* [http://qt.nokia.com Qt + Qt Creator] >= 4.5 (optional, only required for building/editing the GUI)<br />
<br />
== Installing the build-dependencies ==<br />
<br />
On most Linux distributions there are pre-built packages for the sigrok dependencies (if not, you have to build the packages from source). The installation using a package manager is usually pretty simple.<br />
<br />
Debian/Ubuntu:<br />
<br />
$ '''apt-get install git-core gcc g++ make autoconf automake libtool pkg-config libglib2.0-dev libftdi-dev libusb-1.0-0-dev libzip-dev python-dev qtcreator qt4-designer qt4-dev-tools libqt4-dev'''<br />
<br />
Fedora:<br />
<br />
$ '''yum install gcc-c++ libtool glib2-devel libftdi-devel libusb1-devel libzip-devel qt-devel python-devel'''<br />
<br />
== Building ==<br />
<br />
$ '''git clone git://sigrok.git.sourceforge.net/gitroot/sigrok/sigrok'''<br />
$ '''cd sigrok'''<br />
$ '''./autogen.sh'''<br />
$ '''./configure'''<br />
$ '''make'''<br />
$ '''make install'''<br />
<br />
Then, for building the GUI:<br />
<br />
$ '''cd gui'''<br />
$ '''qmake'''<br />
$ '''make'''<br />
<br />
If you get warnings claiming potential symbol conflicts when running qmake, you are likely invoking qt3. Try running qmake-qt4 to force the correct version.<br />
<br />
== Distribution packages ==<br />
<br />
* Debian / Ubuntu: [[User:Uwe Hermann|Uwe Hermann]] will create [http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=579600 packages for Debian unstable] (which will semi-automatically migrate to Ubuntu after a while).<br />
* Fedora: See [[Linux/Fedora]].</div>Gushttps://sigrok.org/w/index.php?title=ASIX_SIGMA_/_SIGMA2&diff=493ASIX SIGMA / SIGMA22010-05-02T21:40:12Z<p>Gus: </p>
<hr />
<div>[[File:ASIX SIGMA.jpg|thumb|right|ASIX SIGMA.]]<br />
[[File:Sigma.jpg|thumb|right|ASIX SIGMA internals.]]<br />
<br />
The [http://tools.asix.net/dbg_sigma.htm ASIX SIGMA] is a 16 channel logic analyzer with sample rate support up to 200 MHz and with 256 Mbit on-board memory.<br />
<br />
It is supported by sigrok, and the necessary firmware files are generously provided by the vendor for distribution. As a result, the SIGMA works out of the box with sigrok. Trigger support has been implemented in 100 MHz and 200 MHz modes for rising/falling edges. In other modes, users can specify additional trigger values, listed in the table below.<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
!Samplerate<br />
!Number of probes<br />
!Trigger support<br />
|- bgcolor="#eeeeee"<br />
| 200 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 250 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 500 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 1 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 5 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 10 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 25 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 50 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 100 MHz<br />
| 8<br />
| Edge of one probe<br />
|- bgcolor="#dddddd"<br />
| 200 MHz<br />
| 4<br />
| Edge of one probe<br />
|}<br />
<br />
* Not implemented in sigrok yet.<br />
<br />
See [[ASIX SIGMA/Info]] for more detailed information on the device.<br />
<br />
== Example usage ==<br />
An example that captures from 4 probes, for 100ms at 10 MHz, with trigger condition 1:high, 2:rising, 3:low, 4:high.<br />
<br />
sigrok-cli --wait-trigger --triggers 1=1,2=r,3=0,4=1 --samples 5000000 --time 100 -o samplerate=10m -f bits -p 1-4<br />
<br />
== Firmware ==<br />
<br />
The firmware files (FPGA bitstreams) for the ASIX SIGMA have been provided by the vendor under a [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=blob;f=asix-sigma/LICENSE.Sigma license which allows redistribution], and are available from the [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=summary sigrok-firmwares] repository:<br />
<br />
$ '''git clone git://sigrok.git.sourceforge.net/gitroot/sigrok/sigrok-firmwares'''<br />
<br />
In order to use the ASIX SIGMA in sigrok, you need to copy the firmware files to the correct sigrok directory, '''/usr/local/share/sigrok/firmware''' per default:<br />
<br />
$ '''cp sigrok-firmwares/asix-sigma/*.fw /usr/local/share/sigrok/firmware'''<br />
<br />
== Resources ==<br />
<br />
* [http://labs.ping.uio.no/2010/04/initial-support-for-asix-sigma-in-sigrok/ Initial support for Asix Sigma in Sigrok]<br />
* [http://labs.ping.uio.no/2009/09/sampi-a-logic-analyzer/ PING Labs: Sampi – A Logic Analyzer]<br />
* [http://www.flickr.com/photos/chlunde/3383669140/ flickr: ASIX SIGMA in chlunde's photostream] (photos and more information about the device)</div>Gushttps://sigrok.org/w/index.php?title=ASIX_SIGMA_/_SIGMA2&diff=492ASIX SIGMA / SIGMA22010-05-02T21:35:50Z<p>Gus: </p>
<hr />
<div>[[File:ASIX SIGMA.jpg|thumb|right|ASIX SIGMA.]]<br />
[[File:Sigma.jpg|thumb|right|ASIX SIGMA internals.]]<br />
<br />
The [http://tools.asix.net/dbg_sigma.htm ASIX SIGMA] is a 16 channel logic analyzer with sample rate support up to 200 MHz and with 256 Mbit on-board memory.<br />
<br />
It is supported by sigrok, and the necessary firmware files are generously provided by the vendor for distribution. As a result, the SIGMA works out of the box with sigrok. Trigger support has been implemented in 100 MHz and 200 MHz modes for rising/falling edges. Trigger features at lower sample rates are far more advanced and will be supported later.<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
!Samplerate<br />
!Number of probes<br />
!Trigger support<br />
|- bgcolor="#eeeeee"<br />
| 200 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 250 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 500 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 1 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 5 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 10 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 25 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 50 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 100 MHz<br />
| 8<br />
| Edge of one probe<br />
|- bgcolor="#dddddd"<br />
| 200 MHz<br />
| 4<br />
| Edge of one probe<br />
|}<br />
<br />
* Not implemented in sigrok yet.<br />
<br />
See [[ASIX SIGMA/Info]] for more detailed information on the device.<br />
<br />
== Example usage ==<br />
An example that captures from 4 probes, for 100ms at 10 MHz, with trigger condition 1:high, 2:rising, 3:low, 4:high.<br />
<br />
sigrok-cli --wait-trigger --triggers 1=1,2=r,3=0,4=1 --samples 5000000 --time 100 -o samplerate=10m -f bits -p 1-4<br />
<br />
== Firmware ==<br />
<br />
The firmware files (FPGA bitstreams) for the ASIX SIGMA have been provided by the vendor under a [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=blob;f=asix-sigma/LICENSE.Sigma license which allows redistribution], and are available from the [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=summary sigrok-firmwares] repository:<br />
<br />
$ '''git clone git://sigrok.git.sourceforge.net/gitroot/sigrok/sigrok-firmwares'''<br />
<br />
In order to use the ASIX SIGMA in sigrok, you need to copy the firmware files to the correct sigrok directory, '''/usr/local/share/sigrok/firmware''' per default:<br />
<br />
$ '''cp sigrok-firmwares/asix-sigma/*.fw /usr/local/share/sigrok/firmware'''<br />
<br />
== Resources ==<br />
<br />
* [http://labs.ping.uio.no/2010/04/initial-support-for-asix-sigma-in-sigrok/ Initial support for Asix Sigma in Sigrok]<br />
* [http://labs.ping.uio.no/2009/09/sampi-a-logic-analyzer/ PING Labs: Sampi – A Logic Analyzer]<br />
* [http://www.flickr.com/photos/chlunde/3383669140/ flickr: ASIX SIGMA in chlunde's photostream] (photos and more information about the device)</div>Gushttps://sigrok.org/w/index.php?title=ASIX_SIGMA_/_SIGMA2&diff=491ASIX SIGMA / SIGMA22010-05-02T20:44:20Z<p>Gus: </p>
<hr />
<div>[[File:ASIX SIGMA.jpg|thumb|right|ASIX SIGMA.]]<br />
[[File:Sigma.jpg|thumb|right|ASIX SIGMA internals.]]<br />
<br />
The [http://tools.asix.net/dbg_sigma.htm ASIX SIGMA] is a 16 channel logic analyzer with sample rate support up to 200 MHz and with 256 Mbit on-board memory.<br />
<br />
It is supported by sigrok, and the necessary firmware files are generously provided by the vendor for distribution. As a result, the SIGMA works out of the box with sigrok. Trigger support has been implemented in 100 MHz and 200 MHz modes for rising/falling edges. Trigger features at lower sample rates are far more advanced and will be supported later.<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
!Samplerate<br />
!Number of probes<br />
!Trigger support<br />
|- bgcolor="#eeeeee"<br />
| 200 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 250 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 500 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 1 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 5 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 10 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 25 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 50 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 100 MHz<br />
| 8<br />
| Edge of one probe<br />
|- bgcolor="#dddddd"<br />
| 200 MHz<br />
| 4<br />
| Edge of one probe<br />
|}<br />
<br />
* Not implemented in sigrok yet.<br />
<br />
See [[ASIX SIGMA/Info]] for more detailed information on the device.<br />
<br />
== Example usage ==<br />
An example that captures from 4 probes, for 100ms at 10 MHz, with trigger condition pin 1:high, 2:rising, 3:low and 4:high is given below:<br />
<br />
sigrok-cli --wait-trigger --triggers 1=1,2=r,3=0,4=1 --samples 5000000 --time 100 -o samplerate=10m -f bits -p 1-4<br />
<br />
== Firmware ==<br />
<br />
The firmware files (FPGA bitstreams) for the ASIX SIGMA have been provided by the vendor under a [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=blob;f=asix-sigma/LICENSE.Sigma license which allows redistribution], and are available from the [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=summary sigrok-firmwares] repository:<br />
<br />
$ '''git clone git://sigrok.git.sourceforge.net/gitroot/sigrok/sigrok-firmwares'''<br />
<br />
In order to use the ASIX SIGMA in sigrok, you need to copy the firmware files to the correct sigrok directory, '''/usr/local/share/sigrok/firmware''' per default:<br />
<br />
$ '''cp sigrok-firmwares/asix-sigma/*.fw /usr/local/share/sigrok/firmware'''<br />
<br />
== Resources ==<br />
<br />
* [http://labs.ping.uio.no/2010/04/initial-support-for-asix-sigma-in-sigrok/ Initial support for Asix Sigma in Sigrok]<br />
* [http://labs.ping.uio.no/2009/09/sampi-a-logic-analyzer/ PING Labs: Sampi – A Logic Analyzer]<br />
* [http://www.flickr.com/photos/chlunde/3383669140/ flickr: ASIX SIGMA in chlunde's photostream] (photos and more information about the device)</div>Gushttps://sigrok.org/w/index.php?title=ASIX_SIGMA_/_SIGMA2&diff=490ASIX SIGMA / SIGMA22010-05-02T20:03:16Z<p>Gus: </p>
<hr />
<div>[[File:ASIX SIGMA.jpg|thumb|right|ASIX SIGMA.]]<br />
[[File:Sigma.jpg|thumb|right|ASIX SIGMA internals.]]<br />
<br />
The [http://tools.asix.net/dbg_sigma.htm ASIX SIGMA] is a 16 channel logic analyzer with sample rate support up to 200 MHz and with 256 Mbit on-board memory.<br />
<br />
It is supported by sigrok, and the necessary firmware files are generously provided by the vendor for distribution. As a result, the SIGMA works out of the box with sigrok. Trigger support has been implemented in 100 MHz and 200 MHz modes for rising/falling edges. Trigger features at lower sample rates are far more advanced and will be supported later.<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
!Samplerate<br />
!Number of probes<br />
!Trigger support<br />
|- bgcolor="#eeeeee"<br />
| 200 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 250 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 500 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 1 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 5 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 10 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 25 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 50 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 100 MHz<br />
| 8<br />
| Edge of one probe<br />
|- bgcolor="#dddddd"<br />
| 200 MHz<br />
| 4<br />
| Edge of one probe<br />
|}<br />
<br />
* Not implemented in sigrok yet.<br />
<br />
See [[ASIX SIGMA/Info]] for more detailed information on the device.<br />
<br />
== Example usage ==<br />
An example that captures from 4 probes, for 100ms at 10 MHz, with trigger condition pin 1 high, pin 2 rising, ping 3 low and pin 4 high is given below:<br />
<br />
sigrok-cli --wait-trigger --triggers 1=1,2=r,3=0,4=1 --samples 5000000 --time 100 -o samplerate=10m -f bits -p 1-4<br />
<br />
== Firmware ==<br />
<br />
The firmware files (FPGA bitstreams) for the ASIX SIGMA have been provided by the vendor under a [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=blob;f=asix-sigma/LICENSE.Sigma license which allows redistribution], and are available from the [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=summary sigrok-firmwares] repository:<br />
<br />
$ '''git clone git://sigrok.git.sourceforge.net/gitroot/sigrok/sigrok-firmwares'''<br />
<br />
In order to use the ASIX SIGMA in sigrok, you need to copy the firmware files to the correct sigrok directory, '''/usr/local/share/sigrok/firmware''' per default:<br />
<br />
$ '''cp sigrok-firmwares/asix-sigma/*.fw /usr/local/share/sigrok/firmware'''<br />
<br />
== Resources ==<br />
<br />
* [http://labs.ping.uio.no/2010/04/initial-support-for-asix-sigma-in-sigrok/ Initial support for Asix Sigma in Sigrok]<br />
* [http://labs.ping.uio.no/2009/09/sampi-a-logic-analyzer/ PING Labs: Sampi – A Logic Analyzer]<br />
* [http://www.flickr.com/photos/chlunde/3383669140/ flickr: ASIX SIGMA in chlunde's photostream] (photos and more information about the device)</div>Gushttps://sigrok.org/w/index.php?title=ASIX_SIGMA_/_SIGMA2&diff=489ASIX SIGMA / SIGMA22010-05-02T16:14:57Z<p>Gus: </p>
<hr />
<div>[[File:ASIX SIGMA.jpg|thumb|right|ASIX SIGMA.]]<br />
[[File:Sigma.jpg|thumb|right|ASIX SIGMA internals.]]<br />
<br />
The [http://tools.asix.net/dbg_sigma.htm ASIX SIGMA] is a 16 channel logic analyzer with sample rate support up to 200 MHz and with 256 Mbit on-board memory.<br />
<br />
It is supported by sigrok, and the necessary firmware files are generously provided by the vendor for distribution. As a result, the SIGMA works out of the box with sigrok. Trigger support has been implemented in 100 MHz and 200 MHz modes for rising/falling edges. Trigger features at lower sample rates are far more advanced and will be supported later.<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
!Samplerate<br />
!Number of probes<br />
!Trigger support<br />
|- bgcolor="#eeeeee"<br />
| 200 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 250 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 500 kHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 1 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 5 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 10 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 25 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#dddddd"<br />
| 50 MHz<br />
| 16<br />
| Edge of two probes, state, boolean expression*<br />
|- bgcolor="#eeeeee"<br />
| 100 MHz<br />
| 8<br />
| Edge of one probe<br />
|- bgcolor="#dddddd"<br />
| 200 MHz<br />
| 4<br />
| Edge of one probe<br />
|}<br />
<br />
* Not implemented in sigrok yet.<br />
<br />
See [[ASIX SIGMA/Info]] for more detailed information on the device.<br />
<br />
== Example usage ==<br />
An example that captures from 4 probes, for 100ms at 10 MHz, with trigger condition pin 1 high, pin 2 rising, ping 3 low and pin 4 high is given below:<br />
<br />
sigrok-cli --triggers 1=1,2=r,3=0,4=1 --samples 5000000 --time 100 -o samplerate=10m -f bits -p 1-4<br />
<br />
== Firmware ==<br />
<br />
The firmware files (FPGA bitstreams) for the ASIX SIGMA have been provided by the vendor under a [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=blob;f=asix-sigma/LICENSE.Sigma license which allows redistribution], and are available from the [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=summary sigrok-firmwares] repository:<br />
<br />
$ '''git clone git://sigrok.git.sourceforge.net/gitroot/sigrok/sigrok-firmwares'''<br />
<br />
In order to use the ASIX SIGMA in sigrok, you need to copy the firmware files to the correct sigrok directory, '''/usr/local/share/sigrok/firmware''' per default:<br />
<br />
$ '''cp sigrok-firmwares/asix-sigma/*.fw /usr/local/share/sigrok/firmware'''<br />
<br />
== Resources ==<br />
<br />
* [http://labs.ping.uio.no/2010/04/initial-support-for-asix-sigma-in-sigrok/ Initial support for Asix Sigma in Sigrok]<br />
* [http://labs.ping.uio.no/2009/09/sampi-a-logic-analyzer/ PING Labs: Sampi – A Logic Analyzer]<br />
* [http://www.flickr.com/photos/chlunde/3383669140/ flickr: ASIX SIGMA in chlunde's photostream] (photos and more information about the device)</div>Gushttps://sigrok.org/w/index.php?title=ASIX_SIGMA_/_SIGMA2&diff=488ASIX SIGMA / SIGMA22010-05-02T14:57:50Z<p>Gus: </p>
<hr />
<div>[[File:ASIX SIGMA.jpg|thumb|right|ASIX SIGMA.]]<br />
[[File:Sigma.jpg|thumb|right|ASIX SIGMA internals.]]<br />
<br />
The [http://tools.asix.net/dbg_sigma.htm ASIX SIGMA] is a 16 channel logic analyzer with sample rate support up to 200 MHz and with 256 Mbit on-board memory.<br />
<br />
It is supported by sigrok, and the necessary firmware files are generously provided by the vendor for distribution. As a result, the SIGMA works out of the box with sigrok. Trigger support has been implemented in 100 MHz and 200 MHz modes for rising/falling edges. Trigger features at lower sample rates are far more advanced and will be supported later.<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
!Samplerate<br />
!Number of probes<br />
!Trigger support<br />
|- bgcolor="#eeeeee"<br />
| 200 kHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#dddddd"<br />
| 250 kHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#eeeeee"<br />
| 500 kHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#dddddd"<br />
| 1 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#eeeeee"<br />
| 5 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#dddddd"<br />
| 10 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#eeeeee"<br />
| 25 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#dddddd"<br />
| 50 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#eeeeee"<br />
| 100 MHz<br />
| 8<br />
| Edge of one probe<br />
|- bgcolor="#dddddd"<br />
| 200 MHz<br />
| 4<br />
| Edge of one probe<br />
|}<br />
<br />
See [[ASIX SIGMA/Info]] for more detailed information on the device.<br />
<br />
== Example usage ==<br />
An example that captures from 4 probes, for 100ms at 10 MHz, with trigger condition pin 1 high, pin 2 rising, ping 3 low and pin 4 high is given below:<br />
<br />
sigrok-cli --triggers 1=1,2=r,3=0,4=1 --samples 5000000 --time 100 -o samplerate=10m -f bits -p 1-4<br />
<br />
== Firmware ==<br />
<br />
The firmware files (FPGA bitstreams) for the ASIX SIGMA have been provided by the vendor under a [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=blob;f=asix-sigma/LICENSE.Sigma license which allows redistribution], and are available from the [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=summary sigrok-firmwares] repository:<br />
<br />
$ '''git clone git://sigrok.git.sourceforge.net/gitroot/sigrok/sigrok-firmwares'''<br />
<br />
In order to use the ASIX SIGMA in sigrok, you need to copy the firmware files to the correct sigrok directory, '''/usr/local/share/sigrok/firmware''' per default:<br />
<br />
$ '''cp sigrok-firmwares/asix-sigma/*.fw /usr/local/share/sigrok/firmware'''<br />
<br />
== Resources ==<br />
<br />
* [http://labs.ping.uio.no/2010/04/initial-support-for-asix-sigma-in-sigrok/ Initial support for Asix Sigma in Sigrok]<br />
* [http://labs.ping.uio.no/2009/09/sampi-a-logic-analyzer/ PING Labs: Sampi – A Logic Analyzer]<br />
* [http://www.flickr.com/photos/chlunde/3383669140/ flickr: ASIX SIGMA in chlunde's photostream] (photos and more information about the device)</div>Gushttps://sigrok.org/w/index.php?title=ASIX_SIGMA_/_SIGMA2&diff=487ASIX SIGMA / SIGMA22010-05-02T14:57:12Z<p>Gus: </p>
<hr />
<div>[[File:ASIX SIGMA.jpg|thumb|right|ASIX SIGMA.]]<br />
[[File:Sigma.jpg|thumb|right|ASIX SIGMA internals.]]<br />
<br />
The [http://tools.asix.net/dbg_sigma.htm ASIX SIGMA] is a 16 channel logic analyzer with sample rate support up to 200 MHz and with 256 Mbit on-board memory.<br />
<br />
It is supported by sigrok, and the necessary firmware files are generously provided by the vendor for distribution. As a result, the SIGMA works out of the box with sigrok. Trigger support has been implemented in 100 MHz and 200 MHz modes for rising/falling edges. Trigger features at lower sample rates are far more advanced and will be supported later.<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
!Samplerate<br />
!Number of probes<br />
!Trigger support<br />
|- bgcolor="#eeeeee"<br />
| 200 kHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#dddddd"<br />
| 250 kHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#eeeeee"<br />
| 500 kHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#dddddd"<br />
| 1 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#eeeeee"<br />
| 5 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#dddddd"<br />
| 10 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#eeeeee"<br />
| 25 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#dddddd"<br />
| 50 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#eeeeee"<br />
| 100 MHz<br />
| 8<br />
| Edge of one probe<br />
|- bgcolor="#dddddd"<br />
| 200 MHz<br />
| 4<br />
| Edge of one probe<br />
|}<br />
<br />
See [[ASIX SIGMA/Info]] for more detailed information on the device.<br />
<br />
== Example usage ==<br />
An example that captures from 4 probes, for 100ms at 10 MHz, with trigger condition pin 1 high, pin 2 rising, ping 3 low and ping 4 high is given below:<br />
<br />
sigrok-cli --triggers 1=1,2=r,3=0,4=1 --samples 5000000 --time 100 -o samplerate=10m -f bits -p 1-4<br />
<br />
== Firmware ==<br />
<br />
The firmware files (FPGA bitstreams) for the ASIX SIGMA have been provided by the vendor under a [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=blob;f=asix-sigma/LICENSE.Sigma license which allows redistribution], and are available from the [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=summary sigrok-firmwares] repository:<br />
<br />
$ '''git clone git://sigrok.git.sourceforge.net/gitroot/sigrok/sigrok-firmwares'''<br />
<br />
In order to use the ASIX SIGMA in sigrok, you need to copy the firmware files to the correct sigrok directory, '''/usr/local/share/sigrok/firmware''' per default:<br />
<br />
$ '''cp sigrok-firmwares/asix-sigma/*.fw /usr/local/share/sigrok/firmware'''<br />
<br />
== Resources ==<br />
<br />
* [http://labs.ping.uio.no/2010/04/initial-support-for-asix-sigma-in-sigrok/ Initial support for Asix Sigma in Sigrok]<br />
* [http://labs.ping.uio.no/2009/09/sampi-a-logic-analyzer/ PING Labs: Sampi – A Logic Analyzer]<br />
* [http://www.flickr.com/photos/chlunde/3383669140/ flickr: ASIX SIGMA in chlunde's photostream] (photos and more information about the device)</div>Gushttps://sigrok.org/w/index.php?title=ASIX_SIGMA_/_SIGMA2&diff=486ASIX SIGMA / SIGMA22010-05-02T14:51:37Z<p>Gus: </p>
<hr />
<div>[[File:ASIX SIGMA.jpg|thumb|right|ASIX SIGMA.]]<br />
[[File:Sigma.jpg|thumb|right|ASIX SIGMA internals.]]<br />
<br />
The [http://tools.asix.net/dbg_sigma.htm ASIX SIGMA] is a 16 channel logic analyzer with sample rate support up to 200 MHz and with 256 Mbit on-board memory.<br />
<br />
It is supported by sigrok, and the necessary firmware files are generously provided by the vendor for distribution. As a result, the SIGMA works out of the box with sigrok. Trigger support has been implemented in 100 MHz and 200 MHz modes for rising/falling edges. Trigger features at lower sample rates are far more advanced and will be supported later.<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
!Samplerate<br />
!Number of probes<br />
!Trigger support<br />
|- bgcolor="#eeeeee"<br />
| 200 kHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#dddddd"<br />
| 250 kHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#eeeeee"<br />
| 500 kHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#dddddd"<br />
| 1 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#eeeeee"<br />
| 5 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#dddddd"<br />
| 10 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#eeeeee"<br />
| 25 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#dddddd"<br />
| 50 MHz<br />
| 16<br />
| Edge of two probes, state<br />
|- bgcolor="#eeeeee"<br />
| 100 MHz<br />
| 8<br />
| Edge of one probe<br />
|- bgcolor="#dddddd"<br />
| 200 MHz<br />
| 4<br />
| Edge of one probe<br />
|}<br />
<br />
See [[ASIX SIGMA/Info]] for more detailed information on the device.<br />
<br />
== Firmware ==<br />
<br />
The firmware files (FPGA bitstreams) for the ASIX SIGMA have been provided by the vendor under a [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=blob;f=asix-sigma/LICENSE.Sigma license which allows redistribution], and are available from the [http://sigrok.git.sourceforge.net/git/gitweb.cgi?p=sigrok/sigrok-firmwares;a=summary sigrok-firmwares] repository:<br />
<br />
$ '''git clone git://sigrok.git.sourceforge.net/gitroot/sigrok/sigrok-firmwares'''<br />
<br />
In order to use the ASIX SIGMA in sigrok, you need to copy the firmware files to the correct sigrok directory, '''/usr/local/share/sigrok/firmware''' per default:<br />
<br />
$ '''cp sigrok-firmwares/asix-sigma/*.fw /usr/local/share/sigrok/firmware'''<br />
<br />
== Resources ==<br />
<br />
* [http://labs.ping.uio.no/2010/04/initial-support-for-asix-sigma-in-sigrok/ Initial support for Asix Sigma in Sigrok]<br />
* [http://labs.ping.uio.no/2009/09/sampi-a-logic-analyzer/ PING Labs: Sampi – A Logic Analyzer]<br />
* [http://www.flickr.com/photos/chlunde/3383669140/ flickr: ASIX SIGMA in chlunde's photostream] (photos and more information about the device)</div>Gushttps://sigrok.org/w/index.php?title=ASIX_SIGMA_/_SIGMA2&diff=466ASIX SIGMA / SIGMA22010-04-30T23:02:58Z<p>Gus: </p>
<hr />
<div>[[File:ASIX SIGMA.jpg|thumb|right|ASIX SIGMA.]]<br />
[[File:Sigma.jpg|thumb|right|ASIX SIGMA internals.]]<br />
<br />
The [http://tools.asix.net/dbg_sigma.htm ASIX SIGMA] is a 16 channel logic analyzer with sample rate support up to 200 MHz and with 256 Mbit on-board memory. It is supported by sigrok, and the necessary firmware files are generously provided by the vendor for distribution. As a result, the Sigma works out of the box with sigrok. Trigger support has been implemented in 100 and 200 MHz modes for rising/falling edges. Trigger features at lower sample rates are far more advanced and will be supported later.<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
!Samplerate<br />
!Number of probes<br />
|- bgcolor="#eeeeee"<br />
| 200 kHz<br />
| 16<br />
|- bgcolor="#dddddd"<br />
| 250 kHz<br />
| 16<br />
|- bgcolor="#eeeeee"<br />
| 500 kHz<br />
| 16<br />
|- bgcolor="#dddddd"<br />
| 1 MHz<br />
| 16<br />
|- bgcolor="#eeeeee"<br />
| 5 MHz<br />
| 16<br />
|- bgcolor="#dddddd"<br />
| 10 MHz<br />
| 16<br />
|- bgcolor="#eeeeee"<br />
| 25 MHz<br />
| 16<br />
|- bgcolor="#dddddd"<br />
| 50 MHz<br />
| 16<br />
|- bgcolor="#eeeeee"<br />
| 100 MHz<br />
| 8<br />
|- bgcolor="#dddddd"<br />
| 200 MHz<br />
| 4<br />
|}<br />
<br />
<br />
See [[ASIX SIGMA/Info]] for more detailed information on the device.<br />
<br />
== Resources ==<br />
<br />
* [http://labs.ping.uio.no/2010/04/initial-support-for-asix-sigma-in-sigrok/ Initial support for Asix Sigma in Sigrok]<br />
* [http://labs.ping.uio.no/2009/09/sampi-a-logic-analyzer/ PING Labs: Sampi – A Logic Analyzer]<br />
* [http://www.flickr.com/photos/chlunde/3383669140/ flickr: ASIX SIGMA in chlunde's photostream] (photos and more information about the device)</div>Gushttps://sigrok.org/w/index.php?title=ASIX_SIGMA_/_SIGMA2&diff=465ASIX SIGMA / SIGMA22010-04-30T23:01:19Z<p>Gus: </p>
<hr />
<div>[[File:ASIX SIGMA.jpg|thumb|right|ASIX SIGMA.]]<br />
[[File:Sigma.jpg|thumb|right|ASIX SIGMA internals.]]<br />
<br />
The [http://tools.asix.net/dbg_sigma.htm ASIX SIGMA] is a 16 channel logic analyzer with sample rate support up to 200 MHz and with 256 Mbit on-board memory. It is supported by sigrok, and the necessary firmware files are generously provided by the vendor for distribution with sigrok. As a result, the Sigma works out of the box with sigrok. Trigger support has been implemented in 100 and 200 MHz modes for rising/falling edges of probes. Trigger features at lower sample rates are far more advanced and will be supported later.<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
!Samplerate<br />
!Number of probes<br />
|- bgcolor="#eeeeee"<br />
| 200 kHz<br />
| 16<br />
|- bgcolor="#dddddd"<br />
| 250 kHz<br />
| 16<br />
|- bgcolor="#eeeeee"<br />
| 500 kHz<br />
| 16<br />
|- bgcolor="#dddddd"<br />
| 1 MHz<br />
| 16<br />
|- bgcolor="#eeeeee"<br />
| 5 MHz<br />
| 16<br />
|- bgcolor="#dddddd"<br />
| 10 MHz<br />
| 16<br />
|- bgcolor="#eeeeee"<br />
| 25 MHz<br />
| 16<br />
|- bgcolor="#dddddd"<br />
| 50 MHz<br />
| 16<br />
|- bgcolor="#eeeeee"<br />
| 100 MHz<br />
| 8<br />
|- bgcolor="#dddddd"<br />
| 200 MHz<br />
| 4<br />
|}<br />
<br />
<br />
See [[ASIX SIGMA/Info]] for more detailed information on the device.<br />
<br />
== Resources ==<br />
<br />
* [http://labs.ping.uio.no/2010/04/initial-support-for-asix-sigma-in-sigrok/ Initial support for Asix Sigma in Sigrok]<br />
* [http://labs.ping.uio.no/2009/09/sampi-a-logic-analyzer/ PING Labs: Sampi – A Logic Analyzer]<br />
* [http://www.flickr.com/photos/chlunde/3383669140/ flickr: ASIX SIGMA in chlunde's photostream] (photos and more information about the device)</div>Gushttps://sigrok.org/w/index.php?title=ASIX_SIGMA_/_SIGMA2&diff=464ASIX SIGMA / SIGMA22010-04-30T22:58:29Z<p>Gus: </p>
<hr />
<div>[[File:ASIX SIGMA.jpg|thumb|right|ASIX SIGMA.]]<br />
[[File:Sigma.jpg|thumb|right|ASIX SIGMA internals.]]<br />
<br />
The [http://tools.asix.net/dbg_sigma.htm ASIX SIGMA] is a 16 channel logic analyzer with sample rate support up to 200 MHz and with 256 Mbit on-board memory. It is supported by sigrok, and the necessary firmware files are generously provided by the vendor for distribution with sigrok. As a result, the Sigma works out of the box with sigrok. Trigger support has been implemented in 100 and 200 MHz modes for rising/falling edges of probes. Trigger features at lower sample rates are far more advanced and will be supported later.<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
!Samplerate<br />
!Number of probes<br />
|- bgcolor="#eeeeee"<br />
| 200 kHz<br />
| 16<br />
|- bgcolor="#dddddd"<br />
| 250 kHz<br />
| 16<br />
|- bgcolor="#eeeeee"<br />
| 500 kHz<br />
| 16<br />
|- bgcolor="#dddddd"<br />
| 1 MHz<br />
| 16<br />
|- bgcolor="#eeeeee"<br />
| 5 MHz<br />
| 16<br />
|- bgcolor="#dddddd"<br />
| 25 MHz<br />
| 16<br />
|- bgcolor="#eeeeee"<br />
| 50 MHz<br />
| 16<br />
|- bgcolor="#dddddd"<br />
| 100 MHz<br />
| 8<br />
|- bgcolor="#eeeeee"<br />
| 200 MHz<br />
| 4<br />
|}<br />
<br />
<br />
See [[ASIX SIGMA/Info]] for more detailed information on the device.<br />
<br />
== Resources ==<br />
<br />
* [http://labs.ping.uio.no/2010/04/initial-support-for-asix-sigma-in-sigrok/ Initial support for Asix Sigma in Sigrok]<br />
* [http://labs.ping.uio.no/2009/09/sampi-a-logic-analyzer/ PING Labs: Sampi – A Logic Analyzer]<br />
* [http://www.flickr.com/photos/chlunde/3383669140/ flickr: ASIX SIGMA in chlunde's photostream] (photos and more information about the device)</div>Gushttps://sigrok.org/w/index.php?title=Main_Page&diff=463Main Page2010-04-30T22:47:15Z<p>Gus: </p>
<hr />
<div><table width="100%" valign="top"><tr valign="top"><td width="80%"><br />
<br />
<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#cfdfff; align:right; border:1px solid #aabbcc;"><br />
The '''sigrok''' project aims at creating a portable, cross-platform, Free/Libre/Open-Source logic analyzer software that supports various (usually USB-based) logic analyzer hardware products. The code is licensed under the terms of the '''GNU GPL'''.<br />
</div><br />
<br />
== <span style="font-variant:small-caps">Design goals</span> ==<br />
<br />
* '''Broad hardware support'''. Supports a wide variety of logic analyzers from various vendors with different capabilities.<br />
* '''Cross-platform'''. Works on [[Linux]], [[Mac OS X]] and [[Windows]], and on many architectures including x86, ARM, Sparc and PowerPC.<br />
* '''Scriptable protocol decoding'''. Extendable with [[protocol decoders]] and analyzers written in Python.<br />
* '''Format support'''. Supports various [[Input output formats|input and output formats]] (raw, ASCII, hex, CSV, gnuplot, [http://en.wikipedia.org/wiki/Value_change_dump VCD], others).<br />
<br />
== <span style="font-variant:small-caps">Supported hardware</span> ==<br />
<br />
<gallery widths="120px" heights="70px"><br />
File:Saleae Logic.jpg|<small>'''[[Saleae Logic]]'''<br />(supported)</small><br />
File:Eeelec xla esla100.jpg|<small>'''[[EE Electronics XLA ESLA100|EE Electronics XLA/ESLA100]]''' (supported)</small><br />
File:ASIX SIGMA.jpg|<small>'''[[ASIX SIGMA]]''' (supported)</small><br />
File:Open workbench logic sniffer.jpg|<small>'''[[Openbench Logic Sniffer]]'''<br />(work in progress)</small><br />
File:Zeroplus Logic Cube.jpg|<small>'''[[ZEROPLUS Logic Cube LAP-C]]''' (work in progress)</small><br />
File:Cwav usbee sx.jpg|<small>'''[[CWAV USBee SX]]'''<br />(coming up)</small><br />
File:Braintechnology usb lps.jpg|<small>'''[[Braintechnology USB-LPS]]'''<br />(planned)</small><br />
File:Buspirate v3.jpg|<small>'''[[Buspirate]]'''<br />(planned)</small><br />
File:Intronix Logicport.jpg|<small>'''[[Intronix Logicport]]'''<br />(planned)</small><br />
</gallery><br />
<br />
<table width="100%"><br />
<tr style="vertical-align:top"><br />
<td style="vertical-align:top" width="30%"><br />
<br />
== [[File:Sigrok_stone.png]] <span style="font-variant:small-caps">Documentation</span> ==<br />
<br />
* [[Downloads]]<br />
* [[Supported hardware]]<br />
* [[Logic Analyzer Comparison]]<br />
* [[Command-line]]<br />
* [[GUI|Cross-platform GUI]]<br />
* [[Input output formats]]<br />
* [[Status]]<br />
* [[FAQ]]<br />
* [[News]]<br />
<br />
</td><td style="vertical-align:top" width="30%"><br />
<br />
== [[File:Sigrok_stone.png]] <span style="font-variant:small-caps">Development</span> ==<br />
<br />
* [[TODO]]<br />
* [[Design Ideas]]<br />
* [[Protocol decoders]]<br />
* Build info: [[Linux]], [[Mac OS X]], [[Windows]]<br />
* [[Formats and structures]]<br />
* [[Hardware plugin API]]<br />
* [[Output API]]<br />
<br />
</td><td style="vertical-align:top" width="40%"><br />
<br />
== [[File:Sigrok_stone.png]] <span style="font-variant:small-caps">Getting in touch</span> ==<br />
<br />
* Mailing lists: [https://lists.sourceforge.net/lists/listinfo/sigrok-devel sigrok-devel] ([http://news.gmane.org/gmane.comp.debugging.sigrok.devel archive]), [https://lists.sourceforge.net/lists/listinfo/sigrok-commits sigrok-commits]<br />
* IRC: '''[irc://chat.freenode.net/sigrok #sigrok]''' on [http://www.freenode.net Freenode]<br />
* identi.ca: [http://www.identi.ca/group/sigrok sigrok group]<br />
* Sites: [http://sourceforge.net/projects/sigrok/ SF], [http://freshmeat.net/projects/sigrok Fm], [https://www.ohloh.net/p/sigrok ohloh], [http://delicious.com/url/d8996d567839064c799ac217b263b2c8 del.icio.us]<br />
* [[Press]]<br />
* [[Logo]]<br />
<br />
</td><br />
</tr><br />
</table><br />
<br />
</td><td width="20%"><br />
<br />
[[File:Sigrok linux.png|center|thumb|sigrok-gui on Linux]]<br />
<br />
<br clear=all /><br />
<br />
'''<span style="font-variant:small-caps; font-size:120%">[[File:Sigrok_stone.png]] [[News]]</span>'''<hr /><br />
<!-- Please always make this list 7 items long (7 most recent news items). --><br />
<small><br />
* '''2010/05/01:''' [[ASIX SIGMA]] support<br />
* '''2010/04/06:''' VCD and Gnuplot output<br />
* '''2010/04/01:''' [[ZEROPLUS Logic Cube LAP-C]] support<br />
* '''2010/03/30:''' libsigrokdecode started<br />
* '''2010/03/19:''' GUI: i18n support<br />
* '''2010/03/17:''' Session save support<br />
* '''2010/03/16:''' GUI started<br />
* '''2010/03/14:''' Official project start<br />
</small><br />
<br />
</td></tr></table><br />
<br />
<br />
----<br />
'''IMPORTANT: Please note that (unless explicitly specified otherwise) all contents in this wiki (including text and images) are released to the <span style="color:red">CC-BY-SA 3.0</span>. If you don't want that, please explicitly specify another free-ish license when adding pages or images to the wiki!'''<br />
__NOTOC__<br />
__NOEDITSECTION__</div>Gushttps://sigrok.org/w/index.php?title=ASIX_SIGMA_/_SIGMA2&diff=437ASIX SIGMA / SIGMA22010-04-27T21:06:17Z<p>Gus: </p>
<hr />
<div>[[File:Sigma.jpg|thumb|right|ASIX SIGMA]]<br />
<br />
The [http://tools.asix.net/dbg_sigma.htm ASIX SIGMA] is a 16 channel logic analyzer.<br />
<br />
See [[ASIX SIGMA/Info]] for more detailed information on the device.<br />
<br />
== Resources ==<br />
<br />
* [http://labs.ping.uio.no/2010/04/initial-support-for-asix-sigma-in-sigrok/ Initial support for Asix Sigma in Sigrok]<br />
* [http://labs.ping.uio.no/2009/09/sampi-a-logic-analyzer/ PING Labs: Sampi – A Logic Analyzer]<br />
* [http://www.flickr.com/photos/chlunde/3383669140/ flickr: ASIX SIGMA in chlunde's photostream] (photos and more information about the device)</div>Gushttps://sigrok.org/w/index.php?title=User:Gus&diff=436User:Gus2010-04-25T20:16:42Z<p>Gus: Created page with 'I also use the nick haavares'</p>
<hr />
<div>I also use the nick haavares</div>Gus