sigrok - User contributions [en]

File:Kingst kqs3506 la16100 schematic v6.png

2014-06-21T12:39:00Z

Greg: Greg uploaded a new version of "File:Kingst kqs3506 la16100 schematic v6.png": fix typo

== Summary ==
schematic of v6 pcb, should be correct and complete, FPGA GND not drawn, other FPGA pins probably NC
== Licensing ==
{{PD}}

KingST KQS3506-LA16100

2014-06-21T12:25:10Z

Greg: /* Photos */

{{Infobox logic analyzer
| image = [[File:Kingst kqs3506 la16100.png|180px]]
| name = KingST KQS3506-LA16100
| status = supported
| source_code_dir = saleae-logic16
| channels = 3/6/9/16
| samplerate = 100/50/32/16MHz
| samplerate_state = —
| triggers = none (SW-only)
| voltages = -0.9V — 6V
| threshold = configurable: for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V for 5V systems: VIH=3.6V, VIL=1.4V
| memory = none
| compression = yes
| website = [http://item.taobao.com/item.htm?id=20369792793 taobao.com]
}}

The '''KingST KQS3506-LA16100''' is a USB-based, 16-channel logic analyzer with 100/50/32/16MHz sampling rate (at 3/6/9/16 enabled channels).

This is a clone of the [[Saleae Logic16]].

See [[KingST KQS3506-LA16100/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

== Hardware ==

* '''FPGA''': [http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/spartan-3a.html Xilinx Spartan-3A XC3S200A], 200K gates ([http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf datasheet])
* '''CPLD''': [http://www.altera.com/literature/lit-m3k.jsp Altera EPM3032A], 600 gates, 32 macrocells ([http://www.altera.com/literature/ds/m3000a.pdf datasheet], [http://www.altera.com/literature/dp/max3k/epm3032a.pdf pinout]).
* '''USB interface chip''': [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A-56PVXC (FX2LP)] ([http://www.cypress.com/?docID=34060 datasheet])
* '''I2C EEPROM''': [http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en010810 Microchip 24LC02B] ([http://ww1.microchip.com/downloads/en/DeviceDoc/21709J.pdf datasheet])
* '''3.3V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-3.3] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''1.2V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-1.2] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''Crystal''': 24.000

'''Pinouts and connections:'''

'''I2C EEPROM:'''

The Microchip 24LC02B is connected to the Cypress FX2. The '''WP''' pin of the EEPROM can be jumpered to low or high, in order to write-protect it (or not). The address pins (A0-A2) are all connected to GND, which makes the I2C slave address of the EEPROM 0x50.


{{chip_8pin
| 1=(GND) A0
| 2=(GND) A1
| 3=(GND) A2
| 4=GND
| 5=SDA (FX2 SDA)
| 6=SCL (FX2 SCL)
| 7=WP (jumper W2)
| 8=VCC (3.3V)
}}


'''CLPD:'''

The Altera EPM3032A JTAG pins are available on the '''J3''' pin header.

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!1
!2
!3
!4
!5
!6
!7
!8
!9
!10
!11

|-
| JTAG TDI
| I/O (FX2 PA7)
| I/O (FX2 PA6)
| GND
| I/O (FX2 PA5)
| I/O (FX2 PA4)
| JTAG TMS
| I/O (FX2 PA3)
| VCC
| I/O (FX2 PA2)
| GND

|-
!12
!13
!14
!15
!16
!17
!18
!19
!20
!21
!22

|-
| I/O (FX2 PA1)
| I/O (FX2 PA0)
| I/O (FPGA PROG_B)
| I/O (FPGA 94, IO_L05N_0)
| GND
| VCC
| I/O (FPGA 85, IO_L03P_0)
| I/O (FX2 CTL2)
| I/O (FX2 CTL1)
| I/O (FX2 CTL0)
| I/O (FPGA 51, DIN/MISO)

|-
!23
!24
!25
!26
!27
!28
!29
!30
!31
!32
!33

|-
| I/O (NC?)
| GND
| I/O (FPGA 97, IP0)
| JTAG TCK
| I/O (FPGA 53, CCLK)
| I/O (NC?)
| VCC
| GND
| I/O (FPGA 3, IO_L01P_3)
| JTAG TDO
| I/O (NC?)

|-
!34
!35
!36
!37
!38
!39
!40
!41
!42
!43
!44

|-
| I/O (NC?)
| I/O (NC?)
| GND
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)
| VCC
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)

|}

'''JTAG header (CPLD):'''

The '''J3''' pin header is a JTAG connector wired to the CPLD (it is '''not''' additionally wired to the FPGA in a JTAG chain). The pins are (from left to right):

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!1
!2
!3
!4
!5
!6

|-
| TMS
| TDI
| TCK
| TDO
| GND
| 3.3V

|}

== Photos ==

'''Revision 5.0''':

<gallery>
File:Kingst kqs3506 la16100 package.jpg|Package
File:Kingst kqs3506 la16100 paper.jpg|Paper
File:Kingst kqs3506 la16100 device top.jpg|Device, top
File:Kingst kqs3506 la16100 device bottom.jpg|Device, bottom
File:Kingst kqs3506 la16100 device usb.jpg|Device, USB
File:Kingst kqs3506 la16100 device connector.jpg|Device, connector
File:Kingst kqs3506 la16100 pcb top.jpg|PCB, top
File:Kingst kqs3506 la16100 pcb bottom.jpg|PCB, bottom
File:Kingst kqs3506 la16100 xilinx spartan xc3s200a.jpg|Xilinx XC3S200A
File:Kingst kqs3506 la16100 altera epm3032a.jpg|Altera EPM3032A
File:Kingst kqs3506 la16100 cypress fx2.jpg|Cypress FX2
File:Kingst kqs3506 la16100 at88sc0104 silkscreen.jpg|AT88SC0104 silkscreen
File:Kingst kqs3506 la16100 microchip 24lc02b.jpg|Microchip 24LC02B
File:Kingst kqs3506 la16100 inputstage 2.jpg|Input stage, 1
File:Kingst kqs3506 la16100 input stage1.jpg|Input stage, 2
File:Kingst kqs3506 la16100 ams1117 33.jpg|AMS1117-3.3
File:Kingst kqs3506 la16100 ams1117 12.jpg|AMS1117-1.2
</gallery>

'''Revision 6.0''':

<gallery>
File:Kingst kqs3506 la16100 pcb v6 top.jpg|PCB, top
File:Kingst kqs3506 la16100 pcb v6 bottom.jpg|PCB, bottom
File:Kingst kqs3506 la16100 schematic v6.png|Schematic drawn from PCB
</gallery>

== Protocol ==

See [[Saleae_Logic16#Protocol]].

== Resources ==

* [http://kstmcu.taobao.com/ kstmcu.taobao.com]
* [http://www.kingst.org/forum/index kingst.org forum]
* [http://translate.google.com/translate?sl=zh-CN&tl=en&js=n&prev=_t&hl=de&ie=UTF-8&eotf=1&u=http%3A%2F%2Fwww.mcu123.com%2Fnews%2FArticle%2FPC%2FPCB%2F201210%2F4905.html&act=url MCU123 article]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:In progress]]

File:Kingst kqs3506 la16100 schematic v6.png

2014-06-21T12:24:27Z

Greg: schematic of v6 pcb, should be correct and complete, FPGA GND not drawn, other FPGA pins probably NC

== Summary ==
schematic of v6 pcb, should be correct and complete, FPGA GND not drawn, other FPGA pins probably NC
== Licensing ==
{{PD}}

KingST KQS3506-LA16100

2014-06-20T22:13:42Z

Greg: /* Photos */

{{Infobox logic analyzer
| image = [[File:Kingst kqs3506 la16100.png|180px]]
| name = KingST KQS3506-LA16100
| status = supported
| source_code_dir = saleae-logic16
| channels = 3/6/9/16
| samplerate = 100/50/32/16MHz
| samplerate_state = —
| triggers = none (SW-only)
| voltages = -0.9V — 6V
| threshold = configurable: for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V for 5V systems: VIH=3.6V, VIL=1.4V
| memory = none
| compression = yes
| website = [http://item.taobao.com/item.htm?id=20369792793 taobao.com]
}}

The '''KingST KQS3506-LA16100''' is a USB-based, 16-channel logic analyzer with 100/50/32/16MHz sampling rate (at 3/6/9/16 enabled channels).

This is a clone of the [[Saleae Logic16]].

See [[KingST KQS3506-LA16100/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

== Hardware ==

* '''FPGA''': [http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/spartan-3a.html Xilinx Spartan-3A XC3S200A], 200K gates ([http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf datasheet])
* '''CPLD''': [http://www.altera.com/literature/lit-m3k.jsp Altera EPM3032A], 600 gates, 32 macrocells ([http://www.altera.com/literature/ds/m3000a.pdf datasheet], [http://www.altera.com/literature/dp/max3k/epm3032a.pdf pinout]).
* '''USB interface chip''': [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A-56PVXC (FX2LP)] ([http://www.cypress.com/?docID=34060 datasheet])
* '''I2C EEPROM''': [http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en010810 Microchip 24LC02B] ([http://ww1.microchip.com/downloads/en/DeviceDoc/21709J.pdf datasheet])
* '''3.3V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-3.3] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''1.2V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-1.2] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''Crystal''': 24.000

'''Pinouts and connections:'''

'''I2C EEPROM:'''

The Microchip 24LC02B is connected to the Cypress FX2. The '''WP''' pin of the EEPROM can be jumpered to low or high, in order to write-protect it (or not). The address pins (A0-A2) are all connected to GND, which makes the I2C slave address of the EEPROM 0x50.


{{chip_8pin
| 1=(GND) A0
| 2=(GND) A1
| 3=(GND) A2
| 4=GND
| 5=SDA (FX2 SDA)
| 6=SCL (FX2 SCL)
| 7=WP (jumper W2)
| 8=VCC (3.3V)
}}


'''CLPD:'''

The Altera EPM3032A JTAG pins are available on the '''J3''' pin header.

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!1
!2
!3
!4
!5
!6
!7
!8
!9
!10
!11

|-
| JTAG TDI
| I/O (FX2 PA7)
| I/O (FX2 PA6)
| GND
| I/O (FX2 PA5)
| I/O (FX2 PA4)
| JTAG TMS
| I/O (FX2 PA3)
| VCC
| I/O (FX2 PA2)
| GND

|-
!12
!13
!14
!15
!16
!17
!18
!19
!20
!21
!22

|-
| I/O (FX2 PA1)
| I/O (FX2 PA0)
| I/O (FPGA PROG_B)
| I/O (FPGA 94, IO_L05N_0)
| GND
| VCC
| I/O (FPGA 85, IO_L03P_0)
| I/O (FX2 CTL2)
| I/O (FX2 CTL1)
| I/O (FX2 CTL0)
| I/O (FPGA 51, DIN/MISO)

|-
!23
!24
!25
!26
!27
!28
!29
!30
!31
!32
!33

|-
| I/O (NC?)
| GND
| I/O (FPGA 97, IP0)
| JTAG TCK
| I/O (FPGA 53, CCLK)
| I/O (NC?)
| VCC
| GND
| I/O (FPGA 3, IO_L01P_3)
| JTAG TDO
| I/O (NC?)

|-
!34
!35
!36
!37
!38
!39
!40
!41
!42
!43
!44

|-
| I/O (NC?)
| I/O (NC?)
| GND
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)
| VCC
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)

|}

'''JTAG header (CPLD):'''

The '''J3''' pin header is a JTAG connector wired to the CPLD (it is '''not''' additionally wired to the FPGA in a JTAG chain). The pins are (from left to right):

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!1
!2
!3
!4
!5
!6

|-
| TMS
| TDI
| TCK
| TDO
| GND
| 3.3V

|}

== Photos ==

'''Revision 5.0''':

<gallery>
File:Kingst kqs3506 la16100 package.jpg|Package
File:Kingst kqs3506 la16100 paper.jpg|Paper
File:Kingst kqs3506 la16100 device top.jpg|Device, top
File:Kingst kqs3506 la16100 device bottom.jpg|Device, bottom
File:Kingst kqs3506 la16100 device usb.jpg|Device, USB
File:Kingst kqs3506 la16100 device connector.jpg|Device, connector
File:Kingst kqs3506 la16100 pcb top.jpg|PCB, top
File:Kingst kqs3506 la16100 pcb bottom.jpg|PCB, bottom
File:Kingst kqs3506 la16100 xilinx spartan xc3s200a.jpg|Xilinx XC3S200A
File:Kingst kqs3506 la16100 altera epm3032a.jpg|Altera EPM3032A
File:Kingst kqs3506 la16100 cypress fx2.jpg|Cypress FX2
File:Kingst kqs3506 la16100 at88sc0104 silkscreen.jpg|AT88SC0104 silkscreen
File:Kingst kqs3506 la16100 microchip 24lc02b.jpg|Microchip 24LC02B
File:Kingst kqs3506 la16100 inputstage 2.jpg|Input stage, 1
File:Kingst kqs3506 la16100 input stage1.jpg|Input stage, 2
File:Kingst kqs3506 la16100 ams1117 33.jpg|AMS1117-3.3
File:Kingst kqs3506 la16100 ams1117 12.jpg|AMS1117-1.2
</gallery>

'''Revision 6.0''':

<gallery>
File:Kingst kqs3506 la16100 pcb v6 top.jpg|PCB, top
File:Kingst kqs3506 la16100 pcb v6 bottom.jpg|PCB, bottom
</gallery>

== Protocol ==

See [[Saleae_Logic16#Protocol]].

== Resources ==

* [http://kstmcu.taobao.com/ kstmcu.taobao.com]
* [http://www.kingst.org/forum/index kingst.org forum]
* [http://translate.google.com/translate?sl=zh-CN&tl=en&js=n&prev=_t&hl=de&ie=UTF-8&eotf=1&u=http%3A%2F%2Fwww.mcu123.com%2Fnews%2FArticle%2FPC%2FPCB%2F201210%2F4905.html&act=url MCU123 article]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:In progress]]

KingST KQS3506-LA16100

2014-06-19T15:19:41Z

Greg: /* Photos */

{{Infobox logic analyzer
| image = [[File:Kingst kqs3506 la16100.png|180px]]
| name = KingST KQS3506-LA16100
| status = supported
| source_code_dir = saleae-logic16
| channels = 3/6/9/16
| samplerate = 100/50/32/16MHz
| samplerate_state = —
| triggers = none (SW-only)
| voltages = -0.9V — 6V
| threshold = configurable: for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V for 5V systems: VIH=3.6V, VIL=1.4V
| memory = none
| compression = yes
| website = [http://item.taobao.com/item.htm?id=20369792793 taobao.com]
}}

The '''KingST KQS3506-LA16100''' is a USB-based, 16-channel logic analyzer with 100/50/32/16MHz sampling rate (at 3/6/9/16 enabled channels).

This is a clone of the [[Saleae Logic16]].

See [[KingST KQS3506-LA16100/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

== Hardware ==

* '''FPGA''': [http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/spartan-3a.html Xilinx Spartan-3A XC3S200A], 200K gates ([http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf datasheet])
* '''CPLD''': [http://www.altera.com/literature/lit-m3k.jsp Altera EPM3032A], 600 gates, 32 macrocells ([http://www.altera.com/literature/ds/m3000a.pdf datasheet], [http://www.altera.com/literature/dp/max3k/epm3032a.pdf pinout]).
* '''USB interface chip''': [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A-56PVXC (FX2LP)] ([http://www.cypress.com/?docID=34060 datasheet])
* '''I2C EEPROM''': [http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en010810 Microchip 24LC02B] ([http://ww1.microchip.com/downloads/en/DeviceDoc/21709J.pdf datasheet])
* '''3.3V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-3.3] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''1.2V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-1.2] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''Crystal''': 24.000

'''Pinouts and connections:'''

'''I2C EEPROM:'''

The Microchip 24LC02B is connected to the Cypress FX2. The '''WP''' pin of the EEPROM can be jumpered to low or high, in order to write-protect it (or not). The address pins (A0-A2) are all connected to GND, which makes the I2C slave address of the EEPROM 0x50.


{{chip_8pin
| 1=(GND) A0
| 2=(GND) A1
| 3=(GND) A2
| 4=GND
| 5=SDA (FX2 SDA)
| 6=SCL (FX2 SCL)
| 7=WP (jumper W2)
| 8=VCC (3.3V)
}}


'''CLPD:'''

The Altera EPM3032A JTAG pins are available on the '''J3''' pin header.

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!1
!2
!3
!4
!5
!6
!7
!8
!9
!10
!11

|-
| JTAG TDI
| I/O (FX2 PA7)
| I/O (FX2 PA6)
| GND
| I/O (FX2 PA5)
| I/O (FX2 PA4)
| JTAG TMS
| I/O (FX2 PA3)
| VCC
| I/O (FX2 PA2)
| GND

|-
!12
!13
!14
!15
!16
!17
!18
!19
!20
!21
!22

|-
| I/O (FX2 PA1)
| I/O (FX2 PA0)
| I/O (FPGA PROG_B)
| I/O (FPGA 94, IO_L05N_0)
| GND
| VCC
| I/O (FPGA 85, IO_L03P_0)
| I/O (FX2 CTL2)
| I/O (FX2 CTL1)
| I/O (FX2 CTL0)
| I/O (FPGA 51, DIN/MISO)

|-
!23
!24
!25
!26
!27
!28
!29
!30
!31
!32
!33

|-
| I/O (NC?)
| GND
| I/O (FPGA 97, IP0)
| JTAG TCK
| I/O (FPGA 53, CCLK)
| I/O (NC?)
| VCC
| GND
| I/O (FPGA 3, IO_L01P_3)
| JTAG TDO
| I/O (NC?)

|-
!34
!35
!36
!37
!38
!39
!40
!41
!42
!43
!44

|-
| I/O (NC?)
| I/O (NC?)
| GND
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)
| VCC
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)

|}

'''JTAG header (CPLD):'''

The '''J3''' pin header is a JTAG connector wired to the CPLD (it is '''not''' additionally wired to the FPGA in a JTAG chain). The pins are (from left to right):

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!1
!2
!3
!4
!5
!6

|-
| TMS
| TDI
| TCK
| TDO
| GND
| 3.3V

|}

== Photos ==

<gallery>
File:Kingst kqs3506 la16100 pcb v6 top.jpg
File:Kingst kqs3506 la16100 pcb v6 bottom.jpg
</gallery>

== Protocol ==

See [[Saleae_Logic16#Protocol]].

== Resources ==

* [http://kstmcu.taobao.com/ kstmcu.taobao.com]
* [http://www.kingst.org/forum/index kingst.org forum]
* [http://translate.google.com/translate?sl=zh-CN&tl=en&js=n&prev=_t&hl=de&ie=UTF-8&eotf=1&u=http%3A%2F%2Fwww.mcu123.com%2Fnews%2FArticle%2FPC%2FPCB%2F201210%2F4905.html&act=url MCU123 article]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:In progress]]

File:Kingst kqs3506 la16100 pcb v6 top.jpg

2014-06-19T15:19:21Z

Greg:

== Licensing ==
{{PD}}

KingST KQS3506-LA16100

2014-06-19T12:40:09Z

Greg: /* Photos */

{{Infobox logic analyzer
| image = [[File:Kingst kqs3506 la16100.png|180px]]
| name = KingST KQS3506-LA16100
| status = supported
| source_code_dir = saleae-logic16
| channels = 3/6/9/16
| samplerate = 100/50/32/16MHz
| samplerate_state = —
| triggers = none (SW-only)
| voltages = -0.9V — 6V
| threshold = configurable: for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V for 5V systems: VIH=3.6V, VIL=1.4V
| memory = none
| compression = yes
| website = [http://item.taobao.com/item.htm?id=20369792793 taobao.com]
}}

The '''KingST KQS3506-LA16100''' is a USB-based, 16-channel logic analyzer with 100/50/32/16MHz sampling rate (at 3/6/9/16 enabled channels).

This is a clone of the [[Saleae Logic16]].

See [[KingST KQS3506-LA16100/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

== Hardware ==

* '''FPGA''': [http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/spartan-3a.html Xilinx Spartan-3A XC3S200A], 200K gates ([http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf datasheet])
* '''CPLD''': [http://www.altera.com/literature/lit-m3k.jsp Altera EPM3032A], 600 gates, 32 macrocells ([http://www.altera.com/literature/ds/m3000a.pdf datasheet], [http://www.altera.com/literature/dp/max3k/epm3032a.pdf pinout]).
* '''USB interface chip''': [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A-56PVXC (FX2LP)] ([http://www.cypress.com/?docID=34060 datasheet])
* '''I2C EEPROM''': [http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en010810 Microchip 24LC02B] ([http://ww1.microchip.com/downloads/en/DeviceDoc/21709J.pdf datasheet])
* '''3.3V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-3.3] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''1.2V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-1.2] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''Crystal''': 24.000

'''Pinouts and connections:'''

'''I2C EEPROM:'''

The Microchip 24LC02B is connected to the Cypress FX2. The '''WP''' pin of the EEPROM can be jumpered to low or high, in order to write-protect it (or not). The address pins (A0-A2) are all connected to GND, which makes the I2C slave address of the EEPROM 0x50.


{{chip_8pin
| 1=(GND) A0
| 2=(GND) A1
| 3=(GND) A2
| 4=GND
| 5=SDA (FX2 SDA)
| 6=SCL (FX2 SCL)
| 7=WP (jumper W2)
| 8=VCC (3.3V)
}}


'''CLPD:'''

The Altera EPM3032A JTAG pins are available on the '''J3''' pin header.

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!1
!2
!3
!4
!5
!6
!7
!8
!9
!10
!11

|-
| JTAG TDI
| I/O (FX2 PA7)
| I/O (FX2 PA6)
| GND
| I/O (FX2 PA5)
| I/O (FX2 PA4)
| JTAG TMS
| I/O (FX2 PA3)
| VCC
| I/O (FX2 PA2)
| GND

|-
!12
!13
!14
!15
!16
!17
!18
!19
!20
!21
!22

|-
| I/O (FX2 PA1)
| I/O (FX2 PA0)
| I/O (FPGA PROG_B)
| I/O (FPGA 94, IO_L05N_0)
| GND
| VCC
| I/O (FPGA 85, IO_L03P_0)
| I/O (FX2 CTL2)
| I/O (FX2 CTL1)
| I/O (FX2 CTL0)
| I/O (FPGA 51, DIN/MISO)

|-
!23
!24
!25
!26
!27
!28
!29
!30
!31
!32
!33

|-
| I/O (NC?)
| GND
| I/O (FPGA 97, IP0)
| JTAG TCK
| I/O (FPGA 53, CCLK)
| I/O (NC?)
| VCC
| GND
| I/O (FPGA 3, IO_L01P_3)
| JTAG TDO
| I/O (NC?)

|-
!34
!35
!36
!37
!38
!39
!40
!41
!42
!43
!44

|-
| I/O (NC?)
| I/O (NC?)
| GND
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)
| VCC
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)

|}

'''JTAG header (CPLD):'''

The '''J3''' pin header is a JTAG connector wired to the CPLD (it is '''not''' additionally wired to the FPGA in a JTAG chain). The pins are (from left to right):

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!1
!2
!3
!4
!5
!6

|-
| TMS
| TDI
| TCK
| TDO
| GND
| 3.3V

|}

== Photos ==

<gallery>
File:Kingst kqs3506 la16100 pcb v6 top.png
File:Kingst kqs3506 la16100 pcb v6 bottom.jpg
</gallery>

== Protocol ==

See [[Saleae_Logic16#Protocol]].

== Resources ==

* [http://kstmcu.taobao.com/ kstmcu.taobao.com]
* [http://www.kingst.org/forum/index kingst.org forum]
* [http://translate.google.com/translate?sl=zh-CN&tl=en&js=n&prev=_t&hl=de&ie=UTF-8&eotf=1&u=http%3A%2F%2Fwww.mcu123.com%2Fnews%2FArticle%2FPC%2FPCB%2F201210%2F4905.html&act=url MCU123 article]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:In progress]]

File:Kingst kqs3506 la16100 pcb v6 bottom.jpg

2014-06-19T12:39:57Z

Greg:

KingST KQS3506-LA16100

2014-06-18T10:43:13Z

Greg: /* Photos */

{{Infobox logic analyzer
| image = [[File:Kingst kqs3506 la16100.png|180px]]
| name = KingST KQS3506-LA16100
| status = supported
| source_code_dir = saleae-logic16
| channels = 3/6/9/16
| samplerate = 100/50/32/16MHz
| samplerate_state = —
| triggers = none (SW-only)
| voltages = -0.9V — 6V
| threshold = configurable: for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V for 5V systems: VIH=3.6V, VIL=1.4V
| memory = none
| compression = yes
| website = [http://item.taobao.com/item.htm?id=20369792793 taobao.com]
}}

The '''KingST KQS3506-LA16100''' is a USB-based, 16-channel logic analyzer with 100/50/32/16MHz sampling rate (at 3/6/9/16 enabled channels).

This is a clone of the [[Saleae Logic16]].

See [[KingST KQS3506-LA16100/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

== Hardware ==

* '''FPGA''': [http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/spartan-3a.html Xilinx Spartan-3A XC3S200A], 200K gates ([http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf datasheet])
* '''CPLD''': [http://www.altera.com/literature/lit-m3k.jsp Altera EPM3032A], 600 gates, 32 macrocells ([http://www.altera.com/literature/ds/m3000a.pdf datasheet], [http://www.altera.com/literature/dp/max3k/epm3032a.pdf pinout]).
* '''USB interface chip''': [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A-56PVXC (FX2LP)] ([http://www.cypress.com/?docID=34060 datasheet])
* '''I2C EEPROM''': [http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en010810 Microchip 24LC02B] ([http://ww1.microchip.com/downloads/en/DeviceDoc/21709J.pdf datasheet])
* '''3.3V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-3.3] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''1.2V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-1.2] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''Crystal''': 24.000

'''Pinouts and connections:'''

'''I2C EEPROM:'''

The Microchip 24LC02B is connected to the Cypress FX2. The '''WP''' pin of the EEPROM can be jumpered to low or high, in order to write-protect it (or not). The address pins (A0-A2) are all connected to GND, which makes the I2C slave address of the EEPROM 0x50.


{{chip_8pin
| 1=(GND) A0
| 2=(GND) A1
| 3=(GND) A2
| 4=GND
| 5=SDA (FX2 SDA)
| 6=SCL (FX2 SCL)
| 7=WP (jumper W2)
| 8=VCC (3.3V)
}}


'''CLPD:'''

The Altera EPM3032A JTAG pins are available on the '''J3''' pin header.

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!1
!2
!3
!4
!5
!6
!7
!8
!9
!10
!11

|-
| JTAG TDI
| I/O (FX2 PA7)
| I/O (FX2 PA6)
| GND
| I/O (FX2 PA5)
| I/O (FX2 PA4)
| JTAG TMS
| I/O (FX2 PA3)
| VCC
| I/O (FX2 PA2)
| GND

|-
!12
!13
!14
!15
!16
!17
!18
!19
!20
!21
!22

|-
| I/O (FX2 PA1)
| I/O (FX2 PA0)
| I/O (FPGA PROG_B)
| I/O (FPGA 94, IO_L05N_0)
| GND
| VCC
| I/O (FPGA 85, IO_L03P_0)
| I/O (FX2 CTL2)
| I/O (FX2 CTL1)
| I/O (FX2 CTL0)
| I/O (FPGA 51, DIN/MISO)

|-
!23
!24
!25
!26
!27
!28
!29
!30
!31
!32
!33

|-
| I/O (NC?)
| GND
| I/O (FPGA 97, IP0)
| JTAG TCK
| I/O (FPGA 53, CCLK)
| I/O (NC?)
| VCC
| GND
| I/O (FPGA 3, IO_L01P_3)
| JTAG TDO
| I/O (NC?)

|-
!34
!35
!36
!37
!38
!39
!40
!41
!42
!43
!44

|-
| I/O (NC?)
| I/O (NC?)
| GND
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)
| VCC
| I/O (NC?)
| I/O (NC?)
| I/O (NC?)

|}

'''JTAG header (CPLD):'''

The '''J3''' pin header is a JTAG connector wired to the CPLD (it is '''not''' additionally wired to the FPGA in a JTAG chain). The pins are (from left to right):

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!1
!2
!3
!4
!5
!6

|-
| TMS
| TDI
| TCK
| TDO
| GND
| 3.3V

|}

== Photos ==

<gallery>
File:Kingst kqs3506 la16100 pcb v6 top.png
File:Kingst kqs3506 la16100 pcb v6 bottom.png
</gallery>

== Protocol ==

See [[Saleae_Logic16#Protocol]].

== Resources ==

* [http://kstmcu.taobao.com/ kstmcu.taobao.com]
* [http://www.kingst.org/forum/index kingst.org forum]
* [http://translate.google.com/translate?sl=zh-CN&tl=en&js=n&prev=_t&hl=de&ie=UTF-8&eotf=1&u=http%3A%2F%2Fwww.mcu123.com%2Fnews%2FArticle%2FPC%2FPCB%2F201210%2F4905.html&act=url MCU123 article]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:In progress]]

File:Kingst kqs3506 la16100 pcb v6 top.png

2014-06-18T10:42:51Z

Greg:

== Licensing ==
{{PD}}

File:Kingst kqs3506 la16100 pcb v6 bottom.png

2014-06-18T10:40:44Z

Greg:

== Licensing ==
{{PD}}