sigrok - User contributions [en]

File:CoLA cap.zip

2019-12-29T12:49:00Z

Danny W:

== Licensing ==
{{CC-BY-SA-3.0}}

CoLA

2019-12-29T12:48:35Z

Danny W:

{{Infobox logic analyzer
| image = [[File:IMG 20191206 105430.jpg|180px]]
| name = CoLA - Compact Logic Analyzer
| status = planned
| source_code_dir = -
| channels = 96/48/24
| samplerate = 25MHz/50MHz/100MHz
| samplerate_state = ?
| triggers = 32 hardware, 96 bit masked pattern
| voltages = 1.65V - 5.5V continuously
| threshold = ?
| memory = 262144 bytes
| compression = RLE, frame omission
| website = -
}}

== Introduction ==

CoLA - Compact Logic Analyzer is an USB3.0 based 96ch/25MHz, 48ch/50MHz or 24ch/100MHz logic analyzer/pattern generator, with built-in hardware pattern triggers, supporting all logic levels from 1.65V to 5.5V. It uses an Intel/Altera Cyclone V FPGA for digital aquisition and FTDI FT601B for 5Gbps USB3.0 support. To limit data transfers, it uses Run Length Encoding (RLE) as well as frame omission. Its compact design and versatility, as well as future upgradability and a DIY approach makes CoLA an interesting project.

== Theory ==

The aquisition of digital levels are done by an FPGA. The Intel/Altera Cyclone V series have sufficient speed and resources. Although versions with High Speed Serial Interfaces (HSSI's) and an embedded ARM Host Processor System (HPS) exist, a part without these is selected. The 5CEBA5F23C8 has 29.000 ALM / 77.000 LE's and 446 M10K memory blocks of resources. For now, the 150 DSP hardware multiplier modules are not used, but that can change in the future. The FPGA is also equipped with 6 PLL blocks, but only one is used.

To transfer all data to a computer, a part from FTDI is used to communicate over the USB bus. The FT601 has a 5Gbps transceiver, of which 3200Mbps can be used by the chip. The USB chip interfaces to the FPGA by means of a parallel data bus, 32 bits at 100MHz. It uses an external 30MHz crystal to generate all frequencies, and the FPGA inputs the 100MHz clock as its main clock frequency. Apart from the 32 data bits, some other arbitration signals are used.

The 96 inputs/outputs of the CoLA are equipped with logic level translators and diode clamps, to translate and protect from 1.65V to 5.5V, into the 3.3V logic levels that is used inside. The inputs are not isolated and a common ground is used. Data direction can be changed on a per-byte basis.

Inside the FPGA, the logic analyzer parts is divided into three major parts. First, the 96 inputs are routed through a connection matrix-like multiplexer, so every physical input can be routed freely onto every one of the 96 possible input channels. Secondly, the input channels are fed though a framer/packetizer, which outputs frames with a proper preamble and data compression. These frames are stored in a data buffer, ready to transmit. The third and final part is the communication interface with the FT601B chip, that sends data from the buffer and receives configuration information.

== Data transmission ==
Data transmission coming from the CoLA are formatted in 4 byte (32 bit) frames, each of which consists of a 1 byte preamble and a 3 byte data portion:

{| class="wikitable"
|-
! Preamble !! Data
|-
| 0x82 || bits 95 - 72
|-
| 0x81 || bits 71 - 48
|-
| 0x80 || bits 47 - 24
|-
| 0x00 - 0x7F || bits 23 - 0
|}

Data compression is accomplished in two ways: If nothing changes in input channel bits 95 - 72, the 0x82 frame is omitted completely. Likewise, if channel inputs 71 - 48 or 47 - 24 are unchanged, frame 0x81 and 0x80 respectively are omitted. If nothing changes in inputs 23 - 0, the preamble is increased by 1. This is called the RLE counter. If it finally reaches 0x7F, the frame is sent, and the preamble is reset to 0x00. Using this scheme, data compression can be done in realtime, and with an empty input, a 252:1 ratio can be accomplished. Of course, if the input channel data does change, the frame sent. The hardware WILL send lower preamble frames if a higher one MUST be transmitted. Also, when a USB transmission is started, it triggers a complete preamble set of 0x82, 0x81, 0x80 and 0x00-0x7F, depending on the RLE counter. This is done to provide regular reference points, similar to keyframes in a compressed video stream.

== Design ==
The overall design of the CoLA has two parts: A populated PCB, and an enclosure. The reference design uses a Hammond Manufacturing 1553DTBUBKBAT semi-transparent plastic enclosure. It has minimal exposed metal parts to minimize unwanted short circuits, as the unit is meant to be used near exposed PCB's. The enclosure has a seperate part with a lid, originally meant to house a 9V style battery. This part is used in the CoLA to expose three 34-pin headers to input all signals. Minimal modification is needed to the enclosure to accomodate the PCB.

[[File:1553DTBUBKBAT.jpg|600px]]

The single PCB holds all the electronic components that make the design work. A USB3 B-type connector is used to ruggedize the design, as it is not as fragile compared to a Micro-B or C style connector. The FTDI FT601B-Q ensures steady communication over the USB bus. The parallel bus towards the FPGA is lenght-equalized, to minimize the risk of transmission errors.

Apart from communication, the USB connector also provides supply power to the logic analyzer. The 5V input voltage is converted to a 1.1V core, 2.5V auxilary and 3.3V I/O voltage with a Linear Technology LTC3569. This is a triple buck converter, capable of outputting 1 x 1.2A and 2 x 600mA at a high efficiency of over 90%. The 1.1V core voltage is connected to the 1.2A channel, as it is expected to draw the most current.

The 5CEBA5F23C8N is a 484 ball BGA style chip, with a 1mm pitch. As far as BGA's are DIY friendly at all, this is the most DIY friendly version of any of the packages that the Cyclone V FPGA comes in. As the fanout of this part is not that easy, a 6 layer PCB must be used to route all of the signals from and to the FPGA. Decoupling capacitors are best placed close to ther power pins, so many of them are placed at the opposite PCB side of the FPGA. To store the FPGA configuration image, a EPCQ64A flash is used in Active Serial mode.

For level conversion, a large number of signals needs to be supported. Because the CoLA can also act as a digital pattern generator, data direction signals are also used to drive the six 74LVC16T245DGGR level translators. These are directly connected to the input channels. Input protection is only done by diode clamping, by using twelve SP3003-08ATG 8 channel TVS protection devices. All of the digital channels are present on three 34-pin header connectors, each of which is also equipped with a supply and ground.

== Schematics ==
The schematics of this design can be divided into 5 major blocks. The Input Connector with its Diode Protection devices, the Voltage level Translators, the FPGA as the heart of the device, the USB interface and the Power Supply. All IC's are sufficiently provided with decoupling capacitors, with 2 different values to cover a wider frequency range. The analog PLL voltages of the FPGA are additionally decoupled by means of a ferrite bead. The power supplies have a high switching frequency, but large bulk capacitors of 100uF are provided to handle any kind of current spikes.

[[File:Cola_Block_Schematic.gif]]

[[File:CoLA_Schematics.zip]] Password: sigrok

== Bill of Materials ==

{| class="wikitable"
! Amount
! Designators
! Description
! Package
|-
| 57
| C1 C3 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 C39 C41 C43 C45 C47 C49 C51 C53 C55 C61 C63 C65 C67 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C83 C112 C113 C114 C118 C120 C122 C124 C126 C128 C130 C132
| Chip Capacitor 100nF
| 0402
|-
| 42
| C2 C4 C6 C8 C10 C12 C14 C16 C18 C20 C22 C24 C26 C28 C30 C32 C34 C36 C38 C40 C42 C44 C46 C48 C50 C52 C54 C56 C62 C64 C66 C68 C82 C84 C119 C121 C123 C125 C127 C129 C131 C133
| Chip Capacitor 6.8nF
| 0402
|-
| 9
| C57 C58 C59 C60 C97 C98 C99 C100 C117
| Tantalum Capacitor 100uF 10V
| 2312
|-
| 3
| C85 C86 C87
| Chip Capacitor 22pF
| 0805
|-
| 5
| C101 C103 C104 C106 C110
| Chip Capacitor 100nF
| 0805
|-
| 1
| C111
| Chip Capacitor 470nF
| 0805
|-
| 2
| C115 C116
| Chip Capacitor 18pF
| 0805
|-
| 1
| C134
| Chip Capacitor 10uF
| 0805
|-
| 1
| F1
| Polyfuse 500mA
| 1812
|-
| 7
| L1 L2 L3 L4 L8 L9 L10
| Würth Ferrite Bead 100 Ohms 742792620
| 0603
|-
| 3
| L5 L6 L11
| Würth 2.2uH 74438335022
| 3x3x2mm
|-
| 1
| L7
| Würth Ferrite Bead 11 Ohms 7427920
| 0805
|-
| 1
| LED1
| Led Blue
| 1206
|-
| 1
| P2
| Boxheader 2x5 pin
|
|-
| 1
| P3
| Boxheader 2x17 pin
| Black
|-
| 1
| P4
| Boxheader 2x17 pin
| Grey
|-
| 1
| P5
| Boxheader 2x17 pin
| Blue
|-
| 1
| P6
| Würth 692221030100 USB3.0 B Connector
|
|-
| 1
| Q1
| BC847B NPN Transistor
| SOT23
|-
| 3
| R1 R7 R8
| Chip Resistor 25 Ohms
| 0805
|-
| 1
| R2
| Chip Resistor 4K7 Ohms
| 0805
|-
| 2
| R3 R6
| Chip Resistor 10K Ohms
| 0805
|-
| 1
| R4
| Chip Resistor 33 Ohms
| 0805
|-
| 1
| R5
| Chip Resistor 1K6 Ohms
| 0805
|-
| 1
| R9
| Chip Resistor 2K Ohms
| 0805
|-
| 1
| R10
| Chip Resistor 220 Ohms
| 0805
|-
| 13
| R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23
| Chip Resistor 1K Ohms
| 0805
|-
| 1
| R24
| Chip Resistor 75K Ohms
| 0805
|-
| 1
| R25
| Chip Resistor 200K Ohms
| 0805
|-
| 1
| R26
| Chip Resistor 47K Ohms
| 0805
|-
| 1
| R27
| Chip Resistor 15K Ohms
| 0805
|-
| 1
| R28
| Chip Resistor 51K Ohms
| 0805
|-
| 1
| R29
| Chip Resistor 24K Ohms
| 0805
|-
| 1
| RN1
| Resistor Network 4x10K Ohms
| 0612
|-
| 1
| RN2
| Resistor Network 4x1K Ohms
| 0612
|-
| 11
| RN4 RN5 RN6 RN7 RN8 RN9 RN10 RN11 RN12 RN13 RN14
| Resistor Network 4x33 Ohms
| 0612
|-
| 1
| U1
| Altera EPCQ64A
| SOICW16
|-
| 12
| U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13
| SP3003-08ATG
| MSOP10
|-
| 6
| U14 U15 U16 U17 U18 U19
| 74LVC16T245DGGR
| TSSOP48
|-
| 1
| U20
| Intel/Altera 5CEBA5F23C8N
| FBGA484
|-
| 1
| U21
| Linear Technology LTC3569EFE
| TSSOP16 EP
|-
| 1
| U24
| FTDI FT601Q-B-T
| QFN76
|-
| 1
| Y1
| 30MHz Crystal 10ppm
| 5x3.2mm 4 pad
|-
| 1
| Enclosure
| Hammond 1553DTBUBKBAT
|
|-
| 1
| PCB
| CoLA PCB
|
|}

== PCB layout ==
This is the used PCB stackup for the 6 layer board. If you order PCB's, ask for this stackup:
{| class="wikitable"
! Description
! Thickness
! Material
|-
| Solder mask
| 10um
| Solder resist
|-
| Top Layer
| 35um
| Copper layer
|-
| Prepreg
| 177um
| Insulation layer
|-
| Ground Plane
| 18um
| Copper layer
|-
| FR4 base material
| 410um
| Insulation layer
|-
| Inner layer 1
| 18um
| Copper layer
|-
| Prepreg
| 188um
| Insulation layer
|-
| Inner layer 2
| 18um
| Copper layer
|-
| FR4 base material
| 410um
| Insulation layer
|-
| Split power plane
| 18um
| Copper layer
|-
| Prepreg
| 173um
| Insulation layer
|-
| Bottom Layer
| 35um
| Copper layer
|-
| Solder mask
| 10um
| Solder resist
|}
The PCB is 1.6mm thickness, 139.224mm x 73.666mm. It has a 6mil/6mil track spacing/clearance, with 0.25mm minimum drilled holes. Be sure to select silkscreen on both sides of the PCB. You will need to upload the ZIP file with the Gerber plot files to the PCB manufacturer. On these kinds of boards, electrical testing is the standard, but if you can choose: opt for an E-test.

[[File:CoLA_Gerber.zip]]

[[File:CoLA2.PNG|600px]]

[[File:Cola_PCB_top.jpg|600px]]

[[File:Cola_PCB_bot.jpg|600px]]

== FPGA firmware ==
All the signal processing is done inside a FPGA, which stands for Field Programmable Gate Array. It basically is a chip in which you can configure every digital function you desire (within the constraints and complexity limits of the device). While this describes how a Logic Element inside the FPGA is set up, these FPGA's nowadays also have dedicated hardware for specific functions. For example, you can build a function to store digital information (those are called flipflops), but the FPGA also has on-board memory blocks where you can store loads of data. Since we expect to generate a lot of data with our logic analyzer function, we will need to apply these memory storage blocks. The Cyclone V we chose have them in 10kbit chunks, called M10K, of which we will use 8kbit of. The FPGA has a generous 446 of these. Other dedicated hardware inside the FPGA, such as hardware multipliers called DSP blocks, we will not be needing in this design.

[[File:CoLA_FPGA_block.PNG|600px]]

The 96 inputs coming from the outside of the FPGA are first fed into a multiplexer. This block can route any of its 128 inputs to any of its 128 outputs. The benefit of this is that we can route any signals the way we want to. For example, a D0 signal on input 38 can be routed to D1 that can be all the way on input 71. This way, the data represented to the software can be interpreted more easily. An additional effect is that we can place our signals of interest onto a less wide window, and can use a higher sampling frequency to probe these signals.

Next, after the multiplexer, the data are packetized for the 32 bit data transfers to out USB interface. The 32 bit data consists, as said, of an 8 bit preamble, and a 24 bit data portion. Four of these data frames make for the full 96 bits, and therefore we can sample the data as fast as 25% of the USB clock. Since our USB clock is 100MHz, it means 25MHz is the maximum for 96 bits. If we use only half of the 96 signals, we can sample 48 bits at 50MHz. For 24 input channels, we can even use the full 100MHz sampling frequency. These 24 channels, thanks to our input multiplexer, can still be chosen out of the full 96 possible inputs.

Now that we formed the 32 bit USB transfer frames, we have to store them until the computer want to receive them. We have made room with the M10K memory blocks for 262144 frames, waiting for the computer to fetch them. These are passed onto the FT601 interface, this is the part that talks to the USB chip. It communicates sample data to, and configuration data from the USB bus. On the USB bus, data is transferred in 4Kbyte packets, and 16 of those packets form a 64 kbyte frame. Of course, there may not be that much data available, and a non-full frame indicates that we have not maxed out the available USB throughput. In the case of this maxing out happening 4 times in a row, there might be a chance that there was loss in sampling data due to a buffer overflow inside of the FPGA memory. The computer needs to keep track of this!

The generate the sample clock, the 100MHz USB clock is divided into a lower frequency. This is a point where the CoLA firmware can (and hopefully will) be improved: The FPGA incorporates fractional PLL's, blocks which can output a new clock, based of a reference clock. As opposed to the limited options with the current clock divider circuit, the fractional PLL can output a much broader range of frequencies. So if you want 21.36MHz as sampling frequency, it's possible with the fractional PLL. The sampling clock is sent to the trigger engine, where various trigger options can not be chosen. For now, only a continuous sampling can be selected. In the future, more triggering options such as a pattern trigger or a range trigger will be selectable.

The firmware for the CoLA is written in a hardware description language: VHDL. A HDL is a way to describe the workings of a digital circuit. This is interpreted by the computer and it makes an actual configuration file to write to the FPGA's SRAM. The SRAM is volatile, so if you want a more permanent functionality, you will need a configuration flash EEPROM. The EEPROM will program the FPGA every time it powers up. The SRAM image in Quartus is called a Serial Object File (SOF). Because we have no programming pins brought out for the flash EEPROM, we'll need to flash the FPGA with the design of an EEPROM programmer. The FPGA will in turn program the flash with data coming from the JTAG port. This kind of sequence is done with a JTAG Indirect Configuration, or JIC file.

[[File:CoLA_VHDL.zip]]

[[File:CoLA_SOF.zip]]

[[File:CoLA_JIC.zip]]

== Software ==

The CoLA does not have integration into Sigrok and Pulseview. This is because the used FT601 driver is from FTDI and is closed source. This is the reason that prevents the software from being released under Sigrok compatible licence. However, this chapter describes a capture script that can be used outside of the Sigrok environment, yet produces files that can be read with Pulseview. The capture script can be adjusted to set the input multiplexer inside of the FPGA, as well as adjust the sample frequency, set double or quad speed mode (at cost of half or quarter the channel amount). At the moment of writing, Pulseview supports a maximum of 64 channels, so this scripts only exports a maximum of 64 of the 96 available channels. However, you can still select files over the 64 limit to be captures, by using the multiplexer function.

The capture script works in two steps: The first is to set the CoLA configuration, and write the captured data frames onto disk. Be sure to use a adequate performing storage solution, as the hardware can output in excess of 300 megabytes per second. An NVMe SSD is highly reccommended. The second step is to process the captured data, which is in compressed with RLE and omitted frames, and extract them to the full form. This is output to a Sigrok and Pulseview compatible (zipped) format. The files are automatically timestamped.

The capture script is written in Python 2.7, and is targeted at Windows computers for now. It requires the ftd3xx.dll file, which can be downloaded from hte FTDI website, in order to communicate with the FTDI chip. Be sure to connect the CoLA to an USB3.0 or higher port, and use the FT601 configuration tool to disable the USB suspend option, as this will feature disables the clock signal towards the FPGA. You will recognize this unwanted behaviour by the LED on the CoLA. If it stops blinking, you will need to disbale the suspend option. At idle, the LED will blink in a slow double flash pattern. If it is capturing, it will blink fast. If a communication congestion occurs, the blink pattern will change into a mostly-on pattern.

Please note that the software can be greatly improved upon, and is merely to provide a minimalistic means to use the hardware. The ultimate goal would be to have Sigrok integration, but unless an open source solution is written for the FT601, this Python script will have to do for now.

[[File:CoLA_cap.zip]]

CoLA

2019-12-17T07:11:32Z

Danny W:

CoLA

2019-12-17T07:07:00Z

Danny W:

{{Infobox logic analyzer
| image = [[File:IMG 20191206 105430.jpg|180px]]
| name = CoLA - Compact Logic Analyzer
| status = planned
| source_code_dir = -
| channels = 96/48/24
| samplerate = 25MHz/50MHz/100MHz
| samplerate_state = ?
| triggers = 32 hardware, 96 bit masked pattern
| voltages = 1.65V - 5.5V continuously
| threshold = ?
| memory = 262144 bytes
| compression = RLE, frame omission
| website = -
}}

== Introduction ==

CoLA - Compact Logic Analyzer is an USB3.0 based 96ch/25MHz, 48ch/50MHz or 24ch/100MHz logic analyzer/pattern generator, with built-in hardware pattern triggers, supporting all logic levels from 1.65V to 5.5V. It uses an Intel/Altera Cyclone V FPGA for digital aquisition and FTDI FT601B for 5Gbps USB3.0 support. To limit data transfers, it uses Run Length Encoding (RLE) as well as frame omission. Its compact design and versatility, as well as future upgradability and a DIY approach makes CoLA an interesting project.

== Theory ==

The aquisition of digital levels are done by an FPGA. The Intel/Altera Cyclone V series have sufficient speed and resources. Although versions with High Speed Serial Interfaces (HSSI's) and an embedded ARM Host Processor System (HPS) exist, a part without these is selected. The 5CEBA5F23C8 has 29.000 ALM / 77.000 LE's and 446 M10K memory blocks of resources. For now, the 150 DSP hardware multiplier modules are not used, but that can change in the future. The FPGA is also equipped with 6 PLL blocks, but only one is used.

To transfer all data to a computer, a part from FTDI is used to communicate over the USB bus. The FT601 has a 5Gbps transceiver, of which 3200Mbps can be used by the chip. The USB chip interfaces to the FPGA by means of a parallel data bus, 32 bits at 100MHz. It uses an external 30MHz crystal to generate all frequencies, and the FPGA inputs the 100MHz clock as its main clock frequency. Apart from the 32 data bits, some other arbitration signals are used.

The 96 inputs/outputs of the CoLA are equipped with logic level translators and diode clamps, to translate and protect from 1.65V to 5.5V, into the 3.3V logic levels that is used inside. The inputs are not isolated and a common ground is used. Data direction can be changed on a per-byte basis.

Inside the FPGA, the logic analyzer parts is divided into three major parts. First, the 96 inputs are routed through a connection matrix-like multiplexer, so every physical input can be routed freely onto every one of the 96 possible input channels. Secondly, the input channels are fed though a framer/packetizer, which outputs frames with a proper preamble and data compression. These frames are stored in a data buffer, ready to transmit. The third and final part is the communication interface with the FT601B chip, that sends data from the buffer and receives configuration information.

== Data transmission ==
Data transmission coming from the CoLA are formatted in 4 byte (32 bit) frames, each of which consists of a 1 byte preamble and a 3 byte data portion:

{| class="wikitable"
|-
! Preamble !! Data
|-
| 0x82 || bits 95 - 72
|-
| 0x81 || bits 71 - 48
|-
| 0x80 || bits 47 - 24
|-
| 0x00 - 0x7F || bits 23 - 0
|}

Data compression is accomplished in two ways: If nothing changes in input channel bits 95 - 72, the 0x82 frame is omitted completely. Likewise, if channel inputs 71 - 48 or 47 - 24 are unchanged, frame 0x81 and 0x80 respectively are omitted. If nothing changes in inputs 23 - 0, the preamble is increased by 1. This is called the RLE counter. If it finally reaches 0x7F, the frame is sent, and the preamble is reset to 0x00. Using this scheme, data compression can be done in realtime, and with an empty input, a 252:1 ratio can be accomplished. Of course, if the input channel data does change, the frame sent. The hardware WILL send lower preamble frames if a higher one MUST be transmitted. Also, when a USB transmission is started, it triggers a complete preamble set of 0x82, 0x81, 0x80 and 0x00-0x7F, depending on the RLE counter. This is done to provide regular reference points, similar to keyframes in a compressed video stream.

== Design ==
The overall design of the CoLA has two parts: A populated PCB, and an enclosure. The reference design uses a Hammond Manufacturing 1553DTBUBKBAT semi-transparent plastic enclosure. It has minimal exposed metal parts to minimize unwanted short circuits, as the unit is meant to be used near exposed PCB's. The enclosure has a seperate part with a lid, originally meant to house a 9V style battery. This part is used in the CoLA to expose three 34-pin headers to input all signals. Minimal modification is needed to the enclosure to accomodate the PCB.

[[File:1553DTBUBKBAT.jpg|600px]]

The single PCB holds all the electronic components that make the design work. A USB3 B-type connector is used to ruggedize the design, as it is not as fragile compared to a Micro-B or C style connector. The FTDI FT601B-Q ensures steady communication over the USB bus. The parallel bus towards the FPGA is lenght-equalized, to minimize the risk of transmission errors.

Apart from communication, the USB connector also provides supply power to the logic analyzer. The 5V input voltage is converted to a 1.1V core, 2.5V auxilary and 3.3V I/O voltage with a Linear Technology LTC3569. This is a triple buck converter, capable of outputting 1 x 1.2A and 2 x 600mA at a high efficiency of over 90%. The 1.1V core voltage is connected to the 1.2A channel, as it is expected to draw the most current.

The 5CEBA5F23C8N is a 484 ball BGA style chip, with a 1mm pitch. As far as BGA's are DIY friendly at all, this is the most DIY friendly version of any of the packages that the Cyclone V FPGA comes in. As the fanout of this part is not that easy, a 6 layer PCB must be used to route all of the signals from and to the FPGA. Decoupling capacitors are best placed close to ther power pins, so many of them are placed at the opposite PCB side of the FPGA. To store the FPGA configuration image, a EPCQ64A flash is used in Active Serial mode.

For level conversion, a large number of signals needs to be supported. Because the CoLA can also act as a digital pattern generator, data direction signals are also used to drive the six 74LVC16T245DGGR level translators. These are directly connected to the input channels. Input protection is only done by diode clamping, by using twelve SP3003-08ATG 8 channel TVS protection devices. All of the digital channels are present on three 34-pin header connectors, each of which is also equipped with a supply and ground.

== Schematics ==
The schematics of this design can be divided into 5 major blocks. The Input Connector with its Diode Protection devices, the Voltage level Translators, the FPGA as the heart of the device, the USB interface and the Power Supply. All IC's are sufficiently provided with decoupling capacitors, with 2 different values to cover a wider frequency range. The analog PLL voltages of the FPGA are additionally decoupled by means of a ferrite bead. The power supplies have a high switching frequency, but large bulk capacitors of 100uF are provided to handle any kind of current spikes.

[[File:Cola_Block_Schematic.gif]]

[[File:CoLA_Schematics.zip]] Password: sigrok

== Bill of Materials ==

{| class="wikitable"
! Amount
! Designators
! Description
! Package
|-
| 57
| C1 C3 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 C39 C41 C43 C45 C47 C49 C51 C53 C55 C61 C63 C65 C67 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C83 C112 C113 C114 C118 C120 C122 C124 C126 C128 C130 C132
| Chip Capacitor 100nF
| 0402
|-
| 42
| C2 C4 C6 C8 C10 C12 C14 C16 C18 C20 C22 C24 C26 C28 C30 C32 C34 C36 C38 C40 C42 C44 C46 C48 C50 C52 C54 C56 C62 C64 C66 C68 C82 C84 C119 C121 C123 C125 C127 C129 C131 C133
| Chip Capacitor 6.8nF
| 0402
|-
| 9
| C57 C58 C59 C60 C97 C98 C99 C100 C117
| Tantalum Capacitor 100uF 10V
| 2312
|-
| 3
| C85 C86 C87
| Chip Capacitor 22pF
| 0805
|-
| 5
| C101 C103 C104 C106 C110
| Chip Capacitor 100nF
| 0805
|-
| 1
| C111
| Chip Capacitor 470nF
| 0805
|-
| 2
| C115 C116
| Chip Capacitor 18pF
| 0805
|-
| 1
| C134
| Chip Capacitor 10uF
| 0805
|-
| 1
| F1
| Polyfuse 500mA
| 1812
|-
| 7
| L1 L2 L3 L4 L8 L9 L10
| Würth Ferrite Bead 100 Ohms 742792620
| 0603
|-
| 3
| L5 L6 L11
| Würth 2.2uH 74438335022
| 3x3x2mm
|-
| 1
| L7
| Würth Ferrite Bead 11 Ohms 7427920
| 0805
|-
| 1
| LED1
| Led Blue
| 1206
|-
| 1
| P2
| Boxheader 2x5 pin
|
|-
| 1
| P3
| Boxheader 2x17 pin
| Black
|-
| 1
| P4
| Boxheader 2x17 pin
| Grey
|-
| 1
| P5
| Boxheader 2x17 pin
| Blue
|-
| 1
| P6
| Würth 692221030100 USB3.0 B Connector
|
|-
| 1
| Q1
| BC847B NPN Transistor
| SOT23
|-
| 3
| R1 R7 R8
| Chip Resistor 25 Ohms
| 0805
|-
| 1
| R2
| Chip Resistor 4K7 Ohms
| 0805
|-
| 2
| R3 R6
| Chip Resistor 10K Ohms
| 0805
|-
| 1
| R4
| Chip Resistor 33 Ohms
| 0805
|-
| 1
| R5
| Chip Resistor 1K6 Ohms
| 0805
|-
| 1
| R9
| Chip Resistor 2K Ohms
| 0805
|-
| 1
| R10
| Chip Resistor 220 Ohms
| 0805
|-
| 13
| R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23
| Chip Resistor 1K Ohms
| 0805
|-
| 1
| R24
| Chip Resistor 75K Ohms
| 0805
|-
| 1
| R25
| Chip Resistor 200K Ohms
| 0805
|-
| 1
| R26
| Chip Resistor 47K Ohms
| 0805
|-
| 1
| R27
| Chip Resistor 15K Ohms
| 0805
|-
| 1
| R28
| Chip Resistor 51K Ohms
| 0805
|-
| 1
| R29
| Chip Resistor 24K Ohms
| 0805
|-
| 1
| RN1
| Resistor Network 4x10K Ohms
| 0612
|-
| 1
| RN2
| Resistor Network 4x1K Ohms
| 0612
|-
| 11
| RN4 RN5 RN6 RN7 RN8 RN9 RN10 RN11 RN12 RN13 RN14
| Resistor Network 4x33 Ohms
| 0612
|-
| 1
| U1
| Altera EPCQ64A
| SOICW16
|-
| 12
| U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13
| SP3003-08ATG
| MSOP10
|-
| 6
| U14 U15 U16 U17 U18 U19
| 74LVC16T245DGGR
| TSSOP48
|-
| 1
| U20
| Intel/Altera 5CEBA5F23C8N
| FBGA484
|-
| 1
| U21
| Linear Technology LTC3569EFE
| TSSOP16 EP
|-
| 1
| U24
| FTDI FT601Q-B-T
| QFN76
|-
| 1
| Y1
| 30MHz Crystal 10ppm
| 5x3.2mm 4 pad
|-
| 1
| Enclosure
| Hammond 1553DTBUBKBAT
|
|-
| 1
| PCB
| CoLA PCB
|
|}

== PCB layout ==
This is the used PCB stackup for the 6 layer board. If you order PCB's, ask for this stackup:
{| class="wikitable"
! Description
! Thickness
! Material
|-
| Solder mask
| 10um
| Solder resist
|-
| Top Layer
| 35um
| Copper layer
|-
| Prepreg
| 177um
| Insulation layer
|-
| Ground Plane
| 18um
| Copper layer
|-
| FR4 base material
| 410um
| Insulation layer
|-
| Inner layer 1
| 18um
| Copper layer
|-
| Prepreg
| 188um
| Insulation layer
|-
| Inner layer 2
| 18um
| Copper layer
|-
| FR4 base material
| 410um
| Insulation layer
|-
| Split power plane
| 18um
| Copper layer
|-
| Prepreg
| 173um
| Insulation layer
|-
| Bottom Layer
| 35um
| Copper layer
|-
| Solder mask
| 10um
| Solder resist
|}
The PCB is 1.6mm thickness, 139.224mm x 73.666mm. It has a 6mil/6mil track spacing/clearance, with 0.25mm minimum drilled holes. Be sure to select silkscreen on both sides of the PCB. You will need to upload the ZIP file with the Gerber plot files to the PCB manufacturer. On these kinds of boards, electrical testing is the standard, but if you can choose: opt for an E-test.

[[File:CoLA_Gerber.zip]]

[[File:CoLA2.PNG|600px]]

[[File:Cola_PCB_top.jpg|600px]]

[[File:Cola_PCB_bot.jpg|600px]]

== FPGA firmware ==
All the signal processing is done inside a FPGA, which stands for Field Programmable Gate Array. It basically is a chip in which you can configure every digital function you desire (within the constraints and complexity limits of the device). While this describes how a Logic Element inside the FPGA is set up, these FPGA's nowadays also have dedicated hardware for specific functions. For example, you can build a function to store digital information (those are called flipflops), but the FPGA also has on-board memory blocks where you can store loads of data. Since we expect to generate a lot of data with our logic analyzer function, we will need to apply these memory storage blocks. The Cyclone V we chose have them in 10kbit chunks, called M10K, of which we will use 8kbit of. The FPGA has a generous 446 of these. Other dedicated hardware inside the FPGA, such as hardware multipliers called DSP blocks, we will not be needing in this design.

[[File:CoLA_FPGA_block.PNG|600px]]

The 96 inputs coming from the outside of the FPGA are first fed into a multiplexer. This block can route any of its 128 inputs to any of its 128 outputs. The benefit of this is that we can route any signals the way we want to. For example, a D0 signal on input 38 can be routed to D1 that can be all the way on input 71. This way, the data represented to the software can be interpreted more easily. An additional effect is that we can place our signals of interest onto a less wide window, and can use a higher sampling frequency to probe these signals.

Next, after the multiplexer, the data are packetized for the 32 bit data transfers to out USB interface. The 32 bit data consists, as said, of an 8 bit preamble, and a 24 bit data portion. Four of these data frames make for the full 96 bits, and therefore we can sample the data as fast as 25% of the USB clock. Since our USB clock is 100MHz, it means 25MHz is the maximum for 96 bits. If we use only half of the 96 signals, we can sample 48 bits at 50MHz. For 24 input channels, we can even use the full 100MHz sampling frequency. These 24 channels, thanks to our input multiplexer, can still be chosen out of the full 96 possible inputs.

Now that we formed the 32 bit USB transfer frames, we have to store them until the computer want to receive them. We have made room with the M10K memory blocks for 262144 frames, waiting for the computer to fetch them. These are passed onto the FT601 interface, this is the part that talks to the USB chip. It communicates sample data to, and configuration data from the USB bus. On the USB bus, data is transferred in 4Kbyte packets, and 16 of those packets form a 64 kbyte frame. Of course, there may not be that much data available, and a non-full frame indicates that we have not maxed out the available USB throughput. In the case of this maxing out happening 4 times in a row, there might be a chance that there was loss in sampling data due to a buffer overflow inside of the FPGA memory. The computer needs to keep track of this!

The generate the sample clock, the 100MHz USB clock is divided into a lower frequency. This is a point where the CoLA firmware can (and hopefully will) be improved: The FPGA incorporates fractional PLL's, blocks which can output a new clock, based of a reference clock. As opposed to the limited options with the current clock divider circuit, the fractional PLL can output a much broader range of frequencies. So if you want 21.36MHz as sampling frequency, it's possible with the fractional PLL. The sampling clock is sent to the trigger engine, where various trigger options can not be chosen. For now, only a continuous sampling can be selected. In the future, more triggering options such as a pattern trigger or a range trigger will be selectable.

The firmware for the CoLA is written in a hardware description language: VHDL. A HDL is a way to describe the workings of a digital circuit. This is interpreted by the computer and it makes an actual configuration file to write to the FPGA's SRAM. The SRAM is volatile, so if you want a more permanent functionality, you will need a configuration flash EEPROM. The EEPROM will program the FPGA every time it powers up. The SRAM image in Quartus is called a Serial Object File (SOF). Because we have no programming pins brought out for the flash EEPROM, we'll need to flash the FPGA with the design of an EEPROM programmer. This will in turn program the flash with data coming from the JTAG port. This kind of sequence is done with a JTAG Indirect Configuration, or JIC file.

[[File:CoLA_VHDL.zip]]

[[File:CoLA_SOF.zip]]

[[File:CoLA_JIC.zip]]

File:CoLA JIC.zip

2019-12-17T06:19:12Z

Danny W:

== Licensing ==
{{CC-BY-SA-3.0}}

File:CoLA SOF.zip

2019-12-17T06:18:45Z

Danny W:

== Licensing ==
{{CC-BY-SA-3.0}}

File:CoLA VHDL.zip

2019-12-17T06:18:18Z

Danny W:

== Licensing ==
{{CC-BY-SA-3.0}}

CoLA

2019-12-17T06:17:52Z

Danny W:

{{Infobox logic analyzer
| image = [[File:IMG 20191206 105430.jpg|180px]]
| name = CoLA - Compact Logic Analyzer
| status = planned
| source_code_dir = -
| channels = 96/48/24
| samplerate = 25MHz/50MHz/100MHz
| samplerate_state = ?
| triggers = 32 hardware, 96 bit masked pattern
| voltages = 1.65V - 5.5V continuously
| threshold = ?
| memory = 262144 bytes
| compression = RLE, frame omission
| website = -
}}

== Introduction ==

CoLA - Compact Logic Analyzer is an USB3.0 based 96ch/25MHz, 48ch/50MHz or 24ch/100MHz logic analyzer/pattern generator, with built-in hardware pattern triggers, supporting all logic levels from 1.65V to 5.5V. It uses an Intel/Altera Cyclone V FPGA for digital aquisition and FTDI FT601B for 5Gbps USB3.0 support. To limit data transfers, it uses Run Length Encoding (RLE) as well as frame omission. Its compact design and versatility, as well as future upgradability and a DIY approach makes CoLA an interesting project.

== Theory ==

The aquisition of digital levels are done by an FPGA. The Intel/Altera Cyclone V series have sufficient speed and resources. Although versions with High Speed Serial Interfaces (HSSI's) and an embedded ARM Host Processor System (HPS) exist, a part without these is selected. The 5CEBA5F23C8 has 29.000 ALM / 77.000 LE's and 446 M10K memory blocks of resources. For now, the 150 DSP hardware multiplier modules are not used, but that can change in the future. The FPGA is also equipped with 6 PLL blocks, but only one is used.

To transfer all data to a computer, a part from FTDI is used to communicate over the USB bus. The FT601 has a 5Gbps transceiver, of which 3200Mbps can be used by the chip. The USB chip interfaces to the FPGA by means of a parallel data bus, 32 bits at 100MHz. It uses an external 30MHz crystal to generate all frequencies, and the FPGA inputs the 100MHz clock as its main clock frequency. Apart from the 32 data bits, some other arbitration signals are used.

The 96 inputs/outputs of the CoLA are equipped with logic level translators and diode clamps, to translate and protect from 1.65V to 5.5V, into the 3.3V logic levels that is used inside. The inputs are not isolated and a common ground is used. Data direction can be changed on a per-byte basis.

Inside the FPGA, the logic analyzer parts is divided into three major parts. First, the 96 inputs are routed through a connection matrix-like multiplexer, so every physical input can be routed freely onto every one of the 96 possible input channels. Secondly, the input channels are fed though a framer/packetizer, which outputs frames with a proper preamble and data compression. These frames are stored in a data buffer, ready to transmit. The third and final part is the communication interface with the FT601B chip, that sends data from the buffer and receives configuration information.

== Data transmission ==
Data transmission coming from the CoLA are formatted in 4 byte (32 bit) frames, each of which consists of a 1 byte preamble and a 3 byte data portion:

{| class="wikitable"
|-
! Preamble !! Data
|-
| 0x82 || bits 95 - 72
|-
| 0x81 || bits 71 - 48
|-
| 0x80 || bits 47 - 24
|-
| 0x00 - 0x7F || bits 23 - 0
|}

Data compression is accomplished in two ways: If nothing changes in input channel bits 95 - 72, the 0x82 frame is omitted completely. Likewise, if channel inputs 71 - 48 or 47 - 24 are unchanged, frame 0x81 and 0x80 respectively are omitted. If nothing changes in inputs 23 - 0, the preamble is increased by 1. This is called the RLE counter. If it finally reaches 0x7F, the frame is sent, and the preamble is reset to 0x00. Using this scheme, data compression can be done in realtime, and with an empty input, a 252:1 ratio can be accomplished. Of course, if the input channel data does change, the frame sent. The hardware WILL send lower preamble frames if a higher one MUST be transmitted. Also, when a USB transmission is started, it triggers a complete preamble set of 0x82, 0x81, 0x80 and 0x00-0x7F, depending on the RLE counter. This is done to provide regular reference points, similar to keyframes in a compressed video stream.

== Design ==
The overall design of the CoLA has two parts: A populated PCB, and an enclosure. The reference design uses a Hammond Manufacturing 1553DTBUBKBAT semi-transparent plastic enclosure. It has minimal exposed metal parts to minimize unwanted short circuits, as the unit is meant to be used near exposed PCB's. The enclosure has a seperate part with a lid, originally meant to house a 9V style battery. This part is used in the CoLA to expose three 34-pin headers to input all signals. Minimal modification is needed to the enclosure to accomodate the PCB.

[[File:1553DTBUBKBAT.jpg|600px]]

The single PCB holds all the electronic components that make the design work. A USB3 B-type connector is used to ruggedize the design, as it is not as fragile compared to a Micro-B or C style connector. The FTDI FT601B-Q ensures steady communication over the USB bus. The parallel bus towards the FPGA is lenght-equalized, to minimize the risk of transmission errors.

Apart from communication, the USB connector also provides supply power to the logic analyzer. The 5V input voltage is converted to a 1.1V core, 2.5V auxilary and 3.3V I/O voltage with a Linear Technology LTC3569. This is a triple buck converter, capable of outputting 1 x 1.2A and 2 x 600mA at a high efficiency of over 90%. The 1.1V core voltage is connected to the 1.2A channel, as it is expected to draw the most current.

The 5CEBA5F23C8N is a 484 ball BGA style chip, with a 1mm pitch. As far as BGA's are DIY friendly at all, this is the most DIY friendly version of any of the packages that the Cyclone V FPGA comes in. As the fanout of this part is not that easy, a 6 layer PCB must be used to route all of the signals from and to the FPGA. Decoupling capacitors are best placed close to ther power pins, so many of them are placed at the opposite PCB side of the FPGA. To store the FPGA configuration image, a EPCQ64A flash is used in Active Serial mode.

For level conversion, a large number of signals needs to be supported. Because the CoLA can also act as a digital pattern generator, data direction signals are also used to drive the six 74LVC16T245DGGR level translators. These are directly connected to the input channels. Input protection is only done by diode clamping, by using twelve SP3003-08ATG 8 channel TVS protection devices. All of the digital channels are present on three 34-pin header connectors, each of which is also equipped with a supply and ground.

== Schematics ==
The schematics of this design can be divided into 5 major blocks. The Input Connector with its Diode Protection devices, the Voltage level Translators, the FPGA as the heart of the device, the USB interface and the Power Supply. All IC's are sufficiently provided with decoupling capacitors, with 2 different values to cover a wider frequency range. The analog PLL voltages of the FPGA are additionally decoupled by means of a ferrite bead. The power supplies have a high switching frequency, but large bulk capacitors of 100uF are provided to handle any kind of current spikes.

[[File:Cola_Block_Schematic.gif]]

[[File:CoLA_Schematics.zip]] Password: sigrok

== Bill of Materials ==

{| class="wikitable"
! Amount
! Designators
! Description
! Package
|-
| 57
| C1 C3 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 C39 C41 C43 C45 C47 C49 C51 C53 C55 C61 C63 C65 C67 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C83 C112 C113 C114 C118 C120 C122 C124 C126 C128 C130 C132
| Chip Capacitor 100nF
| 0402
|-
| 42
| C2 C4 C6 C8 C10 C12 C14 C16 C18 C20 C22 C24 C26 C28 C30 C32 C34 C36 C38 C40 C42 C44 C46 C48 C50 C52 C54 C56 C62 C64 C66 C68 C82 C84 C119 C121 C123 C125 C127 C129 C131 C133
| Chip Capacitor 6.8nF
| 0402
|-
| 9
| C57 C58 C59 C60 C97 C98 C99 C100 C117
| Tantalum Capacitor 100uF 10V
| 2312
|-
| 3
| C85 C86 C87
| Chip Capacitor 22pF
| 0805
|-
| 5
| C101 C103 C104 C106 C110
| Chip Capacitor 100nF
| 0805
|-
| 1
| C111
| Chip Capacitor 470nF
| 0805
|-
| 2
| C115 C116
| Chip Capacitor 18pF
| 0805
|-
| 1
| C134
| Chip Capacitor 10uF
| 0805
|-
| 1
| F1
| Polyfuse 500mA
| 1812
|-
| 7
| L1 L2 L3 L4 L8 L9 L10
| Würth Ferrite Bead 100 Ohms 742792620
| 0603
|-
| 3
| L5 L6 L11
| Würth 2.2uH 74438335022
| 3x3x2mm
|-
| 1
| L7
| Würth Ferrite Bead 11 Ohms 7427920
| 0805
|-
| 1
| LED1
| Led Blue
| 1206
|-
| 1
| P2
| Boxheader 2x5 pin
|
|-
| 1
| P3
| Boxheader 2x17 pin
| Black
|-
| 1
| P4
| Boxheader 2x17 pin
| Grey
|-
| 1
| P5
| Boxheader 2x17 pin
| Blue
|-
| 1
| P6
| Würth 692221030100 USB3.0 B Connector
|
|-
| 1
| Q1
| BC847B NPN Transistor
| SOT23
|-
| 3
| R1 R7 R8
| Chip Resistor 25 Ohms
| 0805
|-
| 1
| R2
| Chip Resistor 4K7 Ohms
| 0805
|-
| 2
| R3 R6
| Chip Resistor 10K Ohms
| 0805
|-
| 1
| R4
| Chip Resistor 33 Ohms
| 0805
|-
| 1
| R5
| Chip Resistor 1K6 Ohms
| 0805
|-
| 1
| R9
| Chip Resistor 2K Ohms
| 0805
|-
| 1
| R10
| Chip Resistor 220 Ohms
| 0805
|-
| 13
| R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23
| Chip Resistor 1K Ohms
| 0805
|-
| 1
| R24
| Chip Resistor 75K Ohms
| 0805
|-
| 1
| R25
| Chip Resistor 200K Ohms
| 0805
|-
| 1
| R26
| Chip Resistor 47K Ohms
| 0805
|-
| 1
| R27
| Chip Resistor 15K Ohms
| 0805
|-
| 1
| R28
| Chip Resistor 51K Ohms
| 0805
|-
| 1
| R29
| Chip Resistor 24K Ohms
| 0805
|-
| 1
| RN1
| Resistor Network 4x10K Ohms
| 0612
|-
| 1
| RN2
| Resistor Network 4x1K Ohms
| 0612
|-
| 11
| RN4 RN5 RN6 RN7 RN8 RN9 RN10 RN11 RN12 RN13 RN14
| Resistor Network 4x33 Ohms
| 0612
|-
| 1
| U1
| Altera EPCQ64A
| SOICW16
|-
| 12
| U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13
| SP3003-08ATG
| MSOP10
|-
| 6
| U14 U15 U16 U17 U18 U19
| 74LVC16T245DGGR
| TSSOP48
|-
| 1
| U20
| Intel/Altera 5CEBA5F23C8N
| FBGA484
|-
| 1
| U21
| Linear Technology LTC3569EFE
| TSSOP16 EP
|-
| 1
| U24
| FTDI FT601Q-B-T
| QFN76
|-
| 1
| Y1
| 30MHz Crystal 10ppm
| 5x3.2mm 4 pad
|-
| 1
| Enclosure
| Hammond 1553DTBUBKBAT
|
|-
| 1
| PCB
| CoLA PCB
|
|}

== PCB layout ==
This is the used PCB stackup for the 6 layer board. If you order PCB's, ask for this stackup:
{| class="wikitable"
! Description
! Thickness
! Material
|-
| Solder mask
| 10um
| Solder resist
|-
| Top Layer
| 35um
| Copper layer
|-
| Prepreg
| 177um
| Insulation layer
|-
| Ground Plane
| 18um
| Copper layer
|-
| FR4 base material
| 410um
| Insulation layer
|-
| Inner layer 1
| 18um
| Copper layer
|-
| Prepreg
| 188um
| Insulation layer
|-
| Inner layer 2
| 18um
| Copper layer
|-
| FR4 base material
| 410um
| Insulation layer
|-
| Split power plane
| 18um
| Copper layer
|-
| Prepreg
| 173um
| Insulation layer
|-
| Bottom Layer
| 35um
| Copper layer
|-
| Solder mask
| 10um
| Solder resist
|}
The PCB is 1.6mm thickness, 139.224mm x 73.666mm. It has a 6mil/6mil track spacing/clearance, with 0.25mm minimum drilled holes. Be sure to select silkscreen on both sides of the PCB. You will need to upload the ZIP file with the Gerber plot files to the PCB manufacturer. On these kinds of boards, electrical testing is the standard, but if you can choose: opt for an E-test.

[[File:CoLA_Gerber.zip]]

[[File:CoLA2.PNG|600px]]

[[File:Cola_PCB_top.jpg|600px]]

[[File:Cola_PCB_bot.jpg|600px]]

== FPGA firmware ==
All the signal processing is done inside a FPGA, which stands for Field Programmable Gate Array. It basically is a chip in which you can configure every digital function you desire (within the constraints and complexity limits of the device). While this describes how a Logic Element inside the FPGA is set up, these FPGA's nowadays also have dedicated hardware for specific functions. For example, you can build a function to store digital information (those are called flipflops), but the FPGA also has on-board memory blocks where you can store loads of data. Since we expect to generate a lot of data with our logic analyzer function, we will need to apply these memory storage blocks. The Cyclone V we chose have them in 10kbit chunks, called M10K, of which we will use 8kbit of. The FPGA has a generous 446 of these. Other dedicated hardware inside the FPGA, such as hardware multipliers called DSP blocks, we will not be needing in this design.

[[File:CoLA_FPGA_block.PNG|600px]]

The 96 inputs coming from the outside of the FPGA are first fed into a multiplexer. This block can route any of its 128 inputs to any of its 128 outputs. The benefit of this is that we can route any signals the way we want to. For example, a D0 signal on input 38 can be routed to D1 that can be all the way on input 71. This way, the data represented to the software can be interpreted more easily. An additional effect is that we can place our signals of interest onto a less wide window, and can use a higher sampling frequency to probe these signals.

Next, after the multiplexer, the data are packetized for the 32 bit data transfers to out USB interface. The 32 bit data consists, as said, of an 8 bit preamble, and a 24 bit data portion. Four of these data frames make for the full 96 bits, and therefore we can sample the data as fast as 25% of the USB clock. Since our USB clock is 100MHz, it means 25MHz is the maximum for 96 bits. If we use only half of the 96 signals, we can sample 48 bits at 50MHz. For 24 input channels, we can even use the full 100MHz sampling frequency. These 24 channels, thanks to our input multiplexer, can still be chosen out of the full 96 possible inputs.

Now that we formed the 32 bit USB transfer frames, we have to store them until the computer want to receive them. We have made room with the M10K memory blocks for 262144 frames, waiting for the computer to fetch them. These are passed onto the FT601 interface, this is the part that talks to the USB chip. It communicates sample data to, and configuration data from the USB bus. On the USB bus, data is transferred in 4Kbyte packets, and 16 of those packets form a 64 kbyte frame. Of course, there may not be that much data available, and a non-full frame indicates that we have not maxed out the available USB throughput. In the case of this maxing out happening 4 times in a row, there might be a chance that there was loss in sampling data due to a buffer overflow inside of the FPGA memory. The computer needs to keep track of this!

The generate the sample clock, the 100MHz USB clock is divided into a lower frequency. This is a point where the CoLA firmware can (and hopefully will) be improved: The FPGA incorporates fractional PLL's, blocks which can output a new clock, based of a reference clock. As opposed to the limited options with the current clock divider circuit, the fractional PLL can output a much broader range of frequencies. So if you want 21.36MHz as sampling frequency, it's possible with the fractional PLL. The sampling clock is sent to the trigger engine, where various trigger options can not be chosen. For now, only a continuous sampling can be selected. In the future, more triggering options such as a pattern trigger or a range trigger will be selectable.

The firmware for the CoLA is written in a hardware description language. This is a way to describe the workings of a digital circuit. This is interpreted by the computer and it makes an actual configuration file to write to the FPGA's SRAM. This SRAM is volatile, so if you want a more permanent functionality, you will need a configuration flash EEPROM. This will program the FPGA every time it powers up. The SRAM image in Quartus is called a Serial Object File (SOF). Because we have no programming pins brought out for the flash EEPROM, we'll need to flash the FPGA with the design of an EEPROM programmer. This will in turn program the flash with data coming from the JTAG port. This kind of sequence is done with a JTAG Indirect Configuration, or JIC file.

[[File:CoLA_VHDL.zip]]

[[File:CoLA_SOF.zip]]

[[File:CoLA_JIC.zip]]

CoLA

2019-12-14T12:34:59Z

Danny W:

CoLA

2019-12-14T12:18:33Z

Danny W:

{{Infobox logic analyzer
| image = [[File:IMG 20191206 105430.jpg|180px]]
| name = CoLA - Compact Logic Analyzer
| status = planned
| source_code_dir = -
| channels = 96/48/24
| samplerate = 25MHz/50MHz/100MHz
| samplerate_state = ?
| triggers = 32 hardware, 96 bit masked pattern
| voltages = 1.65V - 5.5V continuously
| threshold = ?
| memory = 262144 bytes
| compression = RLE, frame omission
| website = -
}}

== Introduction ==

CoLA - Compact Logic Analyzer is an USB3.0 based 96ch/25MHz, 48ch/50MHz or 24ch/100MHz logic analyzer/pattern generator, with built-in hardware pattern triggers, supporting all logic levels from 1.65V to 5.5V. It uses an Intel/Altera Cyclone V FPGA for digital aquisition and FTDI FT601B for 5Gbps USB3.0 support. To limit data transfers, it uses Run Length Encoding (RLE) as well as frame omission. Its compact design and versatility, as well as future upgradability and a DIY approach makes CoLA an interesting project.

== Theory ==

The aquisition of digital levels are done by an FPGA. The Intel/Altera Cyclone V series have sufficient speed and resources. Although versions with High Speed Serial Interfaces (HSSI's) and an embedded ARM Host Processor System (HPS) exist, a part without these is selected. The 5CEBA5F23C8 has 29.000 ALM / 77.000 LE's and 446 M10K memory blocks of resources. For now, the 150 DSP hardware multiplier modules are not used, but that can change in the future. The FPGA is also equipped with 6 PLL blocks, but only one is used.

To transfer all data to a computer, a part from FTDI is used to communicate over the USB bus. The FT601 has a 5Gbps transceiver, of which 3200Mbps can be used by the chip. The USB chip interfaces to the FPGA by means of a parallel data bus, 32 bits at 100MHz. It uses an external 30MHz crystal to generate all frequencies, and the FPGA inputs the 100MHz clock as its main clock frequency. Apart from the 32 data bits, some other arbitration signals are used.

The 96 inputs/outputs of the CoLA are equipped with logic level translators and diode clamps, to translate and protect from 1.65V to 5.5V, into the 3.3V logic levels that is used inside. The inputs are not isolated and a common ground is used. Data direction can be changed on a per-byte basis.

Inside the FPGA, the logic analyzer parts is divided into three major parts. First, the 96 inputs are routed through a connection matrix-like multiplexer, so every physical input can be routed freely onto every one of the 96 possible input channels. Secondly, the input channels are fed though a framer/packetizer, which outputs frames with a proper preamble and data compression. These frames are stored in a data buffer, ready to transmit. The third and final part is the communication interface with the FT601B chip, that sends data from the buffer and receives configuration information.

== Data transmission ==
Data transmission coming from the CoLA are formatted in 4 byte (32 bit) frames, each of which consists of a 1 byte preamble and a 3 byte data portion:

{| class="wikitable"
|-
! Preamble !! Data
|-
| 0x82 || bits 95 - 72
|-
| 0x81 || bits 71 - 48
|-
| 0x80 || bits 47 - 24
|-
| 0x00 - 0x7F || bits 23 - 0
|}

Data compression is accomplished in two ways: If nothing changes in input channel bits 95 - 72, the 0x82 frame is omitted completely. Likewise, if channel inputs 71 - 48 or 47 - 24 are unchanged, frame 0x81 and 0x80 respectively are omitted. If nothing changes in inputs 23 - 0, the preamble is increased by 1. This is called the RLE counter. If it finally reaches 0x7F, the frame is sent, and the preamble is reset to 0x00. Using this scheme, data compression can be done in realtime, and with an empty input, a 252:1 ratio can be accomplished. Of course, if the input channel data does change, the frame sent. The hardware WILL send lower preamble frames if a higher one MUST be transmitted. Also, when a USB transmission is started, it triggers a complete preamble set of 0x82, 0x81, 0x80 and 0x00-0x7F, depending on the RLE counter. This is done to provide regular reference points, similar to keyframes in a compressed video stream.

== Design ==
The overall design of the CoLA has two parts: A populated PCB, and an enclosure. The reference design uses a Hammond Manufacturing 1553DTBUBKBAT semi-transparent plastic enclosure. It has minimal exposed metal parts to minimize unwanted short circuits, as the unit is meant to be used near exposed PCB's. The enclosure has a seperate part with a lid, originally meant to house a 9V style battery. This part is used in the CoLA to expose three 34-pin headers to input all signals. Minimal modification is needed to the enclosure to accomodate the PCB.

[[File:1553DTBUBKBAT.jpg|600px]]

The single PCB holds all the electronic components that make the design work. A USB3 B-type connector is used to ruggedize the design, as it is not as fragile compared to a Micro-B or C style connector. The FTDI FT601B-Q ensures steady communication over the USB bus. The parallel bus towards the FPGA is lenght-equalized, to minimize the risk of transmission errors.

Apart from communication, the USB connector also provides supply power to the logic analyzer. The 5V input voltage is converted to a 1.1V core, 2.5V auxilary and 3.3V I/O voltage with a Linear Technology LTC3569. This is a triple buck converter, capable of outputting 1 x 1.2A and 2 x 600mA at a high efficiency of over 90%. The 1.1V core voltage is connected to the 1.2A channel, as it is expected to draw the most current.

The 5CEBA5F23C8N is a 484 ball BGA style chip, with a 1mm pitch. As far as BGA's are DIY friendly at all, this is the most DIY friendly version of any of the packages that the Cyclone V FPGA comes in. As the fanout of this part is not that easy, a 6 layer PCB must be used to route all of the signals from and to the FPGA. Decoupling capacitors are best placed close to ther power pins, so many of them are placed at the opposite PCB side of the FPGA. To store the FPGA configuration image, a EPCQ64A flash is used in Active Serial mode.

For level conversion, a large number of signals needs to be supported. Because the CoLA can also act as a digital pattern generator, data direction signals are also used to drive the six 74LVC16T245DGGR level translators. These are directly connected to the input channels. Input protection is only done by diode clamping, by using twelve SP3003-08ATG 8 channel TVS protection devices. All of the digital channels are present on three 34-pin header connectors, each of which is also equipped with a supply and ground.

== Schematics ==
The schematics of this design can be divided into 5 major blocks. The Input Connector with its Diode Protection devices, the Voltage level Translators, the FPGA as the heart of the device, the USB interface and the Power Supply. All IC's are sufficiently provided with decoupling capacitors, with 2 different values to cover a wider frequency range. The analog PLL voltages of the FPGA are additionally decoupled by means of a ferrite bead. The power supplies have a high switching frequency, but large bulk capacitors of 100uF are provided to handle any kind of current spikes.

[[File:Cola_Block_Schematic.gif]]

[[File:CoLA_Schematics.zip]] Password: sigrok

== Bill of Materials ==

{| class="wikitable"
! Amount
! Designators
! Description
! Package
|-
| 57
| C1 C3 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 C39 C41 C43 C45 C47 C49 C51 C53 C55 C61 C63 C65 C67 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C83 C112 C113 C114 C118 C120 C122 C124 C126 C128 C130 C132
| Chip Capacitor 100nF
| 0402
|-
| 42
| C2 C4 C6 C8 C10 C12 C14 C16 C18 C20 C22 C24 C26 C28 C30 C32 C34 C36 C38 C40 C42 C44 C46 C48 C50 C52 C54 C56 C62 C64 C66 C68 C82 C84 C119 C121 C123 C125 C127 C129 C131 C133
| Chip Capacitor 6.8nF
| 0402
|-
| 9
| C57 C58 C59 C60 C97 C98 C99 C100 C117
| Tantalum Capacitor 100uF 10V
| 2312
|-
| 3
| C85 C86 C87
| Chip Capacitor 22pF
| 0805
|-
| 5
| C101 C103 C104 C106 C110
| Chip Capacitor 100nF
| 0805
|-
| 1
| C111
| Chip Capacitor 470nF
| 0805
|-
| 2
| C115 C116
| Chip Capacitor 18pF
| 0805
|-
| 1
| C134
| Chip Capacitor 10uF
| 0805
|-
| 1
| F1
| Polyfuse 500mA
| 1812
|-
| 7
| L1 L2 L3 L4 L8 L9 L10
| Würth Ferrite Bead 100 Ohms 742792620
| 0603
|-
| 3
| L5 L6 L11
| Würth 2.2uH 74438335022
| 3x3x2mm
|-
| 1
| L7
| Würth Ferrite Bead 11 Ohms 7427920
| 0805
|-
| 1
| LED1
| Led Blue
| 1206
|-
| 1
| P2
| Boxheader 2x5 pin
|
|-
| 1
| P3
| Boxheader 2x17 pin
| Black
|-
| 1
| P4
| Boxheader 2x17 pin
| Grey
|-
| 1
| P5
| Boxheader 2x17 pin
| Blue
|-
| 1
| P6
| Würth 692221030100 USB3.0 B Connector
|
|-
| 1
| Q1
| BC847B NPN Transistor
| SOT23
|-
| 3
| R1 R7 R8
| Chip Resistor 25 Ohms
| 0805
|-
| 1
| R2
| Chip Resistor 4K7 Ohms
| 0805
|-
| 2
| R3 R6
| Chip Resistor 10K Ohms
| 0805
|-
| 1
| R4
| Chip Resistor 33 Ohms
| 0805
|-
| 1
| R5
| Chip Resistor 1K6 Ohms
| 0805
|-
| 1
| R9
| Chip Resistor 2K Ohms
| 0805
|-
| 1
| R10
| Chip Resistor 220 Ohms
| 0805
|-
| 13
| R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23
| Chip Resistor 1K Ohms
| 0805
|-
| 1
| R24
| Chip Resistor 75K Ohms
| 0805
|-
| 1
| R25
| Chip Resistor 200K Ohms
| 0805
|-
| 1
| R26
| Chip Resistor 47K Ohms
| 0805
|-
| 1
| R27
| Chip Resistor 15K Ohms
| 0805
|-
| 1
| R28
| Chip Resistor 51K Ohms
| 0805
|-
| 1
| R29
| Chip Resistor 24K Ohms
| 0805
|-
| 1
| RN1
| Resistor Network 4x10K Ohms
| 0612
|-
| 1
| RN2
| Resistor Network 4x1K Ohms
| 0612
|-
| 11
| RN4 RN5 RN6 RN7 RN8 RN9 RN10 RN11 RN12 RN13 RN14
| Resistor Network 4x33 Ohms
| 0612
|-
| 1
| U1
| Altera EPCQ64A
| SOICW16
|-
| 12
| U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13
| SP3003-08ATG
| MSOP10
|-
| 6
| U14 U15 U16 U17 U18 U19
| 74LVC16T245DGGR
| TSSOP48
|-
| 1
| U20
| Intel/Altera 5CEBA5F23C8N
| FBGA484
|-
| 1
| U21
| Linear Technology LTC3569EFE
| TSSOP16 EP
|-
| 1
| U24
| FTDI FT601Q-B-T
| QFN76
|-
| 1
| Y1
| 30MHz Crystal 10ppm
| 5x3.2mm 4 pad
|-
| 1
| Enclosure
| Hammond 1553DTBUBKBAT
|
|-
| 1
| PCB
| CoLA PCB
|
|}

== PCB layout ==
This is the used PCB stackup for the 6 layer board. If you order PCB's, ask for this stackup:
{| class="wikitable"
! Description
! Thickness
! Material
|-
| Solder mask
| 10um
| Solder resist
|-
| Top Layer
| 35um
| Copper layer
|-
| Prepreg
| 177um
| Insulation layer
|-
| Ground Plane
| 18um
| Copper layer
|-
| FR4 base material
| 410um
| Insulation layer
|-
| Inner layer 1
| 18um
| Copper layer
|-
| Prepreg
| 188um
| Insulation layer
|-
| Inner layer 2
| 18um
| Copper layer
|-
| FR4 base material
| 410um
| Insulation layer
|-
| Split power plane
| 18um
| Copper layer
|-
| Prepreg
| 173um
| Insulation layer
|-
| Bottom Layer
| 35um
| Copper layer
|-
| Solder mask
| 10um
| Solder resist
|}
The PCB is 1.6mm thickness, 139.224mm x 73.666mm. It has a 6mil/6mil track spacing/clearance, with 0.25mm minimum drilled holes. Be sure to select silkscreen on both sides of the PCB. You will need to upload the ZIP file with the Gerber plot files to the PCB manufacturer. On these kinds of boards, electrical testing is the standard, but if you can choose: opt for an E-test.

[[File:CoLA_Gerber.zip]]

[[File:CoLA2.PNG|600px]]

[[File:Cola_PCB_top.jpg|600px]]

[[File:Cola_PCB_bot.jpg|600px]]

== FPGA firmware ==
All the signal processing is done inside a FPGA, which stands for Field Programmable Gate Array. It basically is a chip in which you can configure every digital function you desire (within the constraints and complexity limits of the device). While this describes how a Logic Element inside the FPGA is set up, these FPGA's nowadays also have dedicated hardware for specific functions. For example, you can build a function to store digital information (those are called flipflops), but the FPGA also has on-board memory blocks where you can store loads of data. Since we expect to generate a lot of data with our logic analyzer function, we will need to apply these memory storage blocks. The Cyclone V we chose have them in 10kbit chunks, called M10K, of which we will use 8kbit of. The FPGA has a generous 446 of these. Other dedicated hardware inside the FPGA, such as hardware multipliers called DSP blocks, we will not be needing in this design.

[[File:CoLA_FPGA_block.PNG|600px]]

The 96 inputs coming from the outside of the FPGA are first fed into a multiplexer. This block can route any of its 128 inputs to any of its 128 outputs. The benefit of this is that we can route any signals the way we want to. For example, a D0 signal on input 38 can be routed to D1 that can be all the way on input 71. This way, the data represented to the software can be interpreted more easily. An additional effect is that we can place our signals of interest onto a less wide window, and can use a higher sampling frequency to probe these signals.

Next, after the multiplexer, the data are packetized for the 32 bit data transfers to out USB interface. The 32 bit data consists, as said, of an 8 bit preamble, and a 24 bit data portion. Four of these data frames make for the full 96 bits, and therefore we can sample the data as fast as 25% of the USB clock. Since our USB clock is 100MHz, it means 25MHz is the maximum for 96 bits. If we use only half of the 96 signals, we can sample 48 bits at 50MHz. For 24 input channels, we can even use the full 100MHz sampling frequency. These 24 channels, thanks to our input multiplexer, can still be chosen out of the full 96 possible inputs.

Now that we formed the 32 bit USB transfer frames, we have to store them until the computer want to receive them. We have made room with the M10K memory blocks for 262144 frames, waiting for the computer to fetch them. These are passed onto the FT601 interface, this is the part that talks to the USB chip. It communicates sample data to, and configuration data from the USB bus. On the USB bus, data is transferred in 4Kbyte packets, and 16 of those packets form a 64 kbyte frame. Of course, there may not be that much data available, and a non-full frame indicates that we have not maxed out the available USB throughput. In the case of this happening 4 times in a row, there might be a chance that there was loss in sampling data due to a buffer overflow inside of the FPGA memory. The computer needs to keep track of this!

CoLA

2019-12-14T12:10:53Z

Danny W:

File:CoLA FPGA block.PNG

2019-12-14T11:59:46Z

Danny W:

== Licensing ==
{{CC-BY-SA-3.0}}

CoLA

2019-12-14T11:59:25Z

Danny W:

File:Cola PCB bot.jpg

2019-12-14T09:20:25Z

Danny W:

== Licensing ==
{{CC-BY-SA-3.0}}

File:Cola PCB top.jpg

2019-12-14T09:19:59Z

Danny W:

== Licensing ==
{{CC-BY-SA-3.0}}

CoLA

2019-12-14T09:19:26Z

Danny W:

File:CoLA Gerber.zip

2019-12-14T08:11:22Z

Danny W:

== Licensing ==
{{CC-BY-SA-3.0}}

CoLA

2019-12-14T08:10:53Z

Danny W:

CoLA

2019-12-12T20:06:07Z

Danny W:

CoLA

2019-12-11T21:08:15Z

Danny W:

CoLA

2019-12-11T21:07:46Z

Danny W:

CoLA

2019-12-11T21:06:08Z

Danny W:

CoLA

2019-12-11T20:14:37Z

Danny W:

CoLA

2019-12-11T19:08:44Z

Danny W:

File:1553DTBUBKBAT.jpg

2019-12-11T19:06:24Z

Danny W:

== Licensing ==
{{CC-BY-SA-3.0}}

CoLA

2019-12-11T19:05:57Z

Danny W:

CoLA

2019-12-11T16:53:57Z

Danny W:

File:CoLA Schematics.zip

2019-12-11T16:52:37Z

Danny W:

== Licensing ==
{{CC-BY-SA-3.0}}

CoLA

2019-12-11T16:47:33Z

Danny W:

CoLA

2019-12-11T16:44:26Z

Danny W:

File:Cola Block Schematic.gif

2019-12-11T16:35:17Z

Danny W:

CoLA

2019-12-10T15:13:51Z

Danny W:

Supported hardware

2019-12-10T15:06:00Z

Danny W:

sigrok is intended as a flexible, cross-platform, and '''hardware-independent''' software suite, i.e., it supports various devices from many different vendors.

Here is a list of currently supported devices (various stages of completeness) in the [http://sigrok.org/gitweb/?p=libsigrok.git;a=summary latest git version of libsigrok] (fewer devices might be supported in tarball releases) and devices we plan to support in the future.

The lists are sorted by category ([[File:Nuvola OK.png|16px]] supported: [[:Category:Supported|{{PAGESINCATEGORY:Supported|pages}}]], [[File:Nuvola Orange.png|16px]] in progress: [[:Category:In progress|{{PAGESINCATEGORY:In progress|pages}}]], [[File:Nuvola Red.png|16px]] planned: [[:Category:Planned|{{PAGESINCATEGORY:Planned|pages}}]]), and alphabetically within those categories.

== Logic analyzers ==

<gallery widths="100px" heights="100px">
File:ARMFLY MINI LOGIC.png|link=ARMFLY Mini-Logic|[[File:Nuvola OK.png|16px]] [[ARMFLY Mini-Logic]] (8ch, 24MHz)
File:ASIX SIGMA 2.png|link=ASIX SIGMA|[[File:Nuvola OK.png|16px]] [[ASIX SIGMA]] (16ch, 200MHz)
File:BeagleLogic.jpg|link=BeagleLogic|[[File:Nuvola OK.png|16px]] [[BeagleLogic]] (12(max 14)ch, 100MHz)
File:Braintechnology_usb_interface_v26.png|link=Braintechnology USB Interface V2.x|[[File:Nuvola OK.png|16px]] [[Braintechnology USB Interface V2.x]] (8/16ch, 24/12MHz)
File:Braintechnology_usb_lps.png|link=Braintechnology USB-LPS|[[File:Nuvola OK.png|16px]] [[Braintechnology USB-LPS]] (8/16ch, 24/12MHz)
File:Chronovu la8 front.png|link=ChronoVu LA8|[[File:Nuvola OK.png|16px]] [[ChronoVu LA8]] (8ch, 100MHz)
File:Chronovu la16.png|link=ChronoVu LA16|[[File:Nuvola OK.png|16px]] [[ChronoVu LA16]] (16ch, 200MHz)
File:Cwav_usbee_sx.png|link=CWAV USBee SX|[[File:Nuvola OK.png|16px]] [[CWAV USBee SX]] (8ch, 24MHz)
File:Buspirate_v3.png|link=Dangerous Prototypes Buspirate|[[File:Nuvola OK.png|16px]] [[Dangerous Prototypes Buspirate]] (5ch, 1MHz)
File:Dangerous prototypes irtoy mugshot.png|link=Dangerous Prototypes USB IR Toy|[[File:Nuvola OK.png|16px]] [[Dangerous Prototypes USB IR Toy]] (1ch, 10kHz)
File:DSLogic.png|link=DreamSourceLab DSLogic|[[File:Nuvola OK.png|16px]] [[DreamSourceLab DSLogic]] (16ch, 400MHz)
File:DSLogic.png|link=DreamSourceLab DSLogic Basic|[[File:Nuvola OK.png|16px]] [[DreamSourceLab DSLogic Basic]] (16ch, 100MHz)
File:DSLogic.png|link=DreamSourceLab DSLogic Plus|[[File:Nuvola OK.png|16px]] [[DreamSourceLab DSLogic Plus]] (16ch, 400MHz)
File:DSLogic.png|link=DreamSourceLab DSLogic Pro|[[File:Nuvola OK.png|16px]] [[DreamSourceLab DSLogic Pro]] (16ch, 400MHz)
File:Eeelec xla esla100.png|link=EE Electronics ESLA100|[[File:Nuvola OK.png|16px]] [[EE Electronics ESLA100]] (8ch, 24MHz)
File:Chronovu la8 ftdi ft245rl.jpg|link=FTDI-LA|[[File:Nuvola OK.png|16px]] [[FTDI-LA]] (8ch, ~10MHz)
File:Hantek 4032l mugshot.png|link=Hantek 4032L|[[File:Nuvola OK.png|16px]] [[Hantek 4032L]] (32ch, 400MHz)
File:Hantek 6022be mugshot.png|link=Hantek 6022BL|[[File:Nuvola OK.png|16px]] [[Hantek 6022BL]] (8ch, 24MHz)
File:Hobby components hctest0006 mugshot.png|link=Hobby Components HCTEST0006|[[File:Nuvola OK.png|16px]] [[Hobby Components HCTEST0006]] (8ch, 24MHz)
File:Ikalogic_scanalogic2.png|link=IKALOGIC Scanalogic-2|[[File:Nuvola OK.png|16px]] [[IKALOGIC Scanalogic-2]] (4ch, 20MHz)
File:Ikalogic scanaplus mugshot.png|link=IKALOGIC ScanaPLUS|[[File:Nuvola OK.png|16px]] [[IKALOGIC ScanaPLUS]] (9ch, 100MHz)
File:Kingst kqs3506 la16100.png|link=KingST KQS3506-LA16100|[[File:Nuvola OK.png|16px]] [[KingST KQS3506-LA16100]] (16ch, 100/50/32/16MHz @ 3/6/9/16ch)
File:Lcsoft-miniboard-front.png|link=Lcsoft Mini Board|[[File:Nuvola OK.png|16px]] [[Lcsoft Mini Board]] (8/16ch, 24/12MHz)
File:Lecroy logicstudio16 mugshot.png|link=LeCroy LogicStudio|[[File:Nuvola OK.png|16px]] [[LeCroy LogicStudio]] (8/16ch, 1GHz/500MHz)
File:logic-shrimp-front.png|link=Logic Shrimp|[[File:Nuvola OK.png|16px]] [[Logic Shrimp]] (4ch, 20MHz)
File:Mcu123 saleae logic clone.png|link=MCU123 Saleae Logic clone|[[File:Nuvola OK.png|16px]] [[MCU123 Saleae Logic clone]] (8ch, 24MHz)
File:Meilhaus logian 16l mugshot.png|link=Meilhaus Logian-16L|[[File:Nuvola OK.png|16px]] [[Meilhaus Logian-16L]] (16ch, 200MHz)
File:Microchip_pickit2.png|link=Microchip PICkit2|[[File:Nuvola OK.png|16px]] [[Microchip PICkit2]] (3ch, 1MHz)
File:Usbee_ax_clone_front.png|link=MCU123 USBee AX Pro clone|[[File:Nuvola OK.png|16px]] [[MCU123 USBee AX Pro clone]] (8ch, 24MHz)
File:Mcupro_Logic16_overview.png|link=mcupro Logic16 clone|[[File:Nuvola OK.png|16px]] [[mcupro Logic16 clone]] (16ch, 100MHz)
File:Openbench logic sniffer front.png|link=Openbench Logic Sniffer|[[File:Nuvola OK.png|16px]] [[Openbench Logic Sniffer]] (32ch, 100MHz)
File:Prist akip 9101 mugshot.png|link=Prist AKIP-9101|[[File:Nuvola OK.png|16px]] [[Prist AKIP-9101]] (16ch, 200MHz)
File:Robomotic buglogic3.png|link=Robomotic BugLogic 3|[[File:Nuvola OK.png|16px]] [[Robomotic BugLogic 3]] (8ch, 24MHz)
File:Robomotic_minilogic.png|link=Robomotic MiniLogic|[[File:Nuvola OK.png|16px]] [[Robomotic MiniLogic]] (8ch, 24MHz)
File:Saleae Logic.png|link=Saleae Logic|[[File:Nuvola OK.png|16px]] [[Saleae Logic]] (8ch, 24MHz)
File:Saleae_Logic16_bottom.png|link=Saleae Logic16|[[File:Nuvola OK.png|16px]] [[Saleae Logic16]] (16ch, 100/50/32/16MHz @ 3/6/9/16ch)
File:Saanlima Pipistrello-OLS.png|link=Saanlima Pipistrello OLS|[[File:Nuvola OK.png|16px]] [[Saanlima Pipistrello OLS]] (32ch, 100MHz)
File:Sysclk lwla1016.png|link=Sysclk LWLA1016|[[File:Nuvola OK.png|16px]] [[Sysclk LWLA1016]] (16ch, 100MHz)
File:Sysclk lwla1034 mugshot.png|link=Sysclk LWLA1034|[[File:Nuvola OK.png|16px]] [[Sysclk LWLA1034]] (34ch, 125MHz)
File:Sysclk sla5032 mugshot.png|link=Sysclk SLA5032|[[File:Nuvola OK.png|16px]] [[Sysclk SLA5032]] (32ch, 500MHz)
File:VKTECH_thumb.jpg|link=VKTECH_saleae_clone|[[File:Nuvola OK.png|16px]] [[VKTECH_saleae_clone|VKTECH saleae clone]] (8ch, 24MHz)
File:Wayengineer saleae16.png|link=WayEngineer Saleae16|[[File:Nuvola OK.png|16px]] [[WayEngineer Saleae16]] (16ch, 100/50/32/16MHz @ 3/6/9/16ch)
File:Zeroplus Logic Cube.png|link=ZEROPLUS Logic Cube LAP-C(16032)|[[File:Nuvola OK.png|16px]] [[ZEROPLUS Logic Cube LAP-C(16032)]] (16ch, 100MHz)
File:Zeroplus Logic Cube.png|link=ZEROPLUS Logic Cube LAP-C(322000)|[[File:Nuvola OK.png|16px]] [[ZEROPLUS Logic Cube LAP-C(322000)]] (32ch, 200MHz)
File:Zeroplus_lap-16128u.png|link=ZEROPLUS LAP-16128U|[[File:Nuvola OK.png|16px]] [[ZEROPLUS LAP-16128U]] (16ch, 200MHz)
</gallery>

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery>
File:Acute_pkla1216.png|link=Acute PKLA-1216|[[File:Nuvola Red.png|16px]] [[Acute PKLA-1216]] (16ch, 200MHz)
File:Arduino_Uno-R3.jpg|link=Arduino|[[File:Nuvola Orange.png|16px]] [[Arduino]] (6ch, 4MHz)
File:ASIX Omega.png|link=ASIX OMEGA|[[File:Nuvola Red.png|16px]] [[ASIX OMEGA]] (16ch, 400MHz)
File:IMG 20191206 105430.jpg|link=CoLA|[[File:Nuvola Red.png|16px]] [[CoLA]] (96/48/24ch, 25/50/100MHz)
File:Hsa-logic.png|link=HSA Logic|[[File:Nuvola Red.png|16px]] [[HSA Logic]] (8ch, 6.25MHz)
File:Ideofy_la_08.png|link=Ideofy LA-08|[[File:Nuvola Red.png|16px]] [[Ideofy LA-08]] (8ch, 96/60/30MHz @ 2/4/8ch)
File:Intronix Logicport.png|link=Intronix Logicport LA1034|[[File:Nuvola Red.png|16px]] [[Intronix Logicport LA1034]] (34ch, 500MHz)
File:Kingst la2016 mugshot.png|link=Kingst LA2016|[[File:Nuvola Red.png|16px]] [[Kingst LA2016]] (16ch, 200MHz)
File:Sigrok_logo_no_text_transparent_512.png|link=Link Instruments LA-5580|[[File:Nuvola Red.png|16px]] [[Link Instruments LA-5580]] (80ch, 500MHz)
File:Minila parport.png|link=MiniLA|[[File:Nuvola Red.png|16px]] [[MiniLA]] (32ch, 100MHz)
File:Minila_mockup.png|link=MiniLA Mockup|[[File:Nuvola Red.png|16px]] [[MiniLA Mockup]] (32ch, 100MHz)
File:Noname_la16_mugshot.png|link=Noname LA16|[[File:Nuvola Red.png|16px]] [[Noname LA16]] (16ch, 100MHz)
File:Noname xl logic16 100m mugshot.png|link=Noname XL-LOGIC16-100M|[[File:Nuvola Orange.png|16px]] [[Noname XL-LOGIC16-100M]] (16ch, 100/50/32/16MHz @ 3/6/9/16ch)
File:Rockylogic_ant8.png|link=RockyLogic Ant8|[[File:Nuvola Red.png|16px]] [[RockyLogic Ant8]] (8ch, 500MHz)
File:RockyLogic Ant18e.png|link=RockyLogic Ant18e|[[File:Nuvola Red.png|16px]] [[RockyLogic Ant18e]] (8ch, 1GHz)
File:Sysclk lwla2034 mugshot.png|link=Sysclk LWLA2034|[[File:Nuvola Red.png|16px]] [[Sysclk LWLA2034]] (34ch, 200MHz)
File:Techtools_digiview_dv1-100.png|link=TechTools DigiView DV1-100|[[File:Nuvola Red.png|16px]] [[TechTools DigiView DV1-100]] (18ch, 100MHz)
File:Tektronix TLA5204 1000.png|link=Tektronix TLA520X|[[File:Nuvola Red.png|16px]] [[Tektronix TLA520X]] (128ch, 2Ghz)
File:Xmos xtag2.png|link=XMOS XTAG-2|[[File:Nuvola Red.png|16px]] [[XMOS XTAG-2]] (?ch, 50MHz)
File:Zlg_la1032.png|link=ZLG LA1032|[[File:Nuvola Red.png|16px]] [[ZLG LA1032]] (32ch, 100MHz)
</gallery>

== Mixed-signal devices ==

<gallery widths=105px heights=105px>
File:Armfly_ax_pro.png|link=ARMFLY AX-Pro|[[File:Nuvola OK.png|16px]] [[ARMFLY AX-Pro]] (8ch, 24MHz; 1ch analog, 3MHz BW)
File:Sysclk ax pro mugshot.png|link=Sysclk AX-Pro|[[File:Nuvola OK.png|16px]] [[Sysclk AX-Pro]] (8ch, 24MHz; 1ch analog, 3MHz BW)
File:Esla201a.png|link=EE Electronics ESLA201A|[[File:Nuvola OK.png|16px]] [[EE Electronics ESLA201A]] (8ch, 24MHz; 1ch analog, 3MHz BW)
File:Ht usbee axpro v5 mugshot.png|link=HT USBee-AxPro|[[File:Nuvola OK.png|16px]] [[HT USBee-AxPro]] (8ch, 24MHz; 1ch analog, 3MHz BW)
File:LeCroy_WaveSurfer_24Xs-A_front.png|link=LeCroy oscilloscope series|[[File:Nuvola OK.png|16px]] [[LeCroy oscilloscope series]] (various)
File:Noname lht00su1 mugshot.png|link=Noname LHT00SU1|[[File:Nuvola OK.png|16px]] [[Noname LHT00SU1]] (8ch, 24MHz; 1ch analog, 3MHz BW)
File:Rigol DS1052E.png|link=Rigol DS1000 series|[[File:Nuvola OK.png|16px]] [[Rigol DS1000 series|Rigol DS1000D series]] (16ch, 2ch analog, 50-150MHz BW)
File:Sigrok_logo_no_text_transparent_512.png|link=Rigol DS4000 series|[[File:Nuvola OK.png|16px]] [[Rigol DS4000 series]] (0/16ch , 2-4ch analog, 2-4GS/s, 100MHz/200MHz/350MHz/500MHz BW)
File:Rigol_VS5202D.png|link=Rigol VS5000 series|[[File:Nuvola OK.png|16px]] [[Rigol VS5000 series|Rigol VS5000D series]] (16ch, 2ch analog, 20-200MHz BW)
File:Sigrok_logo_no_text_transparent_512.png|link=Rohde&Schwarz HMO3000 series|[[File:Nuvola OK.png|16px]] [[Rohde&Schwarz HMO 3000 series]] (16ch, 2/4ch analog, 4GS/s, 300-500MHz BW)
File:Saleae Logic Pro 16 bottom.jpg|link=Saleae Logic Pro 16|[[File:Nuvola OK.png|16px]] [[Saleae Logic Pro 16]] (4/16ch, 500/100MHz; 16ch analog, 50MSa/s, 5MHz BW)
File:Siglent_SDS1202X-E_front.png|link=Siglent SDS1000X series|[[File:Nuvola OK.png|16px]] [[Siglent SDS1000X series]] (16ch, 2ch analog, 1GSa/s, 200/100MHz BW)
File:sds2304x-mugshot.png|link=Siglent SDS2000X series|[[File:Nuvola OK.png|16px]] [[Siglent SDS2000X series]] (16ch, 2/4ch analog, 2GSa/s, 300/200/150/100/70MHz BW)
File:Yokogawa DLM2000 front.png|link=Yokogawa DLM2000 series|[[File:Nuvola OK.png|16px]] [[Yokogawa DLM2000 series]] (8ch, 2/4ch analog, 2.5GSa/s, 200/350/500MHz BW)
File:Xzl studio ax mugshot.png|link=XZL_Studio AX|[[File:Nuvola OK.png|16px]] [[XZL_Studio AX]] (8ch, 24MHz; 1ch analog, 3MHz BW)
File:Xzl studio-dx mugshot.png|link=XZL_Studio DX|[[File:Nuvola OK.png|16px]] [[XZL_Studio DX]] (16ch, 24MHz; 2ch analog), Analog not supported
</gallery>

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery>
File:Agilent_MSO7104A.png|link=Agilent MSO7104A|[[File:Nuvola Red.png|16px]] [[Agilent MSO7104A]] (16ch, ?; 4ch analog, 2GSa/s, 1GHz BW)
File:BitScope BS10.png|link=BitScope BS10|[[File:Nuvola Red.png|16px]] [[BitScope BS10]] (8ch, 40MHz; 2ch analog, 20MSa/s, ? BW)
File:Digilent_analog_discovery.png|link=Digilent Analog Discovery|[[File:Nuvola Red.png|16px]] [[Digilent Analog Discovery]] (16ch, 100MHz; 2ch analog, 100MSa/s, 5MHz BW)
File:Hantek_1008C.png|link=Hantek 1008C|[[File:Nuvola Red.png|16px]] [[Hantek 1008C]] (8ch)
File:Ht usbee dxpro mugshot.png|link=HT USBee-DxPro|[[File:Nuvola Red.png|16px]] [[HT USBee-DxPro]] (16ch, 24MHz; 2ch analog)
File:Lab nation smartscope mugshot.png|link=LabNation SmartScope|[[File:Nuvola Red.png|16px]] [[LabNation SmartScope]] (8ch, 100MHz; 2ch analog, 100MSa/s, 45MHz BW)
File:Link Instruments MSO-19 front.png|link=Link Instruments MSO-19|[[File:Nuvola Red.png|16px]] [[Link Instruments MSO-19]] (8ch, 200MHz; 1ch analog, 200MSa/s, 60MHz BW)
File:Meilhaus_mephisto_scope1.png|link=Meilhaus MEphisto Scope1|[[File:Nuvola Red.png|16px]] [[Meilhaus MEphisto Scope1]] (16ch, 100kHz; 2ch analog, 1MSa/s, 500kHz BW)
File:Polabs_poscope_basic2.png|link=PoLabs PoScope Basic2|[[File:Nuvola Red.png|16px]] [[PoLabs PoScope Basic2]] (16ch, 8MHz; 2ch analog, 200kSa/s, ? BW)
File:QuantAsylum QA100.png|link=QuantAsylum QA100|[[File:Nuvola Red.png|16px]] [[QuantAsylum QA100]] (12ch; 2ch analog)
File:Saleae_Logic8_case_bottom.jpg|link=Saleae Logic8|[[File:Nuvola Red.png|16px]] [[Saleae Logic8]] (3/6/7/8ch, 100/50/40/25MHz; 8ch analog, 10MSa/s, 1MHz BW)
File:Saleae_logic_pro_8-bottom.png|link=Saleae Logic Pro 8|[[File:Nuvola Red.png|16px]] [[Saleae Logic Pro 8]] (4/8ch, 500/100MHz; 8ch analog, 50MSa/s, 5MHz BW)
File:Picoscope 3205D MSO fp.jpg|link=Pico Technology PicoScope 3205D MSO|[[File:Nuvola Red.png|16px]] [[Pico Technology PicoScope 3205D MSO]] (16ch, 100MHz; 2ch analog, 1/0.5GS/s, 100MHz BW)
File:DSO3254A.jpg|link=Hantek DSO3254A|[[File:Nuvola Red.png|16px]] [[Hantek DSO3254A]] (16ch, 250MHz; 4ch analog, 1GS/s, 250MHz BW; 1 ch func/arb generator, 200MHz)

</gallery>

== Oscilloscopes ==

<gallery widths=100px heights=100px>
File:Agilent DSO1014A.png|link=Agilent DSO1000 series|[[File:Nuvola OK.png|16px]] [[Agilent DSO1000 series]] (2-4ch, 2GS/s, 60-200MHz BW)
File:Fluke_Scopemeter_199B.png|link=Fluke ScopeMeter 199B|[[File:Nuvola OK.png|16px]] [[Fluke ScopeMeter 199B]] (2ch, 2.5GS/s, 200MHz BW)
File:Voltcraft dso-6060c mugshot.png|link=GW Instek GDS-800 series|[[File:Nuvola OK.png|16px]] [[GW Instek GDS-800 series]] (2ch, 25GS/s, 60-250MHz BW)
File:Hameg HMO2024.png|link=Hameg HMO compact series|[[File:Nuvola OK.png|16px]] [[Hameg HMO compact series]] (2-4ch, 2GS/s, 70-200MHz BW)
File:Hantek 6022be mugshot.png|link=Hantek 6022BE|[[File:Nuvola OK.png|16px]] [[Hantek 6022BE]] (2ch, 48MS/s, 20MHz BW)
File:Hantek DSO-2090.png|link=Hantek DSO-2090|[[File:Nuvola OK.png|16px]] [[Hantek DSO-2090]] (2ch, 100MS/s, 40MHz)
File:Hung chang dso 2100 mugshot.png|link=Hung-Chang_DSO-2100|[[File:Nuvola OK.png|16px]] [[Hung-Chang DSO-2100]] (2ch, 100MS/s, 30MHz BW)
File:Rigol DS1052E.png|link=Rigol DS1000 series|[[File:Nuvola OK.png|16px]] [[Rigol DS1000 series|Rigol DS1000E series]] (2ch, 1GS/s, 50-150MHz BW)
File:Rigol DS1074Z front.png|link=Rigol DS1000Z series|[[File:Nuvola OK.png|16px]] [[Rigol DS1000Z series|Rigol DS1000Z series]] (4ch, 1GS/s, 50-100MHz BW)
File:Rigol-ds2072 mugshot.png|link=Rigol DS2000 series|[[File:Nuvola OK.png|16px]] [[Rigol DS2000 series]] (2ch, 2GS/s, 70-200MHz BW)
File:Rigol_VS5202D.png|link=Rigol VS5000 series|[[File:Nuvola OK.png|16px]] [[Rigol VS5000 series]] (2ch, 20-200MHz BW)
File:Rocktech bm102 mugshot.png|link=Rocktech BM102|[[File:Nuvola OK.png|16px]] [[Rocktech BM102]] (2ch, 50MS/s, 20MHz BW)
File:RS HMO1002.png|link=Rohde&Schwarz HMO 1002 series|[[File:Nuvola OK.png|16px]] [[Rohde&Schwarz HMO 1002 series]] (2ch, 1GS/s, 50-100MHz BW)
File:Dds120 mugshot.png|link=SainSmart DDS120|[[File:Nuvola OK.png|16px]] [[SainSmart DDS120]] (2ch, 50MS/s, 20MHz BW)
File:YiXingDianZi-MDSO.png|link=YiXingDianZi MDSO|[[File:Nuvola OK.png|16px]] [[YiXingDianZi MDSO]] (2ch, 48MS/s, 20MHz BW)
</gallery>

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery>
File:Dreamsourcelab dscope c20p front.jpg|link=DreamSourceLab DScope C20P|[[File:Nuvola Red.png|16px]] [[DreamSourceLab DScope C20P]] (2ch, 200MS/s, 50MHz BW)
File:Fluke scopemeter123.png|link=Fluke ScopeMeter 123|[[File:Nuvola Red.png|16px]] [[Fluke ScopeMeter 123]] (2ch, 25MS/s, 20MHz BW)
File:Focussz_fosc21_mugshot.png|link=Focussz Fosc21|[[File:Nuvola Red.png|16px]] [[Focussz Fosc21]] (2ch, 8kS/s, 3kHz BW)
File:Sigrok_logo_no_text_transparent_512.png|link=GW Instek GDS-2000 series|[[File:Nuvola Red.png|16px]] [[GW Instek GDS-2000 series]] (2ch, 1GS/s, 60MHz/100MHz/200MHz BW)
File:Hantek front.jpg|link=Hantek 6052BE|[[File:Nuvola Red.png|16px]] [[Hantek 6052BE]] (2ch, 150MS/s, 50MHz BW)
File:Hantek 6254bd mugshot.png|link=Hantek 6254BD|[[File:Nuvola Red.png|16px]] [[Hantek 6254BD]] (4ch, 1GS/s, 250MHz BW)
File:Sigrok_logo_no_text_transparent_512.png|link=Hantek DSO-1200|[[File:Nuvola Red.png|16px]] [[Hantek DSO-1200]] (2ch, 500MS/s, 200MHz BW)
File:Hantek_DSO_2100_usb.jpg|link=Hantek DSO-2100|[[File:Nuvola Red.png|16px]] [[Hantek DSO-2100]] (2ch, 100M/s, 30MHz BW)
File:Hantek_PSO2020_0.JPG|link=Hantek PSO2020|[[File:Nuvola Red.png|16px]] [[Hantek PSO2020]] (1ch, 96MS/s, 20MHz BW)
File:Hantek dso2250 mugshot.png|link=Hantek DSO-2250|[[File:Nuvola Red.png|16px]] [[Hantek DSO-2250]] (2ch, 250MS/s, 100MHz BW)
File:Hantek dso-5200a device front.png|link=Hantek DSO-5200A|[[File:Nuvola Red.png|16px]] [[Hantek DSO-5200A]] (2ch, 250MS/s, 200MHz BW)
File:Hantek iDSO1070A.JPG|link=Hantek iDSO1070|[[File:Nuvola Red.png|16px]] [[Hantek iDSO1070]] (2ch, 250MS/s, 70MHz BW)
File:Sigrok_logo_no_text_transparent_512.png|link=Hantek iDSO1070A|[[File:Nuvola Red.png|16px]] [[Hantek iDSO1070A]] (2ch, 125MS/s, 70MHz BW)
File:Usbduxfast.png|link=Incite Technology USB-DUXfast|[[File:Nuvola Red.png|16px]] [[Incite Technology USB-DUXfast]] (16ch, 3MHz, ? BW)
File:Instrustar-IDS205A CaseFront.jpg|link=Instrustar ISDS205A|[[File:Nuvola Red.png|16px]] [[Instrustar_ISDS205A]] (2ch, 48MS/s, 20MHz BW)
File:Loto_OSC802.jpg|link=Loto OSC802|[[File:Nuvola Red.png|16px]] [[Loto OSC802]] (2ch, 80MS/s, 20MHz BW)
File:OsciPrime.png|link=Nexus-Computing OsciPrime|[[File:Nuvola Red.png|16px]] [[Nexus-Computing OsciPrime]] (2ch, ?MS/s, 3.3MHz-8MHz BW)
File:Sigrok_logo_no_text_transparent_512.png|link=Owon SDS series|[[File:Nuvola Red.png|16px]] [[Owon SDS series]] (2ch, 0.5-3.2GS/s, 60-300MHz BW)
File:Picoscope 2203.png|link=Pico Technology PicoScope 2203|[[File:Nuvola Red.png|16px]] [[Pico Technology PicoScope 2203]] (40/20MS/s, 5MHz BW)
File:PicoScope_2205.png|link=Pico Technology PicoScope 2205|[[File:Nuvola Red.png|16px]] [[Pico Technology PicoScope 2205]] (200/100MS/s, 25MHz BW)
File:Picoscope 3206.png|link=Pico Technology PicoScope 3206|[[File:Nuvola Red.png|16px]] [[Pico Technology PicoScope 3206]] (200/100MS/s, 200MHz BW)
File:Picoscope 5203.png|link=Pico Technology PicoScope 5203|[[File:Nuvola Red.png|16px]] [[Pico Technology PicoScope 5203]] (1/0.5GS/s, 250MHz BW)
File:Sainsmart dds140 mugshot.png|link=SainSmart DDS140|[[File:Nuvola Red.png|16px]] [[SainSmart DDS140]] (2ch, 200MS/s, 40MHz BW)
File:Tektronix tds2024b mugshot.png|link=Tektronix TDS2000B series|[[File:Nuvola Red.png|16px]] [[Tektronix TDS2000B series]] (2-4ch, 1-2GS/s, 60-200MHz BW)
File:UNI-T UTD2042C.png|link=UNI-T UTD2042C|[[File:Nuvola Red.png|16px]] [[UNI-T UTD2042C]] (2ch, 500MS/s, 40MHz BW)
File:Velleman PCSU1000.png|link=Velleman PCSU1000|[[File:Nuvola Red.png|16px]] [[Velleman PCSU1000]] (2ch, 1GS/s, 50MHz BW)
File:VellemanWFS210.png|link=Velleman WFS210|[[File:Nuvola Red.png|16px]] [[Velleman WFS210]] (2ch, 10MS/s, ?? MHz BW)
File:Voltcraft dso-220 usb.png|link=Voltcraft DSO-220|[[File:Nuvola Red.png|16px]] [[Voltcraft DSO-220]] (2ch, 60MS/s, 20MHz BW)
File:Voltcraft DSO-3062C.png|link=Voltcraft DSO-3062C|[[File:Nuvola Orange.png|16px]] [[Voltcraft DSO-3062C]] (2ch, 1GS/s, 60MHz BW)
</gallery>

== Multimeters ==

<gallery widths="100px" heights="100px">
File:Agilent_34405A.png|link=Agilent_34405A|[[file:Nuvola OK.png|16px]] [[Agilent 34405A]] (120000 counts, USB TMC)
File:Agilent U1232A.png|link=Agilent U12xxx series|[[File:Nuvola OK.png|16px]] [[Agilent U12xxx series]] (USB/Bluetooth)
File:Bbc gm m2110 mugshot.png|link=BBC Goertz Metrawatt M2110|[[File:Nuvola OK.png|16px]] [[BBC Goertz Metrawatt M2110]] (30000 counts, RS232)
File:Brymen BM257.png|link=Brymen BM257|[[File:Nuvola OK.png|16px]] [[Brymen BM257]] (6000 counts, RS232/USB)
File:Brymen bm257s mugshot.png|link=Brymen BM257s|[[File:Nuvola OK.png|16px]] [[Brymen BM257s]] (6000 counts, RS232/USB)
File:Bm_857_mugshot_500000.png|link=Brymen BM857|[[File:Nuvola OK.png|16px]] [[Brymen BM857]] (50000 counts, RS232)
File:Bm869_mugshot.png|link=Brymen BM869|[[File:Nuvola OK.png|16px]] [[Brymen BM869]] (50000 counts, USB)
File:Digitek_dt4000zc_device_front.png|link=Digitek DT4000ZC|[[File:Nuvola OK.png|16px]] [[Digitek DT4000ZC]] (4000 counts, RS232)
File:Eevblog 121gw mugshot.png|link=EEVBlog 121GW|[[File:Nuvola OK.png|16px]] [[EEVBlog 121GW]] (50000 counts, BLE, SD)
File:Fluke 187.png|link=Fluke 187/189|[[File:Nuvola OK.png|16px]] [[Fluke 187/189]] (50000 counts, RS232)
File:Fluke 287.png|link=Fluke 287/289|[[File:Nuvola OK.png|16px]] [[Fluke 287/289]] (50000 counts, RS232)
File:Fluke_45_mugshot.png|link=Fluke 45|[[File:Nuvola OK.png|16px]] [[Fluke 45]] (100000 counts, GPIB/RS232)
File:Gmc metrahit 14a logo.png|link=Gossen Metrawatt Metrahit 14A|[[File:Nuvola OK.png|16px]] [[Gossen Metrawatt Metrahit 14A]] (3100 counts, RS232)
File:Gossen Metrawatt Metrahit 16I small.png|link=Gossen Metrawatt Metrahit 16I|[[File:Nuvola OK.png|16px]] [[Gossen Metrawatt Metrahit 16I]] (3100 counts, RS232)
File:Gossen Metrawatt Metrahit 18S small.png|link=Gossen Metrawatt Metrahit 18S|[[File:Nuvola OK.png|16px]] [[Gossen Metrawatt Metrahit 18S]] (31000 counts, RS232)
File:Gossen Metrawatt Metrahit 25S Logo.png|link=Gossen Metrawatt Metrahit 25S|[[File:Nuvola OK.png|16px]] [[Gossen Metrawatt Metrahit 25S]] (31000 counts, RS232/USB)
File:Gmc metrahit 29s logo.png|link=Gossen Metrawatt Metrahit 29S|[[File:Nuvola OK.png|16px]] [[Gossen Metrawatt Metrahit 29S]] (310000 counts, RS232/USB)
File:Gmc kmm2002 logo.png|link=Gossen Metrawatt T-Com KMM2002|[[File:Nuvola OK.png|16px]] [[Gossen Metrawatt T-Com KMM2002]] (3100 counts, RS232)
File:HP_3457a_sigrok_teaser.png|link=HP 3457A|[[File:Nuvola OK.png|16px]] [[HP 3457A]] (7.5 digits, GPIB)
File:Hp3478a mugshot.png|link=HP 3478A|[[File:Nuvola OK.png|16px]] [[HP 3478A]] (5.5 digits, GPIB)
File:HT410 logo.png|link=HT Instruments HT410|[[File:Nuvola OK.png|16px]] [[HT Instruments HT410]] (3100 counts, RS232)
File:100px_Idm103n.png|link=ISO-TECH IDM103N|[[File:Nuvola OK.png|16px]] [[ISO-TECH IDM103N]] (4000 counts, RS232)
File:keysight-34465a-mugshot.png|link=Keysight 34465A|[[File:Nuvola OK.png|16px]] [[Keysight 34465A]] (1200000 counts, LAN/USB/GPIB)
File:Mastech mas345 device front.png|link=MASTECH MAS345|[[File:Nuvola OK.png|16px]] [[MASTECH MAS345]] (4000 counts, RS232)
File:Mastech_ms2115b_mugshot.png|link=MASTECH MS2115B|[[File:Nuvola OK.png|16px]] [[MASTECH MS2115B]] (6000 counts, USB)
File:Mastech ms8250b mugshot.png|link=MASTECH MS8250B|[[File:Nuvola OK.png|16px]] [[MASTECH MS8250B]] (4000 counts, USB)
File:Mastech ms8250d mugshot.png|link=MASTECH MS8250D|[[File:Nuvola OK.png|16px]] [[MASTECH MS8250D]] (6600 counts, USB)
File:Metex m4650cr mugshot.png|link=Metex M-4650CR|[[File:Nuvola OK.png|16px]] [[Metex M-4650CR]] (20000 counts, RS232)
File:Metex_me-31.png|link=Metex ME-31|[[File:Nuvola OK.png|16px]] [[Metex ME-31]] (4000 counts, RS232)
File:Metrix mx56c.png|link=Metrix MX56C|[[File:Nuvola OK.png|16px]] [[Metrix MX56C]] (50000 counts, RS232)
File:Mooshimeter_mugshot.png|link=Mooshim Engineering Mooshimeter|[[File:Nuvola OK.png|16px]] [[Mooshim Engineering Mooshimeter]] (24bit, BLE)
File:Norma dm950.png|link=Norma DM950|[[File:Nuvola OK.png|16px]] [[Norma DM950]] (21000 counts, RS232)
File:Pce-pce-dm32.png|link=PCE PCE-DM32|[[File:Nuvola OK.png|16px]] [[PCE PCE-DM32]] (4000 counts, RS232)
File:Peaktech 3330 mugshot.png|link=PeakTech 3330|[[File:Nuvola OK.png|16px]] [[PeakTech 3330]] (4000 counts, RS232/USB)
File:Metex_me-31.png|link=PeakTech 3410|[[File:Nuvola OK.png|16px]] [[PeakTech 3410]] (4000 counts, RS232)
File:Peaktech3415_top.png|link=PeakTech 3415|[[File:Nuvola OK.png|16px]] [[PeakTech 3415]] (6000 counts, USB)
File:Peaktech 4370 device front.png|link=PeakTech 4370|[[File:Nuvola OK.png|16px]] [[PeakTech 4370]] (2000 counts, RS232)
File:Peaktech 4390a metex m-3860m mugshot.png|link=PeakTech 4390A|[[File:Nuvola OK.png|16px]] [[PeakTech 4390A]] (4000 counts, RS232)
File:Rs_22_168_mugshot.png|link=RadioShack 22-168|[[File:Nuvola OK.png|16px]] [[RadioShack 22-168]] (2000 counts, RS232)
File:Rs_22-805_front.png|link=RadioShack 22-805|[[File:Nuvola OK.png|16px]] [[RadioShack 22-805]] (4000 counts, RS232)
File:radioshack_22_812_front.png|link=RadioShack 22-812|[[File:Nuvola OK.png|16px]] [[RadioShack 22-812]] (4000 counts, RS232)
File:siemens_b1026_logo.png|link=Siemens B1026|[[File:Nuvola OK.png|16px]] [[Siemens B1026]] (21000 counts, RS232)
File:Siemens B1105 small.png|link=Siemens B1105|[[File:Nuvola OK.png|16px]] [[Siemens B1105]] (310000 counts, RS232/USB)
File:Sparkfun 70c mugshot.png|link=SparkFun 70C|[[File:Nuvola OK.png|16px]] [[SparkFun 70C]] (6000 counts, USB)
File:Tecpel dmm8061.png|link=Tecpel DMM-8061|[[File:Nuvola OK.png|16px]] [[Tecpel DMM-8061]] (4000 counts, RS232/USB)
File:Tp4000zc_front.png|link=TekPower TP4000ZC|[[File:Nuvola OK.png|16px]] [[TekPower TP4000ZC]] (4000 counts, RS232)
File:Tenma 72-7730.png|link=Tenma 72-7730|[[File:Nuvola OK.png|16px]] [[Tenma 72-7730]] (20000 counts, RS232/USB)
File:Tenma 72-7732.png|link=Tenma 72-7732|[[File:Nuvola OK.png|16px]] [[Tenma 72-7732]] (40000 counts, RS232/USB)
File:Tenma 72-7745.png|link=Tenma 72-7745|[[File:Nuvola OK.png|16px]] [[Tenma 72-7745]] (4000 counts, RS232/USB)
File:Tenma 72-7750.png|link=Tenma 72-7750|[[File:Nuvola OK.png|16px]] [[Tenma 72-7750]] (6000 counts, RS232/USB)
File:Tenma 72-9380A.png|link=Tenma 72-9380A|[[File:Nuvola OK.png|16px]] [[Tenma 72-9380A]] (40000 counts, RS232/USB)
File:Ut60e_-_front_-_alpha.png|link=UNI-T UT60E|[[File:Nuvola OK.png|16px]] [[UNI-T UT60E]] (4000 counts, RS232/USB)
File:Uni-t ut61b mugshot.png|link=UNI-T UT61B|[[File:Nuvola OK.png|16px]] [[UNI-T UT61B]] (4000 counts, RS232/USB)
File:Uni-t ut61c mugshot.png|link=UNI-T UT61C|[[File:Nuvola OK.png|16px]] [[UNI-T UT61C]] (6000 counts, RS232/USB)
File:Uni t ut61d device.png|link=UNI-T UT61D|[[File:Nuvola OK.png|16px]] [[UNI-T UT61D]] (6000 counts, RS232/USB)
File:Old ver front.png|link=UNI-T UT61E|[[File:Nuvola OK.png|16px]] [[UNI-T UT61E]] (22000 counts, RS232/USB)
File:Ut71c mugshot.png|link=UNI-T UT71C|[[File:Nuvola OK.png|16px]] [[UNI-T UT71C]] (40000 counts, RS232/USB)
File:Va_va18b.png|link=V&A VA18B|[[File:Nuvola OK.png|16px]] [[V&A VA18B]] (6000 counts, USB)
File:Va va40b mugshot.png|link=V&A VA40B|link=V&A VA40B|[[File:Nuvola OK.png|16px]] [[V&A VA40B]] (6000 counts, USB)
File:DVM4100.png|link=Velleman DVM4100|link=Velleman DVM4100|[[File:Nuvola OK.png|16px]] [[Velleman DVM4100]] (6000 counts, USB)
File:Victor 70C.png|link=Victor 70C|[[File:Nuvola OK.png|16px]] [[Victor 70C]] (4000 counts, USB)
File:Victor 86c device front.png|link=Victor 86C|[[File:Nuvola OK.png|16px]] [[Victor 86C]] (4000 counts, USB)
File:Voltcraft m-3650cr.png|link=Voltcraft M-3650CR|[[File:Nuvola OK.png|16px]] [[Voltcraft M-3650CR]] (2000 counts, RS232)
File:Voltcraft_M-3650D_transparent.png|link=Voltcraft M-3650D|[[File:Nuvola OK.png|16px]] [[Voltcraft M-3650D]] (2000 counts, RS232)
File:Voltcraft m4650cr.png|link=Voltcraft M-4650CR|[[File:Nuvola OK.png|16px]] [[Voltcraft M-4650CR]] (20000 counts, RS232)
File:Voltcraft ME-42 logo.png|link=Voltcraft ME-42|[[File:Nuvola OK.png|16px]] [[Voltcraft ME-42]] (4000 counts, RS232)
File:Voltcraft vc820 device.png|link=Voltcraft VC-820|[[File:Nuvola OK.png|16px]] [[Voltcraft VC-820]] (4000 counts, RS232/USB)
File:Voltcraft vc830.png|link=Voltcraft VC-830|[[File:Nuvola OK.png|16px]] [[Voltcraft VC-830]] (6000 counts, RS232/USB)
File:Voltcraft vc840 device front.png|link=Voltcraft VC-840|[[File:Nuvola OK.png|16px]] [[Voltcraft VC-840]] (4000 counts, RS232/USB)
File:Voltcraft vc870 mugshot.png|link=Voltcraft VC-870|[[File:Nuvola OK.png|16px]] [[Voltcraft VC-870]] (40000 counts, RS232/USB)
File:Voltcraft vc920.png|link=Voltcraft VC-920|[[File:Nuvola OK.png|16px]] [[Voltcraft VC-920]] (40000/4000 counts, RS232/USB)
File:Voltcraft vc940.png|link=Voltcraft VC-940|[[File:Nuvola OK.png|16px]] [[Voltcraft VC-940]] (40000/4000 counts, RS232/USB)
File:Voltcraft vc96 top.jpg|link=Voltcraft VC-96|[[File:Nuvola OK.png|16px]] [[Voltcraft VC-96]] (4000 counts, RS232)
</gallery>

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery>
File:Appa 107.png|link=APPA 107|[[File:Nuvola Red.png|16px]] [[APPA 107]] (4000 / 20000 counts, RS232)
File:Digitek dt8000.png|link=Digitek DT8000|[[File:Nuvola Red.png|16px]] [[Digitek DT8000]] (8000 counts, RS232)
File:Digitek dt80000.png|link=Digitek DT80000|[[File:Nuvola Red.png|16px]] [[Digitek DT80000]] (80000 counts, RS232)
File:Escort 179 device front.png|link=Escort 179|[[File:Nuvola Red.png|16px]] [[Escort 179]] (10000 counts, RS232)
File:Sigrok_logo_no_text_transparent_512.png|link=Gossen Metrawatt Metrahit 28C|[[File:Nuvola Red.png|16px]] [[Gossen Metrawatt Metrahit 28C]] (310000 counts, RS232/USB)
File:Sigrok_logo_no_text_transparent_512.png|link=Gossen Metrawatt Metrahit 28S|[[File:Nuvola Red.png|16px]] [[Gossen Metrawatt Metrahit 28S]] (310000 counts, RS232/USB)
File:Gossen metrahit 30m.png|link=Gossen-Metrawatt METRAHIT 30M|[[File:Nuvola Red.png|16px]] [[Gossen-Metrawatt METRAHIT 30M]] (1200000 counts, RS232/USB)
File:Sigrok_logo_no_text_transparent_512.png|link=Gossen Metrawatt Metrahit X-Tra|[[File:Nuvola Red.png|16px]] [[Gossen Metrawatt Metrahit X-Tra]] (12000 counts, USB)
File:Sigrok_logo_no_text_transparent_512.png|link=GW Instek GDM-8251A|[[File:Nuvola Red.png|16px]] [[GW Instek GDM-8251A]] (120000 counts, RS232/USB/DigitalIO)
File:Sigrok_logo_no_text_transparent_512.png|link=HYELEC MS8236|[[File:Nuvola Red.png|16px]] [[HYELEC MS8236]] (6000 counts, USB)
File:800px-Mastech m9803r device front.png|link=MASTECH M9803R|[[File:Nuvola Red.png|16px]] [[MASTECH M9803R]] (4000 counts, RS232)
File:Metrix mx53.png|link=Metrix MX53|[[File:Nuvola Red.png|16px]] [[Metrix MX53]] (50000 counts, RS232)
File:Peaktech 4380 mugshot.png|link=PeakTech 4380|[[File:Nuvola Red.png|16px]] [[PeakTech 4380]] (4000 counts, RS232)
File:Peaktech 4390 mugshot.png|link=PeakTech 4390|[[File:Nuvola Red.png|16px]] [[PeakTech 4390]] (6000 counts, USB)
File:Sigrok_logo_no_text_transparent_512.png|link=Protek 6500|[[File:Nuvola Red.png|16px]] [[Protek 6500]] (50000 counts, RS232)
File:Rigol DM3068 front.png|link=Rigol DM3068|[[File:Nuvola Red.png|16px]] [[Rigol DM3068]] (2200000 counts, LAN/USB/GPIB/RS232)
File:Tenma 72-1016.png|link=Tenma 72-1016|[[File:Nuvola Red.png|16px]] [[Tenma 72-1016]] (6000 counts, RS232/USB)
File:Uni-t-ut81b mugshot.png|link=UNI-T UT81B|[[File:Nuvola Red.png|16px]] [[UNI-T UT81B]] (6000 counts, USB)
File:Voltcraft 3850D front transp.png|link=Voltcraft M-3850D|[[File:Nuvola Red.png|16px]] [[Voltcraft M-3850D]] (4000 counts, RS232)
File:Voltcraft m3890dt usb.png|link=Voltcraft M-3890DT|[[File:Nuvola Red.png|16px]] [[Voltcraft M-3890DT]] (4000 counts, USB)
File:Voltcraft m4660a device front.png|link=Voltcraft M-4660A|[[File:Nuvola Red.png|16px]] [[Voltcraft M-4660A]] (20000 counts, RS232)
File:Voltcraft vc890 mugshot.png|link=Voltcraft VC-890|[[File:Nuvola Red.png|16px]] [[Voltcraft VC-890]] (60000 counts, USB/serial)
</gallery>

== LCR meters ==

<gallery widths="100Px" heights="100px">
File:Der ee de-5000 mugshot.png|link=DER EE DE-5000|[[File:Nuvola_OK.png|16px]] [[DER EE DE-5000]] (serial)
File:Sigrok_logo_no_text_transparent_512.png|link=MASTECH MS5308|[[File:Nuvola_OK.png|16px]] [[MASTECH MS5308]] (serial)
File:peaktech2165-front.png|link=Peaktech 2165|[[File:Nuvola_OK.png|16px]] [[Peaktech 2165]] (serial)
File:Peaktech 2170 mugshot.png|link=PeakTech 2170|[[File:Nuvola_OK.png|16px]] [[PeakTech 2170]] (serial)
File:uni_t_ut612_1.png|link=UNI-T UT612|[[File:Nuvola_OK.png|16px]] [[UNI-T UT612]] (USB/HID)
File:Voltcraft4080_2.png|link=Voltcraft 4080|[[File:Nuvola_OK.png|16px]] [[Voltcraft 4080]] (serial)
</gallery>

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery widths="100px" heights="100px">
File:Agilent U1732B.png|link=Agilent U1732B|[[File:Nuvola Red.png|16px]] [[Agilent U1732B]] (IR)
</gallery>

== Sound level meters ==

<gallery widths="100px" heights="100px">
File:CEM DT-8852.png|link=CEM DT-8852|[[File:Nuvola OK.png|16px]] [[CEM DT-8852]] (USB)
File:Colead SL-5868P.png|link=Colead SL-5868P|[[File:Nuvola OK.png|16px]] [[Colead SL-5868P]] (RS232)
File:Kecheng KC-330B.png|link=Kecheng KC-330B|[[File:Nuvola OK.png|16px]] [[Kecheng KC-330B]] (RS232)
File:PCE-322A.png|link=PCE PCE-322A|[[File:Nuvola OK.png|16px]] [[PCE PCE-322A]] (USB)
File:Tondaj sl-814.png|link=Tondaj SL-814|[[File:Nuvola OK.png|16px]] [[Tondaj SL-814]] (USB)
</gallery>

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery>
File:Pce_pce-222_front.png|link=PCE PCE-222|[[File:Nuvola Red.png|16px]] [[PCE PCE-222]] (also: light-/thermo-/hygrometer; RS232)
File:Voltcraft_dl_160s.png|link=Voltcraft DL-160S|[[File:Nuvola Red.png|16px]] [[Voltcraft DL-160S]] (USB)
File:Voltcraft_DL-161S.png|link=Voltcraft DL-161S|[[File:Nuvola Red.png|16px]] [[Voltcraft DL-161S]] (USB)
</gallery>

== Thermometers ==

<gallery widths="100px" heights="100px">
File:rs55ii.png|link=APPA 55II|[[File:Nuvola OK.png|16px]] [[APPA 55II]] (2xtemp, RS232)
File:EL-USB-2.png|link=Lascar Electronics EL-USB-2|[[File:Nuvola OK.png|16px]] [[Lascar Electronics EL-USB-2]] (1xtemp, 1xhum, USB)
File:Mic 98581.png|link=MIC 98581|[[File:Nuvola OK.png|16px]] [[MIC 98581]] (1xtemp, USB)
File:Mic 98583.png|link=MIC 98583|[[File:Nuvola OK.png|16px]] [[MIC 98583]] (1xtemp, 1xhum, USB)
File:Uni-t ut325 front.png|link=UNI-T UT325|[[File:Nuvola OK.png|16px]] [[UNI-T UT325]] (2xtemp, USB)
File:Voltcraft k204.png|link=Voltcraft K204|[[File:Nuvola OK.png|16px]] [[Voltcraft K204]] (4xtemp, RS232)
</gallery>

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery>
File:Elitech rc3.png|link=Elitech RC-3|[[File:Nuvola Red.png|16px]] [[Elitech RC-3]] (1xtemp, RS232)
File:Escort 19.png|link=Escort 19|[[File:Nuvola Red.png|16px]] [[Escort 19]] (1x temp, RS232)
File:MASTECH_MS6514_front.png|link=MASTECH_MS6514|[[File:Nuvola Orange.png|16px]] [[MASTECH_MS6514]] (2x temp, USB/serial)
File:Pax_instruments_t400.jpg|link=Pax Instruments T400|[[File:Nuvola Red.png|16px]] [[Pax Instruments T400]] (4xtemp, USB)
File:Pce_pce-222_front.png|link=PCE PCE-222|[[File:Nuvola Red.png|16px]] [[PCE PCE-222]] (1xtemp, RS232)
File:Rding temper front.png|link=RDing TEMPer|[[File:Nuvola Red.png|16px]] [[RDing TEMPer]] (1xtemp, USB)
File:Rding temper gold device front.png|link=RDing TEMPer Gold|[[File:Nuvola Red.png|16px]] [[RDing TEMPer Gold]] (1xtemp, USB)
File:Rding temper1 device front.png|link=RDing TEMPer1|[[File:Nuvola Red.png|16px]] [[RDing TEMPer1]] (1xtemp, USB)
File:Pcsensor_temper1k2.png|link=RDing TEMPer1K2|[[File:Nuvola Red.png|16px]] [[RDing TEMPer1K2]] (1xtemp, USB)
File:Voltcraft dl-120th.png|link=Voltcraft DL-120TH|[[File:Nuvola Red.png|16px]] [[Voltcraft DL-120TH]] (1xtemp, USB)
File:Voltcraft dl-140th.png|link=Voltcraft DL-140TH|[[File:Nuvola Red.png|16px]] [[Voltcraft DL-140TH]] (1xtemp, USB)
</gallery>

== Hygrometers ==

<gallery widths="100px" heights="100px">
File:EL-USB-2.png|link=Lascar Electronics EL-USB-2|[[File:Nuvola OK.png|16px]] [[Lascar Electronics EL-USB-2]] (temp/humidity, USB)
File:Mic 98583.png|link=MIC 98583|[[File:Nuvola OK.png|16px]] [[MIC 98583]] (temp/humidity, USB)
</gallery>

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery>
File:Pce_pce-222_front.png|link=PCE PCE-222|[[File:Nuvola Red.png|16px]] [[PCE PCE-222]] (also: light-/soundlevelmeter; RS232)
File:Silabs si7005usb dgl eb top.jpg|link=SiLabs Si7005USB-Dongle|[[File:Nuvola Red.png|16px]] [[SiLabs Si7005USB-Dongle]] (USB)
</gallery>

== Anemometers ==

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery widths="100px" heights="100px">
File:Mastech ms6252b.png|link=MASTECH MS6252B|[[File:Nuvola Red.png|16px]] [[MASTECH MS6252B]] (USB)
</gallery>

== Light meters ==

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery widths="100px" heights="100px">
File:Lutron YK-2005LX.png|link=Lutron YK-2005LX|[[File:Nuvola Red.png|16px]] [[Lutron YK-2005LX]] (RS232)
File:Pce_pce-222_front.png|link=PCE PCE-222|[[File:Nuvola Red.png|16px]] [[PCE PCE-222]] (RS232)
</gallery>

== Energy meters ==

<gallery widths="100px" heights="100px">
File:Actaris_a14c5_teleinfo.png|link=EDF Teleinfo|[[File:Nuvola OK.png|16px]] [[EDF Teleinfo]] (RS232)
File:Acme.png|link=BayLibre ACME|[[File:Nuvola OK.png|16px]] [[BayLibre ACME]] (I2C)
</gallery>

== DAQs ==

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery widths="100px" heights="100px">
File:Ni usb 6008.png|link=NI USB-6008|[[File:Nuvola Red.png|16px]] [[NI USB-6008]] (8/2 analog inputs/outputs, 12 digital I/Os)
</gallery>

== Dataloggers ==

<gallery widths="100px" heights="100px">
File:EL-USB-CO.png|link=Lascar Electronics EL-USB-CO|[[File:Nuvola OK.png|16px]] [[Lascar Electronics EL-USB-CO]] (carbon monoxide (CO) logger, USB)
File:Testo_435-4.png|link=Testo 435-4|[[File:Nuvola OK.png|16px]] [[Testo 435-4]] (USB)
</gallery>

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery>
File:Gsg_indoor_air_monitor.png|link=GSG Indoor Air Monitor|[[File:Nuvola Red.png|16px]] [[GSG Indoor Air Monitor]] (air quality monitor, USB)
File:Maul_studio_i.png|link=MAUL studio i|[[File:Nuvola Red.png|16px]] [[MAUL studio i]] (weighing scale, RS232)
File:Voltcraft co-20.png|link=Voltcraft CO-20|[[File:Nuvola Red.png|16px]] [[Voltcraft CO-20]] (air quality monitor, USB)
</gallery>

== Tachometers ==

<gallery widths="100px" heights="100px">
File:Uni-t ut372 mugshot.png|link=UNI-T UT372|[[File:Nuvola OK.png|16px]] [[UNI-T UT372]] (USB)
</gallery>

== Scales ==

<gallery widths="100px" heights="100px">
File:Kern ew-6200-2nm mugshot.png|link=KERN scale series|[[File:Nuvola OK.png|16px]] [[KERN scale series]] (RS232)
</gallery>

== Digital loads ==

<gallery widths="100px" heights="100px">
File:Arachnid Labs ReLoad Pro - Mugshot.png|link=Arachnid Labs Reload Pro|[[File:Nuvola OK.png|16px]] [[Arachnid Labs Reload Pro]] (USB)
File:Maynuo m9812 mugshot.png|link=Maynuo M9812|[[File:Nuvola OK.png|16px]] [[Maynuo M9812]]
File:Ztetech-ebd-usb%2B.png|link=ZKETECH_EBD-USB|[[File:Nuvola OK.png|16px]] [[ZKETECH EBD-USB]]
</gallery>

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery>
File:Atten ATZ9711.png|link=ATTEN ATZ9711|[[File:Nuvola Red.png|16px]] [[ATTEN ATZ9711]]
</gallery>

== Function generators ==

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery widths="100px" heights="100px">
File:BG7TBL small.png|link=BG7TBL|[[File:Nuvola Red.png|16px]] [[BG7TBL]] (138MHz-4.4GHz, PC-based, USB)
File:Hantek DDS-3X25 top.png|link=Hantek DDS-3X25|[[File:Nuvola Red.png|16px]] [[Hantek DDS-3X25]] (25MHz, PC-based, USB)
File:Hp_3325a_front.png|link=HO 3325A|[[File:Nuvola Red.png|16px]] [[HP 3325A]] (20MHz, GPIB)
File:Jds6600-mugshot.png|link=Joy-IT JDS6600|[[File:Nuvola Red.png|16px]] [[Joy-IT JDS6600]] (60MHz, USB RS232)
File:MHINSTEK UDB1305S persp.jpg|link=MHINSTEK UDB1xxxS|[[File:Nuvola Red.png|16px]] [[MHINSTEK UDB1xxxS]] (2/5/8MHz, Serial)
File:MHINSTEK MHS-5200A persp.jpg|link=MHINSTEK MHS-5200A|[[File:Nuvola Red.png|16px]] [[MHINSTEK MHS-5200A]] (6/12/20/25MHz, USB)
File:Siglent sdg1010 device front 8116.png|link=Siglent SDG1010|[[File:Nuvola Red.png|16px]] [[Siglent SDG1010]] (10MHz, USB)
File:Sigrok_logo_no_text_transparent_512.png|link=Velleman PCG10|[[File:Nuvola Red.png|16px]] [[Velleman PCG10]] (1MHz, PC-based, LPT)
</gallery>

== Frequency counters ==

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery widths="100px" heights="100px">
File:Hantek DDS-3X25 top.png|link=Hantek DDS-3X25|[[File:Nuvola Red.png|16px]] [[Hantek DDS-3X25]] (50MHz, PC-based, USB)
File:HP 5350B.png|link=HP 5350B|[[File:Nuvola Red.png|16px]] [[HP 5350B]] (10Hz-20GHz, GPIB)
</gallery>

== RF receivers ==

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery widths="100px" heights="100px">
File:Per vices noctar.png|link=Per Vices Noctar|[[File:Nuvola Red.png|16px]] [[Per Vices Noctar]] (100kHz-4GHz, IQ modulator/demodulator, PCIe)
</gallery>

== Spectrum analyzers ==

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery widths="100px" heights="100px">
File:Sigrok_logo_no_text_transparent_512.png|link=Siglent SSA3000X series|[[File:Nuvola Red.png|16px]] [[Siglent SSA3000X series]] (9kHz-2.1GHz, USB, Ethernet)
</gallery>

== Power supplies ==

<gallery widths="100px" heights="100px">
File:Atten PPS3203T-3S.png|link=Atten PPS3203T-3S|[[File:Nuvola OK.png|16px]] [[Atten PPS3203T-3S]] (3ch, 2x 0-32V, 1x 0-6V at 0-3A, USB&RS232)
File:Chroma_61604_front.png|link=Chroma 61604|[[File:Nuvola OK.png|16px]] [[Chroma 61604]] (1ch, 0-300V, 0-16A, 2kVA)
File:Conrad_digi_35_cpu_logo.png|link=Conrad DIGI 35 CPU|[[File:Nuvola OK.png|16px]] [[Conrad DIGI 35 CPU]] (1ch, 0-35V / 0-2.55A, RS232)
File:Agilent-66312a-mugshot.png|link=HP 66312A|[[File:Nuvola OK.png|16px]] [[HP 66312A]] (1ch, 0-20V / 0-2A, GPIB&RS232)
File:HP-6632B_mugshot.png|link=HP 6632B|[[File:Nuvola OK.png|16px]] [[HP 6632B]] (1ch, 0-20V / 0-5A, GPIB&RS232)
File:Sigrok logo no text transparent 512.png|link=GW Instek GPD series|[[File:Nuvola OK.png|16px]] [[GW Instek GPD series]] (2/3/4ch, 0-30V / 0-3A, USB/serial)
File:Velleman ps3005d mugshot.png|link=Korad KAxxxxP series|[[File:Nuvola OK.png|16px]] [[Korad KAxxxxP series]] (1ch, 0-30V / 0-5A, USB&RS232)
File:Manson hcs3202.png|link=Manson HCS-3xxx series|[[File:Nuvola OK.png|16px]] [[Manson HCS-3xxx series]] (1ch, 1-36V / 0-10A, USB)
File:Motech_LPS-301_logo.png|link=Motech LPS-301|[[File:Nuvola OK.png|16px]] [[Motech LPS-301]] (1ch, 1-32V / 0-2A, RS232)
File:Philips PM2813.png|link=Philips PM2800 series|[[File:Nuvola OK.png|16px]] Fluke/Philips PM2800 series
File:Rigol DP832.png|link=Rigol DP800 series|[[File:Nuvola OK.png|16px]] [[Rigol DP800 series]]
File:rs_hmc8043_mugshot.png|link=Rohde&Schwarz HMC 8043|[[File:Nuvola OK.png|16px]] [[Rohde&Schwarz HMC 8043]] (3ch, 0-32V / 0-3A, USB&LXI)
File:Rdtech-dps.png|link=RDTech DPS series|[[File:Nuvola OK.png|16px]] [[RDTech DPS series]] (1ch, various, USB/BT)
</gallery>

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery>
File:Sigrok logo no text transparent 512.png|link=Voltcraft 18220|[[File:Nuvola Red.png|16px]] [[Voltcraft 18220]] (1ch, 0-40V/0-5A, RS232)
</gallery>

== GPIB interfaces ==

'''Work in progress [[File:Nuvola Orange.png|16px]] / planned [[File:Nuvola Red.png|16px]]:'''

<gallery widths="100px" heights="100px">
File:Sigrok logo no text transparent 512.png|link=AR488|[[File:Nuvola Red.png|16px]] [[AR488]] (Arduino based, USB/RS232)
File:Beiming_s82357.png|link=Beiming S82357|[[File:Nuvola Red.png|16px]] [[Beiming S82357]] (hardware-based, USB)
File:ICS 488-USB.png|link=ICS 488-USB|[[File:Nuvola Red.png|16px]] [[ICS 488-USB]] (hardware-based, USB)
File:GPIB-USB 82357B clone.png|link=GPIB-USB 82357B clone|[[File:Nuvola Red.png|16px]] [[GPIB-USB 82357B clone]] (hardware-based, USB)
File:NI GPIB-ENET.png|link=National Instruments GPIB-ENET|[[File:Nuvola Red.png|16px]] [[National Instruments GPIB-ENET]] (hardware-based, Ethernet)
File:NI GPIB-USB-HS.png|link=National Instruments GPIB-USB-HS|[[File:Nuvola Red.png|16px]] [[National Instruments GPIB-USB-HS]] (hardware-based, USB)
File:Prologix-usb.png|link=Prologix GPIB-USB|[[File:Nuvola Red.png|16px]] [[Prologix GPIB-USB]] (firmware-based, USB)
File:GalvantGPIBUSBrev4.JPG|link=Galvant GPIBUSB|[[File:Nuvola Red.png|16px]] [[Galvant GPIBUSB]] (firmware-based, USB, OSHW)
</gallery>

== Potential other candidates ==

If you own any other logic analyzers, oscilloscopes, multimeters, dataloggers, ... and want to add support for them in sigrok (or donate/lend devices to developers), please let us know. We're always happy to add more hardware support! Join the [https://lists.sourceforge.net/lists/listinfo/sigrok-devel mailing list] or ask on [irc://chat.freenode.net/sigrok IRC #sigrok] if you want to help out.

__FORCETOC__

CoLA

2019-12-10T15:02:39Z

Danny W:

File:CoLA2.PNG

2019-12-10T15:01:00Z

Danny W:

== Licensing ==
{{CC-BY-SA-3.0}}

CoLA

2019-12-10T15:00:27Z

Danny W:

CoLA

2019-12-10T14:26:02Z

Danny W:

CoLA

2019-12-10T14:24:13Z

Danny W:

CoLA

2019-12-10T14:06:36Z

Danny W:

CoLA

2019-12-10T13:33:32Z

Danny W:

File:IMG 20191206 105430.jpg

2019-12-10T13:32:45Z

Danny W:

== Licensing ==
{{CC-BY-SA-3.0}}

CoLA

2019-12-10T13:29:42Z

Danny W: An advanced logic analyzer with professional specs you can build yourself.

{{Infobox logic analyzer
| image = [[File:CoLA.png|180px]]
| name = CoLA - Compact Logic Analyzer
| status = planned
| source_code_dir = -
| channels = 96/48/24
| samplerate = 25MHz/50MHz/100MHz
| samplerate_state = ?
| triggers = 32 hardware, 96 bit masked pattern
| voltages = 1.65V - 5.5V continuously
| threshold = ?
| memory = 262144 bytes
| compression = RLE, frame omission
| website = -
}}