sigrok - User contributions [en]

Digilent Analog Discovery/Info

2016-05-08T05:46:52Z

Cyrozap: /* FPGA I/O map */ Added LED pin

== lsusb ==


$ '''lsusb -vvv'''
Bus 001 Device 003: ID '''0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC'''
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
idVendor 0x0403 '''Future Technology Devices International, Ltd'''
idProduct 0x6014 '''FT232H Single HS USB-UART/FIFO IC'''
bcdDevice 9.00
iManufacturer 1 '''Digilent'''
iProduct 2 '''Digilent USB Device'''
iSerial 3 '''210244449192'''
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 32
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0x80
(Bus Powered)
MaxPower 500mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 255 Vendor Specific Class
bInterfaceSubClass 255 Vendor Specific Subclass
bInterfaceProtocol 255 Vendor Specific Protocol
iInterface 2 Digilent USB Device
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 EP 2 OUT
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Device Qualifier (for other device speed):
bLength 10
bDescriptorType 6
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
bNumConfigurations 1
Device Status: 0x0000
(Bus Powered)


== FPGA I/O map ==

=== Miscellaneous ===

* Red LED on N5, active high

=== Clocks ===

* 12 MHz clock on P7

==== Clock Generator ====

{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| CS_CLKD_N || M14
|-
| SCLK_CLKD || L14
|-
| SDIO_CLKD || L13
|-
| LD_CLKD || M13
|}

=== Digital I/O ===

{| class="wikitable" style="text-align:center;"
! External pin name || FPGA pad
|-
| T1 || D2
|-
| T2 || D1
|-
| 0 || E2
|-
| 1 || F2
|-
| 2 || G2
|-
| 3 || H2
|-
| 4 || J2
|-
| 5 || K2
|-
| 6 || L2
|-
| 7 || M2
|-
| 8 || E1
|-
| 9 || F1
|-
| 10 || G1
|-
| 11 || H1
|-
| 12 || J1
|-
| 13 || K1
|-
| 14 || L1
|-
| 15 || M1
|}

=== Scope ===

==== ADC ====
{| class="wikitable" style="text-align:center;"
! ADC pin || FPGA pad
|-
| D13B || K14
|-
| D12B || J13
|-
| D11B || J14
|-
| D10B || H13
|-
| D9B || H14
|-
| D8B || G13
|-
| D7B || G14
|-
| D6B || F13
|-
| D5B || F14
|-
| D4B || E13
|-
| D3B || E14
|-
| D2B || D13
|-
| D1B || D14
|-
| D0B || C13
|-
| DCOB || H12
|-
| SDIO || B12
|-
| SCLK || A12
|-
| CSB || B11
|-
| PDWN || A11
|}

==== Gain Selection ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| EN_HG_SC1 || J4
|-
| EN_LG_SC1 || F3
|-
| EN_HG_SC2 || C1
|-
| EN_LG_SC2 || B1
|}

==== Voltage Reference and Offset ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SYNC_SC_OFF_N || F11
|-
| SCLK_OFF || F12
|-
| SDIN_OFF || C12
|}

=== Arbitrary Waveform Generator ===

==== DAC ====

{| class="wikitable" style="text-align:center;"
! DAC pin || FPGA pad
|-
| DB13 || B8
|-
| DB12 || A7
|-
| DB11 || B7
|-
| DB10 || A6
|-
| DB9 || B6
|-
| DB8 || A5
|-
| DB7 || B5
|-
| DB6 || A4
|-
| DB5 || A3
|-
| DB4 || A8
|-
| DB3 || B9
|-
| DB2 || A9
|-
| DB1 || B10
|-
| DB0 || A10
|-
| DCLKIO || C8
|-
| SCLK || B4
|-
| SDIO || B3
|-
| CSN || A2
|-
| RESET || D8
|}

==== Gain Setting ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SET_FS_AWG1 || D11
|-
| SET_FS_AWG2 || C11
|}

==== Voltage Reference and Offset ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SCL_AWG_OFF || J3
|-
| SDA_AWG_OFF || N3
|}

=== Power Supplies and Control ===

==== USB Power Control ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SCL_PWR || J11
|-
| SDA_PWR || K13
|-
| EN_AVCC || L4
|}

==== User Supplies Control ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SCL_PWR_TEMP || N4
|-
| SDA_PWR_TEMP || M4
|-
| EN_PWR_USR || P2
|}

==== User Voltage Supplies ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| EN_5V0_USR || D4
|-
| EN_-5V0_USR || D3
|}

==== Internal Digital Supply ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| EN_DVCC1V8 || J12
|}

Digilent Analog Discovery/Info

2016-04-10T21:37:58Z

Cyrozap: /* Power Supplies and Control */ Added section for the Internal Digital Supply

== lsusb ==


$ '''lsusb -vvv'''
Bus 001 Device 003: ID '''0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC'''
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
idVendor 0x0403 '''Future Technology Devices International, Ltd'''
idProduct 0x6014 '''FT232H Single HS USB-UART/FIFO IC'''
bcdDevice 9.00
iManufacturer 1 '''Digilent'''
iProduct 2 '''Digilent USB Device'''
iSerial 3 '''210244449192'''
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 32
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0x80
(Bus Powered)
MaxPower 500mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 255 Vendor Specific Class
bInterfaceSubClass 255 Vendor Specific Subclass
bInterfaceProtocol 255 Vendor Specific Protocol
iInterface 2 Digilent USB Device
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 EP 2 OUT
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Device Qualifier (for other device speed):
bLength 10
bDescriptorType 6
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
bNumConfigurations 1
Device Status: 0x0000
(Bus Powered)


== FPGA I/O map ==

=== Clocks ===

* 12 MHz clock on P7

==== Clock Generator ====

{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| CS_CLKD_N || M14
|-
| SCLK_CLKD || L14
|-
| SDIO_CLKD || L13
|-
| LD_CLKD || M13
|}

=== Digital I/O ===

{| class="wikitable" style="text-align:center;"
! External pin name || FPGA pad
|-
| T1 || D2
|-
| T2 || D1
|-
| 0 || E2
|-
| 1 || F2
|-
| 2 || G2
|-
| 3 || H2
|-
| 4 || J2
|-
| 5 || K2
|-
| 6 || L2
|-
| 7 || M2
|-
| 8 || E1
|-
| 9 || F1
|-
| 10 || G1
|-
| 11 || H1
|-
| 12 || J1
|-
| 13 || K1
|-
| 14 || L1
|-
| 15 || M1
|}

=== Scope ===

==== ADC ====
{| class="wikitable" style="text-align:center;"
! ADC pin || FPGA pad
|-
| D13B || K14
|-
| D12B || J13
|-
| D11B || J14
|-
| D10B || H13
|-
| D9B || H14
|-
| D8B || G13
|-
| D7B || G14
|-
| D6B || F13
|-
| D5B || F14
|-
| D4B || E13
|-
| D3B || E14
|-
| D2B || D13
|-
| D1B || D14
|-
| D0B || C13
|-
| DCOB || H12
|-
| SDIO || B12
|-
| SCLK || A12
|-
| CSB || B11
|-
| PDWN || A11
|}

==== Gain Selection ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| EN_HG_SC1 || J4
|-
| EN_LG_SC1 || F3
|-
| EN_HG_SC2 || C1
|-
| EN_LG_SC2 || B1
|}

==== Voltage Reference and Offset ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SYNC_SC_OFF_N || F11
|-
| SCLK_OFF || F12
|-
| SDIN_OFF || C12
|}

=== Arbitrary Waveform Generator ===

==== DAC ====

{| class="wikitable" style="text-align:center;"
! DAC pin || FPGA pad
|-
| DB13 || B8
|-
| DB12 || A7
|-
| DB11 || B7
|-
| DB10 || A6
|-
| DB9 || B6
|-
| DB8 || A5
|-
| DB7 || B5
|-
| DB6 || A4
|-
| DB5 || A3
|-
| DB4 || A8
|-
| DB3 || B9
|-
| DB2 || A9
|-
| DB1 || B10
|-
| DB0 || A10
|-
| DCLKIO || C8
|-
| SCLK || B4
|-
| SDIO || B3
|-
| CSN || A2
|-
| RESET || D8
|}

==== Gain Setting ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SET_FS_AWG1 || D11
|-
| SET_FS_AWG2 || C11
|}

==== Voltage Reference and Offset ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SCL_AWG_OFF || J3
|-
| SDA_AWG_OFF || N3
|}

=== Power Supplies and Control ===

==== USB Power Control ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SCL_PWR || J11
|-
| SDA_PWR || K13
|-
| EN_AVCC || L4
|}

==== User Supplies Control ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SCL_PWR_TEMP || N4
|-
| SDA_PWR_TEMP || M4
|-
| EN_PWR_USR || P2
|}

==== User Voltage Supplies ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| EN_5V0_USR || D4
|-
| EN_-5V0_USR || D3
|}

==== Internal Digital Supply ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| EN_DVCC1V8 || J12
|}

Digilent Analog Discovery/Info

2016-04-10T21:33:50Z

Cyrozap: /* Clocks */ Added clock generator pins

== lsusb ==


$ '''lsusb -vvv'''
Bus 001 Device 003: ID '''0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC'''
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
idVendor 0x0403 '''Future Technology Devices International, Ltd'''
idProduct 0x6014 '''FT232H Single HS USB-UART/FIFO IC'''
bcdDevice 9.00
iManufacturer 1 '''Digilent'''
iProduct 2 '''Digilent USB Device'''
iSerial 3 '''210244449192'''
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 32
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0x80
(Bus Powered)
MaxPower 500mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 255 Vendor Specific Class
bInterfaceSubClass 255 Vendor Specific Subclass
bInterfaceProtocol 255 Vendor Specific Protocol
iInterface 2 Digilent USB Device
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 EP 2 OUT
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Device Qualifier (for other device speed):
bLength 10
bDescriptorType 6
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
bNumConfigurations 1
Device Status: 0x0000
(Bus Powered)


== FPGA I/O map ==

=== Clocks ===

* 12 MHz clock on P7

==== Clock Generator ====

{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| CS_CLKD_N || M14
|-
| SCLK_CLKD || L14
|-
| SDIO_CLKD || L13
|-
| LD_CLKD || M13
|}

=== Digital I/O ===

{| class="wikitable" style="text-align:center;"
! External pin name || FPGA pad
|-
| T1 || D2
|-
| T2 || D1
|-
| 0 || E2
|-
| 1 || F2
|-
| 2 || G2
|-
| 3 || H2
|-
| 4 || J2
|-
| 5 || K2
|-
| 6 || L2
|-
| 7 || M2
|-
| 8 || E1
|-
| 9 || F1
|-
| 10 || G1
|-
| 11 || H1
|-
| 12 || J1
|-
| 13 || K1
|-
| 14 || L1
|-
| 15 || M1
|}

=== Scope ===

==== ADC ====
{| class="wikitable" style="text-align:center;"
! ADC pin || FPGA pad
|-
| D13B || K14
|-
| D12B || J13
|-
| D11B || J14
|-
| D10B || H13
|-
| D9B || H14
|-
| D8B || G13
|-
| D7B || G14
|-
| D6B || F13
|-
| D5B || F14
|-
| D4B || E13
|-
| D3B || E14
|-
| D2B || D13
|-
| D1B || D14
|-
| D0B || C13
|-
| DCOB || H12
|-
| SDIO || B12
|-
| SCLK || A12
|-
| CSB || B11
|-
| PDWN || A11
|}

==== Gain Selection ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| EN_HG_SC1 || J4
|-
| EN_LG_SC1 || F3
|-
| EN_HG_SC2 || C1
|-
| EN_LG_SC2 || B1
|}

==== Voltage Reference and Offset ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SYNC_SC_OFF_N || F11
|-
| SCLK_OFF || F12
|-
| SDIN_OFF || C12
|}

=== Arbitrary Waveform Generator ===

==== DAC ====

{| class="wikitable" style="text-align:center;"
! DAC pin || FPGA pad
|-
| DB13 || B8
|-
| DB12 || A7
|-
| DB11 || B7
|-
| DB10 || A6
|-
| DB9 || B6
|-
| DB8 || A5
|-
| DB7 || B5
|-
| DB6 || A4
|-
| DB5 || A3
|-
| DB4 || A8
|-
| DB3 || B9
|-
| DB2 || A9
|-
| DB1 || B10
|-
| DB0 || A10
|-
| DCLKIO || C8
|-
| SCLK || B4
|-
| SDIO || B3
|-
| CSN || A2
|-
| RESET || D8
|}

==== Gain Setting ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SET_FS_AWG1 || D11
|-
| SET_FS_AWG2 || C11
|}

==== Voltage Reference and Offset ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SCL_AWG_OFF || J3
|-
| SDA_AWG_OFF || N3
|}

=== Power Supplies and Control ===

==== USB Power Control ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SCL_PWR || J11
|-
| SDA_PWR || K13
|-
| EN_AVCC || L4
|}

==== User Supplies Control ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SCL_PWR_TEMP || N4
|-
| SDA_PWR_TEMP || M4
|-
| EN_PWR_USR || P2
|}

==== User Voltage Supplies ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| EN_5V0_USR || D4
|-
| EN_-5V0_USR || D3
|}

Digilent Analog Discovery/Info

2016-04-10T21:22:15Z

Cyrozap: /* FPGA I/O map */ Added a section for Power Supplies and Control

== lsusb ==


$ '''lsusb -vvv'''
Bus 001 Device 003: ID '''0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC'''
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
idVendor 0x0403 '''Future Technology Devices International, Ltd'''
idProduct 0x6014 '''FT232H Single HS USB-UART/FIFO IC'''
bcdDevice 9.00
iManufacturer 1 '''Digilent'''
iProduct 2 '''Digilent USB Device'''
iSerial 3 '''210244449192'''
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 32
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0x80
(Bus Powered)
MaxPower 500mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 255 Vendor Specific Class
bInterfaceSubClass 255 Vendor Specific Subclass
bInterfaceProtocol 255 Vendor Specific Protocol
iInterface 2 Digilent USB Device
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 EP 2 OUT
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Device Qualifier (for other device speed):
bLength 10
bDescriptorType 6
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
bNumConfigurations 1
Device Status: 0x0000
(Bus Powered)


== FPGA I/O map ==

=== Clocks ===

* 12 MHz clock on P7

=== Digital I/O ===

{| class="wikitable" style="text-align:center;"
! External pin name || FPGA pad
|-
| T1 || D2
|-
| T2 || D1
|-
| 0 || E2
|-
| 1 || F2
|-
| 2 || G2
|-
| 3 || H2
|-
| 4 || J2
|-
| 5 || K2
|-
| 6 || L2
|-
| 7 || M2
|-
| 8 || E1
|-
| 9 || F1
|-
| 10 || G1
|-
| 11 || H1
|-
| 12 || J1
|-
| 13 || K1
|-
| 14 || L1
|-
| 15 || M1
|}

=== Scope ===

==== ADC ====
{| class="wikitable" style="text-align:center;"
! ADC pin || FPGA pad
|-
| D13B || K14
|-
| D12B || J13
|-
| D11B || J14
|-
| D10B || H13
|-
| D9B || H14
|-
| D8B || G13
|-
| D7B || G14
|-
| D6B || F13
|-
| D5B || F14
|-
| D4B || E13
|-
| D3B || E14
|-
| D2B || D13
|-
| D1B || D14
|-
| D0B || C13
|-
| DCOB || H12
|-
| SDIO || B12
|-
| SCLK || A12
|-
| CSB || B11
|-
| PDWN || A11
|}

==== Gain Selection ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| EN_HG_SC1 || J4
|-
| EN_LG_SC1 || F3
|-
| EN_HG_SC2 || C1
|-
| EN_LG_SC2 || B1
|}

==== Voltage Reference and Offset ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SYNC_SC_OFF_N || F11
|-
| SCLK_OFF || F12
|-
| SDIN_OFF || C12
|}

=== Arbitrary Waveform Generator ===

==== DAC ====

{| class="wikitable" style="text-align:center;"
! DAC pin || FPGA pad
|-
| DB13 || B8
|-
| DB12 || A7
|-
| DB11 || B7
|-
| DB10 || A6
|-
| DB9 || B6
|-
| DB8 || A5
|-
| DB7 || B5
|-
| DB6 || A4
|-
| DB5 || A3
|-
| DB4 || A8
|-
| DB3 || B9
|-
| DB2 || A9
|-
| DB1 || B10
|-
| DB0 || A10
|-
| DCLKIO || C8
|-
| SCLK || B4
|-
| SDIO || B3
|-
| CSN || A2
|-
| RESET || D8
|}

==== Gain Setting ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SET_FS_AWG1 || D11
|-
| SET_FS_AWG2 || C11
|}

==== Voltage Reference and Offset ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SCL_AWG_OFF || J3
|-
| SDA_AWG_OFF || N3
|}

=== Power Supplies and Control ===

==== USB Power Control ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SCL_PWR || J11
|-
| SDA_PWR || K13
|-
| EN_AVCC || L4
|}

==== User Supplies Control ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SCL_PWR_TEMP || N4
|-
| SDA_PWR_TEMP || M4
|-
| EN_PWR_USR || P2
|}

==== User Voltage Supplies ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| EN_5V0_USR || D4
|-
| EN_-5V0_USR || D3
|}

Digilent Analog Discovery/Info

2016-04-10T20:36:44Z

Cyrozap: /* FPGA I/O map */ Moved DAC information to AWG section and added Gain Setting and Voltage Reference and Offset subsections

== lsusb ==


$ '''lsusb -vvv'''
Bus 001 Device 003: ID '''0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC'''
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
idVendor 0x0403 '''Future Technology Devices International, Ltd'''
idProduct 0x6014 '''FT232H Single HS USB-UART/FIFO IC'''
bcdDevice 9.00
iManufacturer 1 '''Digilent'''
iProduct 2 '''Digilent USB Device'''
iSerial 3 '''210244449192'''
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 32
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0x80
(Bus Powered)
MaxPower 500mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 255 Vendor Specific Class
bInterfaceSubClass 255 Vendor Specific Subclass
bInterfaceProtocol 255 Vendor Specific Protocol
iInterface 2 Digilent USB Device
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 EP 2 OUT
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Device Qualifier (for other device speed):
bLength 10
bDescriptorType 6
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
bNumConfigurations 1
Device Status: 0x0000
(Bus Powered)


== FPGA I/O map ==

=== Clocks ===

* 12 MHz clock on P7

=== Digital I/O ===

{| class="wikitable" style="text-align:center;"
! External pin name || FPGA pad
|-
| T1 || D2
|-
| T2 || D1
|-
| 0 || E2
|-
| 1 || F2
|-
| 2 || G2
|-
| 3 || H2
|-
| 4 || J2
|-
| 5 || K2
|-
| 6 || L2
|-
| 7 || M2
|-
| 8 || E1
|-
| 9 || F1
|-
| 10 || G1
|-
| 11 || H1
|-
| 12 || J1
|-
| 13 || K1
|-
| 14 || L1
|-
| 15 || M1
|}

=== Scope ===

==== ADC ====
{| class="wikitable" style="text-align:center;"
! ADC pin || FPGA pad
|-
| D13B || K14
|-
| D12B || J13
|-
| D11B || J14
|-
| D10B || H13
|-
| D9B || H14
|-
| D8B || G13
|-
| D7B || G14
|-
| D6B || F13
|-
| D5B || F14
|-
| D4B || E13
|-
| D3B || E14
|-
| D2B || D13
|-
| D1B || D14
|-
| D0B || C13
|-
| DCOB || H12
|-
| SDIO || B12
|-
| SCLK || A12
|-
| CSB || B11
|-
| PDWN || A11
|}

==== Gain Selection ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| EN_HG_SC1 || J4
|-
| EN_LG_SC1 || F3
|-
| EN_HG_SC2 || C1
|-
| EN_LG_SC2 || B1
|}

==== Voltage Reference and Offset ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SYNC_SC_OFF_N || F11
|-
| SCLK_OFF || F12
|-
| SDIN_OFF || C12
|}

=== Arbitrary Waveform Generator ===

==== DAC ====

{| class="wikitable" style="text-align:center;"
! DAC pin || FPGA pad
|-
| DB13 || B8
|-
| DB12 || A7
|-
| DB11 || B7
|-
| DB10 || A6
|-
| DB9 || B6
|-
| DB8 || A5
|-
| DB7 || B5
|-
| DB6 || A4
|-
| DB5 || A3
|-
| DB4 || A8
|-
| DB3 || B9
|-
| DB2 || A9
|-
| DB1 || B10
|-
| DB0 || A10
|-
| DCLKIO || C8
|-
| SCLK || B4
|-
| SDIO || B3
|-
| CSN || A2
|-
| RESET || D8
|}

==== Gain Setting ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SET_FS_AWG1 || D11
|-
| SET_FS_AWG2 || C11
|}

==== Voltage Reference and Offset ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SCL_AWG_OFF || J3
|-
| SDA_AWG_OFF || N3
|}

Digilent Analog Discovery/Info

2016-04-10T20:19:25Z

Cyrozap: /* FPGA I/O map */ Grouped all the scope-related pins together

== lsusb ==


$ '''lsusb -vvv'''
Bus 001 Device 003: ID '''0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC'''
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
idVendor 0x0403 '''Future Technology Devices International, Ltd'''
idProduct 0x6014 '''FT232H Single HS USB-UART/FIFO IC'''
bcdDevice 9.00
iManufacturer 1 '''Digilent'''
iProduct 2 '''Digilent USB Device'''
iSerial 3 '''210244449192'''
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 32
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0x80
(Bus Powered)
MaxPower 500mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 255 Vendor Specific Class
bInterfaceSubClass 255 Vendor Specific Subclass
bInterfaceProtocol 255 Vendor Specific Protocol
iInterface 2 Digilent USB Device
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 EP 2 OUT
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Device Qualifier (for other device speed):
bLength 10
bDescriptorType 6
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
bNumConfigurations 1
Device Status: 0x0000
(Bus Powered)


== FPGA I/O map ==

=== Clocks ===

* 12 MHz clock on P7

=== Digital I/O ===

{| class="wikitable" style="text-align:center;"
! External pin name || FPGA pad
|-
| T1 || D2
|-
| T2 || D1
|-
| 0 || E2
|-
| 1 || F2
|-
| 2 || G2
|-
| 3 || H2
|-
| 4 || J2
|-
| 5 || K2
|-
| 6 || L2
|-
| 7 || M2
|-
| 8 || E1
|-
| 9 || F1
|-
| 10 || G1
|-
| 11 || H1
|-
| 12 || J1
|-
| 13 || K1
|-
| 14 || L1
|-
| 15 || M1
|}

=== DAC ===

{| class="wikitable" style="text-align:center;"
! DAC pin || FPGA pad
|-
| DB13 || B8
|-
| DB12 || A7
|-
| DB11 || B7
|-
| DB10 || A6
|-
| DB9 || B6
|-
| DB8 || A5
|-
| DB7 || B5
|-
| DB6 || A4
|-
| DB5 || A3
|-
| DB4 || A8
|-
| DB3 || B9
|-
| DB2 || A9
|-
| DB1 || B10
|-
| DB0 || A10
|-
| DCLKIO || C8
|-
| SCLK || B4
|-
| SDIO || B3
|-
| CSN || A2
|-
| RESET || D8
|}

=== Scope ===

==== ADC ====
{| class="wikitable" style="text-align:center;"
! ADC pin || FPGA pad
|-
| D13B || K14
|-
| D12B || J13
|-
| D11B || J14
|-
| D10B || H13
|-
| D9B || H14
|-
| D8B || G13
|-
| D7B || G14
|-
| D6B || F13
|-
| D5B || F14
|-
| D4B || E13
|-
| D3B || E14
|-
| D2B || D13
|-
| D1B || D14
|-
| D0B || C13
|-
| DCOB || H12
|-
| SDIO || B12
|-
| SCLK || A12
|-
| CSB || B11
|-
| PDWN || A11
|}

==== Gain Selection ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| EN_HG_SC1 || J4
|-
| EN_LG_SC1 || F3
|-
| EN_HG_SC2 || C1
|-
| EN_LG_SC2 || B1
|}

==== Voltage Reference and Offset ====
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SYNC_SC_OFF_N || F11
|-
| SCLK_OFF || F12
|-
| SDIN_OFF || C12
|}

Digilent Analog Discovery/Info

2016-04-10T03:35:12Z

Cyrozap: /* FPGA I/O map */ Added Scope Reference and Offset section

== lsusb ==


$ '''lsusb -vvv'''
Bus 001 Device 003: ID '''0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC'''
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
idVendor 0x0403 '''Future Technology Devices International, Ltd'''
idProduct 0x6014 '''FT232H Single HS USB-UART/FIFO IC'''
bcdDevice 9.00
iManufacturer 1 '''Digilent'''
iProduct 2 '''Digilent USB Device'''
iSerial 3 '''210244449192'''
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 32
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0x80
(Bus Powered)
MaxPower 500mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 255 Vendor Specific Class
bInterfaceSubClass 255 Vendor Specific Subclass
bInterfaceProtocol 255 Vendor Specific Protocol
iInterface 2 Digilent USB Device
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 EP 2 OUT
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Device Qualifier (for other device speed):
bLength 10
bDescriptorType 6
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
bNumConfigurations 1
Device Status: 0x0000
(Bus Powered)


== FPGA I/O map ==

=== Clocks ===

* 12 MHz clock on P7

=== Digital I/O ===

{| class="wikitable" style="text-align:center;"
! External pin name || FPGA pad
|-
| T1 || D2
|-
| T2 || D1
|-
| 0 || E2
|-
| 1 || F2
|-
| 2 || G2
|-
| 3 || H2
|-
| 4 || J2
|-
| 5 || K2
|-
| 6 || L2
|-
| 7 || M2
|-
| 8 || E1
|-
| 9 || F1
|-
| 10 || G1
|-
| 11 || H1
|-
| 12 || J1
|-
| 13 || K1
|-
| 14 || L1
|-
| 15 || M1
|}

=== DAC ===

{| class="wikitable" style="text-align:center;"
! DAC pin || FPGA pad
|-
| DB13 || B8
|-
| DB12 || A7
|-
| DB11 || B7
|-
| DB10 || A6
|-
| DB9 || B6
|-
| DB8 || A5
|-
| DB7 || B5
|-
| DB6 || A4
|-
| DB5 || A3
|-
| DB4 || A8
|-
| DB3 || B9
|-
| DB2 || A9
|-
| DB1 || B10
|-
| DB0 || A10
|-
| DCLKIO || C8
|-
| SCLK || B4
|-
| SDIO || B3
|-
| CSN || A2
|-
| RESET || D8
|}

=== ADC ===
{| class="wikitable" style="text-align:center;"
! ADC pin || FPGA pad
|-
| D13B || K14
|-
| D12B || J13
|-
| D11B || J14
|-
| D10B || H13
|-
| D9B || H14
|-
| D8B || G13
|-
| D7B || G14
|-
| D6B || F13
|-
| D5B || F14
|-
| D4B || E13
|-
| D3B || E14
|-
| D2B || D13
|-
| D1B || D14
|-
| D0B || C13
|-
| DCOB || H12
|-
| SDIO || B12
|-
| SCLK || A12
|-
| CSB || B11
|-
| PDWN || A11
|}

=== Scope Gain Selection ===
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| EN_HG_SC1 || J4
|-
| EN_LG_SC1 || F3
|-
| EN_HG_SC2 || C1
|-
| EN_LG_SC2 || B1
|}

=== Scope Reference and Offset ===
{| class="wikitable" style="text-align:center;"
! Signal || FPGA pad
|-
| SYNC_SC_OFF_N || F11
|-
| SCLK_OFF || F12
|-
| SDIN_OFF || C12
|}

Digilent Analog Discovery/Info

2016-04-10T03:23:48Z

Cyrozap: /* FPGA I/O map */ Added Scope Gain Selection section

Digilent Analog Discovery/Info

2016-04-02T06:03:28Z

Cyrozap: /* ADC */ Added PDWN pin

Digilent Analog Discovery/Info

2016-04-02T06:02:21Z

Cyrozap: /* DAC */ Added RESET pin

Digilent Analog Discovery/Info

2016-04-02T06:00:27Z

Cyrozap: /* FPGA I/O map */ Added DAC and ADC I2C pins

Digilent Analog Discovery/Info

2016-04-01T01:00:16Z

Cyrozap: /* FPGA I/O map */ Added initial ADC pin map

Digilent Analog Discovery/Info

2016-03-31T19:09:49Z

Cyrozap: /* DAC */ Updated pin map

Digilent Analog Discovery

2016-03-30T20:32:15Z

Cyrozap: Added reference to FPGA I/O listing

[[File:Digilent_analog_discovery.png|thumb|right|Digilent Analog Discovery]]

The [http://www.digilentinc.com/Products/Detail.cfm?Prod=ANALOG-DISCOVERY Digilent Analog Discovery] is a 100MSa/s oscilloscope, function generator, logic analyzer and pattern generator.

See [[Digilent Analog Discovery/Info]] for more details (such as '''lsusb -vvv''' output and FPGA I/O map) about the device.

== Hardware ==

PCB top side

* XC6SLX16 Xilinx Spartan 6 FPGA
* [http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9648/products/product.html AD9648BCPZ-125] 14-Bit 125 MSa/s ADC
* [http://www.analog.com/en/rfif-components/pll-synthesizersvcos/adf4360-9/products/product.html ADF4360-9] 65 to 400MHz VCO
* 2x [http://www.analog.com/en/specialty-amplifiers/differential-amplifiers/ada4940-2/products/product.html ADA4940-2ACPZ] ADC driver
* 2x [http://www.analog.com/en/switchesmultiplexers/analog-switches/adg612/products/product.html ADG612] CMOS switches
* 2x [http://www.analog.com/en/all-operational-amplifiers-op-amps/operational-amplifiers-op-amps/ad8066/products/product.html AD8066ARMZ] 145 MHz OpAmp
* FTDI FT232HQ USB-to-serial interface

PCB bottom side

* [http://www.analog.com/en/digital-to-analog-converters/high-speed-da-converters/ad9717/products/product.html AD9717BCPZ] 14-bit 125MSa/s DAC
* [http://www.analog.com/en/digital-to-analog-converters/da-converters/ad5645r/products/product.html AD5645R] Quad 14-bit DAC with I2C interface
* [http://www.analog.com/en/audiovideo-products/video-ampsbuffersfilters/ad8058/products/product.html AD8058ARM] 325 MHz amplifier (marking H8A)
* 2x [http://www.analog.com/en/all-operational-amplifiers-op-amps/operational-amplifiers-op-amps/ada4051-2/products/product.html AD4051-2] OpAmp (marking A2M)
* [http://www.analog.com/en/digital-to-analog-converters/da-converters/ad5623r/products/product.html AD5623R] Dual 12-bit DAC (marking D81)
* [http://www.analog.com/en/all-operational-amplifiers-op-amps/operational-amplifiers-op-amps/ad8591/products/product.html AD8591] OpAmp 250mA output current (marking AQA)
* 2x [http://www.analog.com/en/power-management/hot-swap/adm1177/products/product.html ADM1177-1] Hot swap controller (marking M5Y)

== Photos ==

<gallery>
File:Digilent_analog-discovery.jpg|Device, top
File:Digilent_analog-discovery_bottom.jpg|Device, bottom
File:Digilent_analog-discovery_front.jpg|Device, front
File:Digilent_analog-discovery_back.jpg|Device, back
File:Digilent_analog-discovery_bottom_no-feet.jpg|Device, bottom with rubber feet removed
File:Digilent_analog-discovery_pcb_front.jpg|PCB, top
File:Digilent_analog-discovery_pcb_back.jpg|PCB, bottom
</gallery>

== Protocol ==

WIP.

See [https://github.com/bvanheu/libsigrok-ad libsigrok-ad] project for the current effort.

Contact bvanheu at gmail dot com if you want to help.

== Resources ==

* [http://www.digilentinc.com/Data/Products/ANALOG-DISCOVERY/Analog%20Discovery_Pin-Out.pdf Pinout]
* [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,849&Prod=WAVEFORMS Vendor software]
** [http://www.digilentinc.com/Data/Documents/Product%20Documentation/WaveForms%20Overview.pdf Getting started guide]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Oscilloscope]]
[[Category:Mixed-signal oscilloscope]]
[[Category:Signal generator]]
[[Category:Planned]]

Digilent Analog Discovery/Info

2016-03-30T20:30:19Z

Cyrozap: Added initial FPGA pin map