From: Uwe Hermann <redacted>
Date: Sun, 21 Oct 2018 16:12:41 +0000 (+0200)
Subject: spiflash: Updates due to recent PD chages.
X-Git-Url: https://sigrok.org/gitweb/?p=sigrok-test.git;a=commitdiff_plain;h=3c35aaa05492cfa60c9482634987b50c5b7b2d38;hp=27130f5d421faf4f88ba60efe31100096bfa5b93;ds=sidebyside

spiflash: Updates due to recent PD chages.
---

diff --git a/decoder/test/spiflash/adesto_at45db161e_basic.output b/decoder/test/spiflash/adesto_at45db161e_basic.output
index c44c30b..23acf8c 100644
--- a/decoder/test/spiflash/adesto_at45db161e_basic.output
+++ b/decoder/test/spiflash/adesto_at45db161e_basic.output
@@ -6,6 +6,7 @@
 4256105-4256165 spiflash: bit: "Unknown command: 0x00"
 4256168-4256229 spiflash: bit: "Unknown command: 0x00"
 5895664-5895725 spiflash: field: "Command: Main memory page program through buffer 1 with built-in erase (WRITE1)" "Command: Main memory page program through buffer 1 with built-in erase" "Cmd: Main memory page program through buffer 1 with built-in erase" "Cmd: WRITE1" "WRITE1"
+5895664-4256102 spiflash: warning: "Warning: WREN might be missing"
 5895724-5895785 spiflash: bit: "Address bits 23..16: 0x04" "Addr bits 23..16: 0x04" "Addr bits 23..16" "A23..A16"
 5895784-5895844 spiflash: bit: "Address bits 15..8: 0x8c" "Addr bits 15..8: 0x8c" "Addr bits 15..8" "A15..A8"
 5895845-5895906 spiflash: bit: "Address bits 7..0: 0x00" "Addr bits 7..0: 0x00" "Addr bits 7..0" "A7..A0"
diff --git a/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output b/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output
index 50f9f85..4186414 100644
--- a/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output
+++ b/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output
@@ -7,3 +7,4 @@ Status register writes are allowed.
 "
 28-45 spiflash: field: "Status register"
 8-45 spiflash: rdsr: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
+66-84 spiflash: ce: "Command: Chip erase (CE)" "Command: Chip erase" "Cmd: Chip erase" "Cmd: CE" "CE"
diff --git a/decoder/test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output b/decoder/test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output
index 436b0a7..701f126 100644
--- a/decoder/test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output
+++ b/decoder/test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output
@@ -31,6 +31,7 @@ Status register writes are allowed.
 "
 631-648 spiflash: field: "Status register"
 611-648 spiflash: rdsr: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
+669-687 spiflash: ce: "Command: Chip erase (CE)" "Command: Chip erase" "Cmd: Chip erase" "Cmd: CE" "CE"
 712-729 spiflash: field: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
 733-750 spiflash: bit: "Write operation in progress.
 Internal write enable latch is set.