]> sigrok.org Git - sigrok-test.git/commitdiff
HD44780 dump has moved into display/ subdirectory
authorGerhard Sittig <redacted>
Sun, 20 Jan 2019 10:16:37 +0000 (11:16 +0100)
committerGerhard Sittig <redacted>
Sun, 20 Jan 2019 10:16:37 +0000 (11:16 +0100)
decoder/test/counter/test.conf
decoder/test/parallel/test.conf

index 89043548b8ebc86f39b8de77cc80f31235df2db2..179b2bd76a8b576fbe9f9caff82da68d8abafc46 100644 (file)
@@ -35,5 +35,5 @@ test nrf24l01_communication_tx_8bit_words_reset
 
 test hd44780_text_falling_reset
        protocol-decoder counter channel data=3 channel reset=1 option data_edge=falling option divider=2 option reset_edge=rising
 
 test hd44780_text_falling_reset
        protocol-decoder counter channel data=3 channel reset=1 option data_edge=falling option divider=2 option reset_edge=rising
-       input hd44780/hd44780-reset-init-hello.sr
+       input display/hd44780/hd44780-reset-init-hello.sr
        output counter annotation match hd44780_text_falling_reset.output
        output counter annotation match hd44780_text_falling_reset.output
index a28dd2d5f3f0ca23613b134a3b115e383379a283..1c650bb020159eb9c8b8961a17ff4b8a0d350bc1 100644 (file)
@@ -24,5 +24,5 @@ test incremental_8ch_long_clock
 
 test hd44780_word_demux
        protocol-decoder parallel channel clk=3 channel d0=4 channel d1=5 channel d2=6 channel d3=7 option clock_edge=falling option wordsize=2 option endianness=big
 
 test hd44780_word_demux
        protocol-decoder parallel channel clk=3 channel d0=4 channel d1=5 channel d2=6 channel d3=7 option clock_edge=falling option wordsize=2 option endianness=big
-       input hd44780/hd44780-reset-init-hello.sr
+       input display/hd44780/hd44780-reset-init-hello.sr
        output parallel annotation match hd44780_word_demux.output
        output parallel annotation match hd44780_word_demux.output