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(parent: e8483d8)

author	George Hopkins <redacted>
	Thu, 30 Nov 2017 16:19:12 +0000 (17:19 +0100)
committer	Uwe Hermann <redacted>
	Thu, 3 May 2018 14:09:46 +0000 (16:09 +0200)
commit	9f4051a592a9242ce885de80f8cec3c66f428ce4
tree	397f3a36b127fade36051ae40372387111e63895	tree \| snapshot
parent	e8483d893dff41ba9a411e2c9600d8e51610a435	commit \| diff

jtag: Fix shifting of registers

As reported in bug #1066, the decoding of IR/DR bits was incorrect.

12 files changed:

decoder/test/jtag/glyn_tonga2_idle.output		diff \| blob \| blame \| history
decoder/test/jtag/glyn_tonga2_idle.python		diff \| blob \| blame \| history
decoder/test/jtag/glyn_tonga2_irscan_drscan.output		diff \| blob \| blame \| history
decoder/test/jtag/glyn_tonga2_irscan_drscan.python		diff \| blob \| blame \| history
decoder/test/jtag/keil_mcb2140_idle.output		diff \| blob \| blame \| history
decoder/test/jtag/keil_mcb2140_idle.python		diff \| blob \| blame \| history
decoder/test/jtag/keil_mcb2140_irscan_drscan.output		diff \| blob \| blame \| history
decoder/test/jtag/keil_mcb2140_irscan_drscan.python		diff \| blob \| blame \| history
decoder/test/jtag/olimex_stm32-h103_idle.output		diff \| blob \| blame \| history
decoder/test/jtag/olimex_stm32-h103_idle.python		diff \| blob \| blame \| history
decoder/test/jtag/olimex_stm32-h103_irscan_drscan.output		diff \| blob \| blame \| history
decoder/test/jtag/olimex_stm32-h103_irscan_drscan.python		diff \| blob \| blame \| history

PD and in/out module tests