spiflash: Updates due to recent PD chages.

[sigrok-test.git] / decoder / test / spiflash / winbond_w25q80dv_chip_erase_and_writes_start.output

diff --git a/decoder/test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output b/decoder/test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output
index 436b0a77916b8c944ebcaa4c7777c00f02418b0c..701f1260c4a0fa576054acd0c792759c084a30f6 100644 (file)
--- a/decoder/test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output
+++ b/decoder/test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output
@@ -31,6 +31,7 @@ Status register writes are allowed.
 "
 631-648 spiflash: field: "Status register"
 611-648 spiflash: rdsr: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
+669-687 spiflash: ce: "Command: Chip erase (CE)" "Command: Chip erase" "Cmd: Chip erase" "Cmd: CE" "CE"
 712-729 spiflash: field: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
 733-750 spiflash: bit: "Write operation in progress.
 Internal write enable latch is set.