Add support for initial pin settings.

[sigrok-test.git] / decoder / test / parallel / test.conf

diff --git a/decoder/test/parallel/test.conf b/decoder/test/parallel/test.conf
index e894ee2738d1b9cd2459e8b7c5557dc0f17574af..cf59c30220a5babc49850bcc12ac9066cbd927fa 100644 (file)
--- a/decoder/test/parallel/test.conf
+++ b/decoder/test/parallel/test.conf
@@ -1,19 +1,23 @@
 test incremental_8ch_short_noclock
-       protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
+       protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 initial_pin d0=0 initial_pin d1=1 initial_pin d2=2
        input misc/demo/incremental_8ch_short.sr
        output parallel annotation match incremental_8ch_short_noclock.output
+       output parallel python match incremental_8ch_short_noclock.python
 
 test incremental_8ch_short_clock
        protocol-decoder parallel channel clk=0 channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
        input misc/demo/incremental_8ch_short.sr
        output parallel annotation match incremental_8ch_short_clock.output
+       output parallel python match incremental_8ch_short_clock.python
 
 test incremental_8ch_long_noclock
-       protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
+       protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 initial_pin d0=0 initial_pin d1=1 initial_pin d2=2
        input misc/demo/incremental_8ch_long.sr
        output parallel annotation match incremental_8ch_long_noclock.output
+       output parallel python match incremental_8ch_long_noclock.python
 
 test incremental_8ch_long_clock
        protocol-decoder parallel channel clk=0 channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
        input misc/demo/incremental_8ch_long.sr
        output parallel annotation match incremental_8ch_long_clock.output
+       output parallel python match incremental_8ch_long_clock.python