From: Uwe Hermann <redacted>
Date: Tue, 30 Apr 2019 17:17:10 +0000 (+0200)
Subject: Rename 2ch-16bit-16khz to 2ch-32bit-8khz.
X-Git-Url: https://sigrok.org/gitweb/?p=sigrok-dumps.git;a=commitdiff_plain;h=c7692e182af6f603db6511ebae5109723cab42f1

Rename 2ch-16bit-16khz to 2ch-32bit-8khz.

https://github.com/sigrokproject/libsigrokdecode/pull/6#issuecomment-442025810
---

diff --git a/i2s/2ch-16bit-16khz/2ch-16bit-16khz-no-samplerate.sr b/i2s/2ch-16bit-16khz/2ch-16bit-16khz-no-samplerate.sr
deleted file mode 100644
index 6db850e..0000000
Binary files a/i2s/2ch-16bit-16khz/2ch-16bit-16khz-no-samplerate.sr and /dev/null differ
diff --git a/i2s/2ch-16bit-16khz/2ch-16bit-16khz.sr b/i2s/2ch-16bit-16khz/2ch-16bit-16khz.sr
deleted file mode 100644
index 1975b87..0000000
Binary files a/i2s/2ch-16bit-16khz/2ch-16bit-16khz.sr and /dev/null differ
diff --git a/i2s/2ch-16bit-16khz/README b/i2s/2ch-16bit-16khz/README
deleted file mode 100644
index 7cf3a8c..0000000
--- a/i2s/2ch-16bit-16khz/README
+++ /dev/null
@@ -1,18 +0,0 @@
--------------------------------------------------------------------------------
-I2S Master 2-channel 16-bit 16-kHz
--------------------------------------------------------------------------------
-
-This is an example of an I2S master playing a recording of the BBC
-shipping forecast through one channel, and the other channel disconnected.
-
-Logic analyzer setup
---------------------
-
-The logic analyzer used was an EE Electronics ESLA201A (at 12MHz):
-
-  Probe       I2S pin
-  -------------------
-  0           Clock
-  1           Frame Select
-  2           Data
-
diff --git a/i2s/2ch-32bit-8khz/2ch-32bit-8khz-no-samplerate.sr b/i2s/2ch-32bit-8khz/2ch-32bit-8khz-no-samplerate.sr
new file mode 100644
index 0000000..6db850e
Binary files /dev/null and b/i2s/2ch-32bit-8khz/2ch-32bit-8khz-no-samplerate.sr differ
diff --git a/i2s/2ch-32bit-8khz/2ch-32bit-8khz.sr b/i2s/2ch-32bit-8khz/2ch-32bit-8khz.sr
new file mode 100644
index 0000000..1975b87
Binary files /dev/null and b/i2s/2ch-32bit-8khz/2ch-32bit-8khz.sr differ
diff --git a/i2s/2ch-32bit-8khz/README b/i2s/2ch-32bit-8khz/README
new file mode 100644
index 0000000..c629dc4
--- /dev/null
+++ b/i2s/2ch-32bit-8khz/README
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+I2S Master 2-channel 32-bit 8-kHz
+-------------------------------------------------------------------------------
+
+This is an example of an I2S master playing a recording of the BBC
+shipping forecast through one channel, and the other channel disconnected.
+
+
+Logic analyzer setup
+--------------------
+
+The logic analyzer used was an EE Electronics ESLA201A (at 12MHz):
+
+  Probe       I2S pin
+  -------------------
+  0           Clock
+  1           Frame Select
+  2           Data