From: Jiahao Li <redacted>
Date: Wed, 20 Feb 2019 23:12:56 +0000 (-0500)
Subject: enc28j60: Adds trace and README
X-Git-Url: https://sigrok.org/gitweb/?p=sigrok-dumps.git;a=commitdiff_plain;h=8a05fd71d8881f3d898ff9bfac8867516f07ecad

enc28j60: Adds trace and README
---

diff --git a/spi/enc28j60/README b/spi/enc28j60/README
new file mode 100644
index 0000000..47d0415
--- /dev/null
+++ b/spi/enc28j60/README
@@ -0,0 +1,35 @@
+-------------------------------------------------------------------------------
+Microchip ENC28J60
+-------------------------------------------------------------------------------
+
+This is an example capture of the Microchip ENC28J60 SPI Ethernet chip.
+
+Details:
+http://ww1.microchip.com/downloads/en/DeviceDoc/39662e.pdf
+
+
+enc28j60-init-and-ping.sr
+-------------------------
+
+Capture contains the following 3 stages:
+
+1) Initialization phase where control registers are written.
+2) Polling phase that waits for the Ethernet link to be up.
+3) Two round-trips of ping packets (each consists of 1 RX of ICMP Echo Request
+   packet and 1 TX of ICMP Echo Reply packet).
+
+The chip was driven by a custom STM32F446 board running custom bare-metal
+firmware.
+
+
+Logic analyzer setup
+--------------------
+
+The logic analyzer used was a DSLogic Plus (at 50MHz, with SPI clock at 16MHz):
+
+  Probe       ENC28J60
+  --------------------
+  0           CS#
+  1           MISO
+  2           CLK
+  3           MOSI
diff --git a/spi/enc28j60/enc28j60-init-and-ping.sr b/spi/enc28j60/enc28j60-init-and-ping.sr
new file mode 100644
index 0000000..f1ce818
Binary files /dev/null and b/spi/enc28j60/enc28j60-init-and-ping.sr differ