From: Gerhard Sittig <redacted>
Date: Mon, 22 Jun 2020 18:13:15 +0000 (+0200)
Subject: pjon/pjdl: add capture of minimal PJON frames over PJDL link layer
X-Git-Url: https://sigrok.org/gitweb/?p=sigrok-dumps.git;a=commitdiff_plain;h=55a8021ad31e5b7e746dc71e9b71041920e62f17

pjon/pjdl: add capture of minimal PJON frames over PJDL link layer

The PJON protocol can use several link layers. These captures run on
PJDL, demonstrate a minimal PJON frame (with TX info) and a response.
And also contain a few exceptional conditions: Glitches in the signal,
outside and inside of frames. Lack of recipient's response, too.

The snippets were extracted from a capture that was
Submitted-By: Julio Aguirre <redacted>
---

diff --git a/pjon/README b/pjon/README
new file mode 100644
index 0000000..507bcd4
--- /dev/null
+++ b/pjon/README
@@ -0,0 +1,10 @@
+-------------------------------------------------------------------------------
+PJON protocol stack, project homepage https://www.pjon.org/
+-------------------------------------------------------------------------------
+
+This is a collection of example PJON communication. Subdirectories contain
+different types of communication (link layers, or setups).
+
+PJON protocol and PJDL link layer specs:
+https://www.pjon.org/PJON-protocol-specification-v3.2.php
+https://www.pjon.org/PJDL-specification-v4.1.php
diff --git a/pjon/pjdl/README b/pjon/pjdl/README
new file mode 100644
index 0000000..25423e9
--- /dev/null
+++ b/pjon/pjdl/README
@@ -0,0 +1,40 @@
+-------------------------------------------------------------------------------
+PJON over PJDL
+-------------------------------------------------------------------------------
+
+This is a collection of example PJON communication which uses the PJDL
+link layer. Which does serial communication on a single wire, and the
+reference library happens to implement it by means of software bitbang
+(which affects the timing of signals on the wire).
+
+
+Logic analyzer setup
+--------------------
+
+The capture was taken with a logic analyzer at a samplerate of 4MSa/s.
+Communication is done on a single channel.
+
+  Probe       PJDL
+  ----------------
+  1           data
+
+
+pjon-pjdl-glitch-and-ack-and-failed-ack.sr
+------------------------------------------
+
+Two STM32F103 (Blue Pill boards) run the example code which resides in
+the examples/ARDUINO/Local/SoftwareBitBang/SendAndReceive/Device1/ and
+Device2/ directories. Communication mode 1 translates to 44us and 116us
+for data and pad bits. Device addresses are 44 and 45. The letter 'B' is
+sent as the payload data in both directions. Synchronous responses get
+requested, but one device won't respond. The capture also contains a few
+glitches which as a byproduct exercise the decoder's robustness, and
+recovery after synchronization loss.
+
+
+pjon-pjdl-incomplete-frame-missing-ack-repetitive.sr
+----------------------------------------------------
+
+This is a longer capture taken from the above setup. Some of the glitches
+happen to fall into a PJON frame's period and can prevent or can disturb
+the accumulation of the frame's content.
diff --git a/pjon/pjdl/pjon-pjdl-glitch-and-ack-and-failed-ack.sr b/pjon/pjdl/pjon-pjdl-glitch-and-ack-and-failed-ack.sr
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diff --git a/pjon/pjdl/pjon-pjdl-incomplete-frame-missing-ack-repetitive.sr b/pjon/pjdl/pjon-pjdl-incomplete-frame-missing-ack-repetitive.sr
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index 0000000..c6aaf62
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