X-Git-Url: https://sigrok.org/gitweb/?p=sigrok-dumps.git;a=blobdiff_plain;f=avr_isp%2Fatmega8L%2FREADME.txt;fp=avr_isp%2Fatmega8L%2FREADME.txt;h=af488634c6787d777481cfa188f5e9846ad14f43;hp=0000000000000000000000000000000000000000;hb=547a4b120781451d6b51ddb3fb66cbcf44b61380;hpb=9a81ff1295e2b278c63098750c9ef101f563f52b diff --git a/avr_isp/atmega8L/README.txt b/avr_isp/atmega8L/README.txt new file mode 100644 index 0000000..af48863 --- /dev/null +++ b/avr_isp/atmega8L/README.txt @@ -0,0 +1,22 @@ +------------------------------------------------------------------------------- +AVR ISP / Atmel ATmega8L +------------------------------------------------------------------------------- + +This is a set of example captures of the AVR in-system programming (ISP) +protocol. The target was a board with an Atmel ATmega8L chip, and another +microcontroller was used as master for the ISP process. + +Details: +http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2486-8-bit-AVR-microcontroller-ATmega8_L_datasheet.pdf + + +Logic analyzer setup +-------------------- + +The logic analyzer used was a Saleae Logic (at 4MHz): + + Probe AVR ISP header + ------------------------- + 5 (green) MOSI + 6 (blue) CLK + 7 (violet) MOSI