From: Soeren Apel <redacted>
Date: Wed, 3 Jan 2018 16:14:51 +0000 (+0100)
Subject: LogicSegment: Limit end in get_subsampled_edges() if needed
X-Git-Url: https://sigrok.org/gitweb/?p=pulseview.git;a=commitdiff_plain;h=4cc0df94c1027add1e62dfdf81e48eda959783c9;ds=sidebyside

LogicSegment: Limit end in get_subsampled_edges() if needed

This is necessary because there is a race condition between
adding samples and trace repainting.
---

diff --git a/pv/data/logicsegment.cpp b/pv/data/logicsegment.cpp
index dff99c01..62f188e3 100644
--- a/pv/data/logicsegment.cpp
+++ b/pv/data/logicsegment.cpp
@@ -314,7 +314,6 @@ void LogicSegment::get_subsampled_edges(
 	bool last_sample;
 	bool fast_forward;
 
-	assert(end <= get_sample_count());
 	assert(start <= end);
 	assert(min_length > 0);
 	assert(sig_index >= 0);
@@ -322,6 +321,10 @@ void LogicSegment::get_subsampled_edges(
 
 	lock_guard<recursive_mutex> lock(mutex_);
 
+	// Make sure we only process as many samples as we have
+	if (end > get_sample_count())
+		end = get_sample_count();
+
 	const uint64_t block_length = (uint64_t)max(min_length, 1.0f);
 	const unsigned int min_level = max((int)floorf(logf(min_length) /
 		LogMipMapScaleFactor) - 1, 0);