X-Git-Url: https://sigrok.org/gitweb/?p=pulseview.git;a=blobdiff_plain;f=test%2Flogicdatasnapshot.cpp;h=4e31bfae8f0a1d21fb10e324043f6f17fb9307b3;hp=5041c1b327bf689c2a0fa3ecb74c70447d44ab9e;hb=b3f22de060b73f15ad3eb2dabee04a0b4f5d947e;hpb=4f767cf7100023341f94fa9f0d1befc5101c3d6d diff --git a/test/logicdatasnapshot.cpp b/test/logicdatasnapshot.cpp index 5041c1b3..4e31bfae 100644 --- a/test/logicdatasnapshot.cpp +++ b/test/logicdatasnapshot.cpp @@ -1,5 +1,5 @@ /* - * This file is part of the sigrok project. + * This file is part of the PulseView project. * * Copyright (C) 2012 Joel Holdsworth * @@ -23,6 +23,7 @@ #include +#include "../extdef.h" #include "../logicdatasnapshot.h" using namespace std; @@ -254,8 +255,8 @@ BOOST_AUTO_TEST_CASE(LargeData) } //----- Test LogicDataSnapshot::get_subsampled_edges -----// + // Check in normal case vector edges; - s.get_subsampled_edges(edges, 0, Length-1, 1, 7); BOOST_CHECK_EQUAL(edges.size(), 32); @@ -267,6 +268,12 @@ BOOST_AUTO_TEST_CASE(LargeData) } BOOST_CHECK_EQUAL(edges[31].first, 999999); + + // Check in very low zoom case + edges.clear(); + s.get_subsampled_edges(edges, 0, Length-1, 50e6f, 7); + + BOOST_CHECK_EQUAL(edges.size(), 2); } BOOST_AUTO_TEST_CASE(Pulses) @@ -419,4 +426,52 @@ BOOST_AUTO_TEST_CASE(LongPulses) BOOST_CHECK_EQUAL(edges.back().second, false); } +BOOST_AUTO_TEST_CASE(LisaMUsbHid) +{ + /* This test was created from the beginning of the USB_DM signal in + * sigrok-dumps-usb/lisa_m_usbhid/lisa_m_usbhid.sr + */ + + const int Edges[] = { + 7028, 7033, 7036, 7041, 7044, 7049, 7053, 7066, 7073, 7079, + 7086, 7095, 7103, 7108, 7111, 7116, 7119, 7124, 7136, 7141, + 7148, 7162, 7500 + }; + const int Length = Edges[countof(Edges) - 1]; + + bool state = false; + int lastEdgePos = 0; + + //----- Create a LogicDataSnapshot -----// + sr_datafeed_logic logic; + logic.unitsize = 1; + logic.length = Length; + logic.data = new uint8_t[Length]; + uint8_t *data = (uint8_t*)logic.data; + + for(int i = 0; i < countof(Edges); i++) { + const int edgePos = Edges[i]; + memset(&data[lastEdgePos], state ? 0x02 : 0, + edgePos - lastEdgePos - 1); + + lastEdgePos = edgePos; + state = !state; + } + + LogicDataSnapshot s(logic); + delete[] (uint64_t*)logic.data; + + vector edges; + + + /* The trailing edge of the pulse train is falling in the source data. + * Check this is always true at different scales + */ + + edges.clear(); + s.get_subsampled_edges(edges, 0, Length-1, 33.333332f, 1); + BOOST_CHECK_EQUAL(edges[edges.size() - 2].second, false); +} + + BOOST_AUTO_TEST_SUITE_END()