X-Git-Url: https://sigrok.org/gitweb/?p=pulseview.git;a=blobdiff_plain;f=pv%2Fdata%2Flogicsegment.cpp;h=fcf572297e689f87762eabc81df96207df3000dc;hp=1e66e364c7f6cfe2f71a3f6ea5ae64a1d5b17dc0;hb=9d22929c3588b994771e8db8f3be5b013fd35040;hpb=eb8269e3b5eebdd77e6a82d42bcfdfbc3f7613a9;ds=sidebyside

diff --git a/pv/data/logicsegment.cpp b/pv/data/logicsegment.cpp
index 1e66e364..fcf57229 100644
--- a/pv/data/logicsegment.cpp
+++ b/pv/data/logicsegment.cpp
@@ -35,6 +35,7 @@ using std::max;
 using std::min;
 using std::pair;
 using std::shared_ptr;
+using std::vector;
 
 using sigrok::Logic;
 
@@ -57,6 +58,15 @@ LogicSegment::LogicSegment(pv::data::Logic& owner, shared_ptr<sigrok::Logic> dat
 	append_payload(data);
 }
 
+LogicSegment::LogicSegment(pv::data::Logic& owner, unsigned int unit_size,
+	uint64_t samplerate) :
+	Segment(samplerate, unit_size),
+	owner_(owner),
+	last_append_sample_(0)
+{
+	memset(mip_map_, 0, sizeof(mip_map_));
+}
+
 LogicSegment::~LogicSegment()
 {
 	lock_guard<recursive_mutex> lock(mutex_);
@@ -143,12 +153,19 @@ void LogicSegment::append_payload(shared_ptr<sigrok::Logic> logic)
 	assert(unit_size_ == logic->unit_size());
 	assert((logic->data_length() % unit_size_) == 0);
 
+	append_payload(logic->data_pointer(), logic->data_length());
+}
+
+void LogicSegment::append_payload(void *data, uint64_t data_size)
+{
+	assert((data_size % unit_size_) == 0);
+
 	lock_guard<recursive_mutex> lock(mutex_);
 
 	uint64_t prev_sample_count = sample_count_;
-	uint64_t sample_count = logic->data_length() / unit_size_;
+	uint64_t sample_count = data_size / unit_size_;
 
-	append_samples(logic->data_pointer(), sample_count);
+	append_samples(data, sample_count);
 
 	// Generate the first mip-map from the data
 	append_payload_to_mipmap();
@@ -298,7 +315,7 @@ uint64_t LogicSegment::get_unpacked_sample(uint64_t index) const
 }
 
 void LogicSegment::get_subsampled_edges(
-	std::vector<EdgePair> &edges,
+	vector<EdgePair> &edges,
 	uint64_t start, uint64_t end,
 	float min_length, int sig_index)
 {
@@ -322,7 +339,7 @@ void LogicSegment::get_subsampled_edges(
 
 	// Store the initial state
 	last_sample = (get_unpacked_sample(start) & sig_mask) != 0;
-	edges.push_back(pair<int64_t, bool>(index++, last_sample));
+	edges.emplace_back(index++, last_sample);
 
 	while (index + block_length <= end) {
 		//----- Continue to search -----//
@@ -376,7 +393,7 @@ void LogicSegment::get_subsampled_edges(
 
 			// Slide right and zoom out at the beginnings of mip-map
 			// blocks until we encounter a change
-			while (1) {
+			while (true) {
 				const int level_scale_power =
 					(level + 1) * MipMapScalePower;
 				const uint64_t offset =
@@ -408,7 +425,7 @@ void LogicSegment::get_subsampled_edges(
 
 			// Zoom in, and slide right until we encounter a change,
 			// and repeat until we reach min_level
-			while (1) {
+			while (true) {
 				assert(mip_map_[level].data);
 
 				const int level_scale_power =
@@ -458,7 +475,7 @@ void LogicSegment::get_subsampled_edges(
 		// Store the final state
 		const bool final_sample =
 			(get_unpacked_sample(final_index - 1) & sig_mask) != 0;
-		edges.push_back(pair<int64_t, bool>(index, final_sample));
+		edges.emplace_back(index, final_sample);
 
 		index = final_index;
 		last_sample = final_sample;
@@ -467,8 +484,8 @@ void LogicSegment::get_subsampled_edges(
 	// Add the final state
 	const bool end_sample = get_unpacked_sample(end) & sig_mask;
 	if (last_sample != end_sample)
-		edges.push_back(pair<int64_t, bool>(end, end_sample));
-	edges.push_back(pair<int64_t, bool>(end + 1, end_sample));
+		edges.emplace_back(end, end_sample);
+	edges.emplace_back(end + 1, end_sample);
 }
 
 uint64_t LogicSegment::get_subsample(int level, uint64_t offset) const