X-Git-Url: https://sigrok.org/gitweb/?p=pulseview.git;a=blobdiff_plain;f=pv%2Fdata%2Flogicsegment.cpp;h=739b2b9ee2a97652de2d4d4e3530041c1613af2c;hp=d000922787daf1346307738658d25f5e3288bac6;hb=HEAD;hpb=4f654de1ecd97104164419985ab31ea83bf9daef

diff --git a/pv/data/logicsegment.cpp b/pv/data/logicsegment.cpp
index d0009227..739b2b9e 100644
--- a/pv/data/logicsegment.cpp
+++ b/pv/data/logicsegment.cpp
@@ -363,6 +363,31 @@ void LogicSegment::append_payload(void *data, uint64_t data_size)
 			prev_sample_count + 1, prev_sample_count + 1);
 }
 
+void LogicSegment::append_subsignal_payload(unsigned int index, void *data,
+	uint64_t data_size, vector<uint8_t>& destination)
+{
+	if (index == 0)
+		destination.resize(data_size * unit_size_, 0);
+
+	// Set the bits for this sub-signal where needed
+	// Note: the bytes in *data must either be 0 or 1, nothing else
+	unsigned int index_byte_offs = index / 8;
+	uint8_t* output_data = destination.data() + index_byte_offs;
+	uint8_t* input_data = (uint8_t*)data;
+
+	for (uint64_t i = 0; i < data_size; i++) {
+		assert((i * unit_size_ + index_byte_offs) < destination.size());
+		*output_data |= (input_data[i] << index);
+		output_data += unit_size_;
+	}
+
+	if (index == owner_.num_channels() - 1) {
+		// We gathered sample data of all sub-signals, let's append it
+		append_payload(destination.data(), destination.size());
+		destination.clear();
+	}
+}
+
 void LogicSegment::get_samples(int64_t start_sample,
 	int64_t end_sample, uint8_t* dest) const
 {